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author | Dan Gohman <gohman@apple.com> | 2008-07-07 23:14:23 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2008-07-07 23:14:23 +0000 |
commit | 8e5f2c6f65841542e2a7092553fe42a00048e4c7 (patch) | |
tree | 24fe54b796f3f450ba6aff12b7357068ca66e341 /lib/Target/PowerPC/PPCISelLowering.cpp | |
parent | 0e5f1306b059b62d7725f324e087efbc8e7a782d (diff) | |
download | external_llvm-8e5f2c6f65841542e2a7092553fe42a00048e4c7.zip external_llvm-8e5f2c6f65841542e2a7092553fe42a00048e4c7.tar.gz external_llvm-8e5f2c6f65841542e2a7092553fe42a00048e4c7.tar.bz2 |
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index d44dc5d..4650ad7 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -3992,7 +3992,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // to set, the condition code register to branch on, the true/false values to // select between, and a branch opcode to use. const BasicBlock *LLVM_BB = BB->getBasicBlock(); - ilist<MachineBasicBlock>::iterator It = BB; + MachineFunction::iterator It = BB; ++It; // thisMBB: @@ -4002,14 +4002,14 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // bCC copy1MBB // fallthrough --> copy0MBB MachineBasicBlock *thisMBB = BB; - MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); - MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); + MachineFunction *F = BB->getParent(); + MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); unsigned SelectPred = MI->getOperand(4).getImm(); BuildMI(BB, TII->get(PPC::BCC)) .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); - MachineFunction *F = BB->getParent(); - F->getBasicBlockList().insert(It, copy0MBB); - F->getBasicBlockList().insert(It, sinkMBB); + F->insert(It, copy0MBB); + F->insert(It, sinkMBB); // Update machine-CFG edges by transferring all successors of the current // block to the new block which will contain the Phi node for the select. sinkMBB->transferSuccessors(BB); @@ -4033,7 +4033,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); - delete MI; // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } |