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| author | Hal Finkel <hfinkel@anl.gov> | 2013-05-20 16:08:37 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-05-20 16:08:37 +0000 |
| commit | 85c08b059ce4248ee739e756cf717a9b429e2ec2 (patch) | |
| tree | b3c8f9746e54bb4d2b9f185f8752d1548542f1fb /lib/Target | |
| parent | e50c8c1f81a38f0ecebafa5dc60a163814a9713a (diff) | |
| download | external_llvm-85c08b059ce4248ee739e756cf717a9b429e2ec2.zip external_llvm-85c08b059ce4248ee739e756cf717a9b429e2ec2.tar.gz external_llvm-85c08b059ce4248ee739e756cf717a9b429e2ec2.tar.bz2 | |
Rename PPC MTCTRse to MTCTRloop
As the pairing of this instruction form with the bdnz/bdz branches is now
enforced by the verification pass, make it clear from the name that these
are used only for counter-based loops.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182296 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/PowerPC/PPCCTRLoops.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstr64Bit.td | 6 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 6 |
3 files changed, 7 insertions, 7 deletions
diff --git a/lib/Target/PowerPC/PPCCTRLoops.cpp b/lib/Target/PowerPC/PPCCTRLoops.cpp index d36fec0..124d778 100644 --- a/lib/Target/PowerPC/PPCCTRLoops.cpp +++ b/lib/Target/PowerPC/PPCCTRLoops.cpp @@ -627,7 +627,7 @@ check_block: CheckPreds = true; for (MachineBasicBlock::iterator IE = MBB->begin();; --I) { unsigned Opc = I->getOpcode(); - if (Opc == PPC::MTCTRse || Opc == PPC::MTCTR8se) { + if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) { CheckPreds = false; break; } diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index c1071b1..7544c5c 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -295,9 +295,9 @@ def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), } let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in { let Pattern = [(int_ppc_mtctr i64:$rS)] in -def MTCTR8se : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), - "mtctr $rS", SprMTSPR>, - PPC970_DGroup_First, PPC970_Unit_FXU; +def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), + "mtctr $rS", SprMTSPR>, + PPC970_DGroup_First, PPC970_Unit_FXU; } let Pattern = [(set i64:$rT, readcyclecounter)] in diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 16a102f..2631cb7 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -1704,9 +1704,9 @@ def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), } let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in { let Pattern = [(int_ppc_mtctr i32:$rS)] in -def MTCTRse : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), - "mtctr $rS", SprMTSPR>, - PPC970_DGroup_First, PPC970_Unit_FXU; +def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), + "mtctr $rS", SprMTSPR>, + PPC970_DGroup_First, PPC970_Unit_FXU; } let Defs = [LR] in { |