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authorChris Lattner <sabre@nondot.org>2010-08-27 22:53:44 +0000
committerChris Lattner <sabre@nondot.org>2010-08-27 22:53:44 +0000
commit5275ba2e7da02086fb9f757f14c5adf1e65a94ae (patch)
tree409b539215f3192ae9c1676a89f5ffd5cbcfb8a1 /lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
parent8cd320aab9573cbba94c7bcfdd33b43306fff024 (diff)
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Enhance the shift propagator to handle the case when you have:
A = shl x, 42 ... B = lshr ..., 38 which can be transformed into: A = shl x, 4 ... iff we can prove that the would-be-shifted-in bits are already zero. This eliminates two shifts in the testcase and allows eliminate of the whole i128 chain in the real example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112314 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Transforms/InstCombine/InstCombineMulDivRem.cpp')
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