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authorEli Friedman <eli.friedman@gmail.com>2009-08-19 08:46:10 +0000
committerEli Friedman <eli.friedman@gmail.com>2009-08-19 08:46:10 +0000
commit67ebebabfb0a1879a297abbcd979dee1065111c6 (patch)
tree8905a2711909abba1b9214b7d5a03fc07ba5b1b9 /lib
parent4a9c9df62c661e3d7917296a5052fd11ee7e053d (diff)
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PR4737: Fix a nasty bug in load narrowing with non-power-of-two types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79415 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 3c4f9de..4138e98 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3466,7 +3466,8 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
// Is the shift amount a multiple of size of VT?
if ((ShAmt & (EVTBits-1)) == 0) {
N0 = N0.getOperand(0);
- if (N0.getValueType().getSizeInBits() <= EVTBits)
+ // Is the load width a multiple of size of VT?
+ if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
return SDValue();
}
}