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| author | Andrew Trick <atrick@apple.com> | 2012-06-05 03:44:29 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-06-05 03:44:29 +0000 |
| commit | d05b46115f5049b7b094d4049aa88f09f7d6b65a (patch) | |
| tree | 35b2941580395ab98188cdce1a9fd5b7fafcc6e1 /lib | |
| parent | 76e9e838a143a12fdf119ecd01919936a437b5a2 (diff) | |
| download | external_llvm-d05b46115f5049b7b094d4049aa88f09f7d6b65a.zip external_llvm-d05b46115f5049b7b094d4049aa88f09f7d6b65a.tar.gz external_llvm-d05b46115f5049b7b094d4049aa88f09f7d6b65a.tar.bz2 | |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157976 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86Schedule.td | 5 | ||||
| -rw-r--r-- | lib/Target/X86/X86ScheduleAtom.td | 2 |
2 files changed, 2 insertions, 5 deletions
diff --git a/lib/Target/X86/X86Schedule.td b/lib/Target/X86/X86Schedule.td index dc311b1..f670f28 100644 --- a/lib/Target/X86/X86Schedule.td +++ b/lib/Target/X86/X86Schedule.td @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// Instruction Itinerary classes used for X86 +// Instruction Itinerary classes used for X86 def IIC_DEFAULT : InstrItinClass; def IIC_ALU_MEM : InstrItinClass; def IIC_ALU_NONMEM : InstrItinClass; @@ -459,6 +459,3 @@ def IIC_NOP : InstrItinClass; def GenericItineraries : ProcessorItineraries<[], [], []>; include "X86ScheduleAtom.td" - - - diff --git a/lib/Target/X86/X86ScheduleAtom.td b/lib/Target/X86/X86ScheduleAtom.td index 9732204..81530b5 100644 --- a/lib/Target/X86/X86ScheduleAtom.td +++ b/lib/Target/X86/X86ScheduleAtom.td @@ -106,7 +106,7 @@ def AtomItineraries : ProcessorItineraries< InstrItinData<IIC_CMOV64_RM, [InstrStage<1, [Port0]>] >, InstrItinData<IIC_CMOV64_RR, [InstrStage<1, [Port0, Port1]>] >, // set - InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >, + InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >, InstrItinData<IIC_SET_R, [InstrStage<1, [Port0, Port1]>] >, // jcc InstrItinData<IIC_Jcc, [InstrStage<1, [Port1]>] >, |