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| author | Joel Jones <joel_k_jones@apple.com> | 2012-07-13 23:25:25 +0000 |
|---|---|---|
| committer | Joel Jones <joel_k_jones@apple.com> | 2012-07-13 23:25:25 +0000 |
| commit | 06a6a300c5f7100e4665667c689369e078d2ad59 (patch) | |
| tree | f521fdce2377d82a92551246d1519630814ca136 /test/Bitcode | |
| parent | cb41e5f6f28da51e37eb072e4bf69143fe29dacc (diff) | |
| download | external_llvm-06a6a300c5f7100e4665667c689369e078d2ad59.zip external_llvm-06a6a300c5f7100e4665667c689369e078d2ad59.tar.gz external_llvm-06a6a300c5f7100e4665667c689369e078d2ad59.tar.bz2 | |
This is one of the first steps at moving to replace target-dependent
intrinsics with target-indepdent intrinsics. The first instruction(s) to be
handled are the vector versions of count leading zeros (ctlz).
The changes here are to clang so that it generates a target independent
vector ctlz when it sees an ARM dependent vector ctlz. The changes in llvm
are to match the target independent vector ctlz and in VMCore/AutoUpgrade.cpp
to update any existing bc files containing ARM dependent vector ctlzs with
target-independent ctlzs. There are also changes to an existing test case in
llvm for ARM vector count instructions and a new test for the bitcode upgrade.
<rdar://problem/11831778>
There is deliberately no test for the change to clang, as so far as I know, no
consensus has been reached regarding how to test neon instructions in clang;
q.v. <rdar://problem/8762292>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160200 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Bitcode')
| -rw-r--r-- | test/Bitcode/arm32_neon_vcnt_upgrade.ll | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/test/Bitcode/arm32_neon_vcnt_upgrade.ll b/test/Bitcode/arm32_neon_vcnt_upgrade.ll new file mode 100644 index 0000000..b3f2f03 --- /dev/null +++ b/test/Bitcode/arm32_neon_vcnt_upgrade.ll @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; NB: currently tests only vclz, should also test vcnt and vcls + +define <4 x i16> @vclz16(<4 x i16>* %A) nounwind { +;CHECK: @vclz16 + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1) +;CHECK: {{call.*@llvm.ctlz.v4i16\(<4 x i16>.*, i1 false}} + ret <4 x i16> %tmp2 +} + +declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone |