diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2012-10-02 23:49:13 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2012-10-02 23:49:13 +0000 |
| commit | 2b87e06d265e83d61873075e8f8e9c51430ff332 (patch) | |
| tree | 7e5ba8eb7c9b2ef26b7ccfd88f10e87760243d5d /test | |
| parent | 394820b8e159a39a9a07aac9722ad8738680037d (diff) | |
| download | external_llvm-2b87e06d265e83d61873075e8f8e9c51430ff332.zip external_llvm-2b87e06d265e83d61873075e8f8e9c51430ff332.tar.gz external_llvm-2b87e06d265e83d61873075e8f8e9c51430ff332.tar.bz2 | |
Fix a serious X86 instruction selection bug. In
X86DAGToDAGISel::PreprocessISelDAG(), isel is moving load inside
callseq_start / callseq_end so it can be folded into a call. This can
create a cycle in the DAG when the call is glued to a copytoreg. We
have been lucky this hasn't caused too many issues because the pre-ra
scheduler has special handling of call sequences. However, it has
caused a crash in a specific tailcall case.
rdar://12393897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165072 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/X86/2012-10-02-DAGCycle.ll | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/test/CodeGen/X86/2012-10-02-DAGCycle.ll b/test/CodeGen/X86/2012-10-02-DAGCycle.ll new file mode 100644 index 0000000..9d2b7ea --- /dev/null +++ b/test/CodeGen/X86/2012-10-02-DAGCycle.ll @@ -0,0 +1,16 @@ +; RUN: llc -mtriple=i386-apple-macosx -relocation-model=pic < %s +; rdar://12393897 + +%TRp = type { i32, %TRH*, i32, i32 } +%TRH = type { i8*, i8*, i8*, i8*, {}* } + +define i32 @t(%TRp* inreg %rp) nounwind optsize ssp { +entry: + %handler = getelementptr inbounds %TRp* %rp, i32 0, i32 1 + %0 = load %TRH** %handler, align 4 + %sync = getelementptr inbounds %TRH* %0, i32 0, i32 4 + %sync12 = load {}** %sync, align 4 + %1 = bitcast {}* %sync12 to i32 (%TRp*)* + %call = tail call i32 %1(%TRp* inreg %rp) nounwind optsize + ret i32 %call +} |