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-rw-r--r--lib/Target/R600/SIInstrInfo.td12
-rw-r--r--lib/Target/R600/SIInstructions.td7
-rw-r--r--test/CodeGen/R600/fconst64.ll12
3 files changed, 31 insertions, 0 deletions
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
index 655a8b1..067a34b 100644
--- a/lib/Target/R600/SIInstrInfo.td
+++ b/lib/Target/R600/SIInstrInfo.td
@@ -21,11 +21,23 @@ def LO32 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
}]>;
+def LO32f : SDNodeXForm<fpimm, [{
+ uint64_t val = N->getValueAPF().bitcastToAPInt().getZExtValue() & 0xffffffff;
+ float *fval = reinterpret_cast<float *>(&val);
+ return CurDAG->getTargetConstantFP(*fval, MVT::f32);
+}]>;
+
// Transformation function, extract the upper 32bit of a 64bit immediate
def HI32 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
}]>;
+def HI32f : SDNodeXForm<fpimm, [{
+ uint64_t val = N->getValueAPF().bitcastToAPInt().getZExtValue() >> 32;
+ float *fval = reinterpret_cast<float *>(&val);
+ return CurDAG->getTargetConstantFP(*fval, MVT::f32);
+}]>;
+
def IMM8bitDWORD : ImmLeaf <
i32, [{
return (Imm & ~0x3FC) == 0;
diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
index 8436b67..3deaa2e 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -1509,6 +1509,13 @@ def : Pat <
(S_MOV_B32 (i32 (HI32 imm:$imm))), sub1)
>;
+def : Pat <
+ (f64 fpimm:$imm),
+ (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
+ (V_MOV_B32_e32 (f32 (LO32f fpimm:$imm))), sub0),
+ (V_MOV_B32_e32 (f32 (HI32f fpimm:$imm))), sub1)
+>;
+
/********** ===================== **********/
/********** Interpolation Paterns **********/
/********** ===================== **********/
diff --git a/test/CodeGen/R600/fconst64.ll b/test/CodeGen/R600/fconst64.ll
new file mode 100644
index 0000000..2402a9c
--- /dev/null
+++ b/test/CodeGen/R600/fconst64.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s
+
+; CHECK: @fconst_f64
+; CHECK: V_MOV_B32_e32 {{VGPR[0-9]+}}, 0.000000e+00
+; CHECK-NEXT: V_MOV_B32_e32 {{VGPR[0-9]+}}, 2.312500e+00
+
+define void @fconst_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
+ %r1 = load double addrspace(1)* %in
+ %r2 = fadd double %r1, 5.000000e+00
+ store double %r2, double addrspace(1)* %out
+ ret void
+}