diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 8 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/fnegsel.ll | 2 |
2 files changed, 1 insertions, 9 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 9472cee..5c69085 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2734,20 +2734,16 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { switch (CC) { default: break; // SETUO etc aren't handled by fsel. case ISD::SETULT: - case ISD::SETOLT: case ISD::SETLT: std::swap(TV, FV); // fsel is natively setge, swap operands for setlt - case ISD::SETUGE: case ISD::SETOGE: case ISD::SETGE: if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); case ISD::SETUGT: - case ISD::SETOGT: case ISD::SETGT: std::swap(TV, FV); // fsel is natively setge, swap operands for setlt - case ISD::SETULE: case ISD::SETOLE: case ISD::SETLE: if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits @@ -2760,13 +2756,11 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { switch (CC) { default: break; // SETUO etc aren't handled by fsel. case ISD::SETULT: - case ISD::SETOLT: case ISD::SETLT: Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); - case ISD::SETUGE: case ISD::SETOGE: case ISD::SETGE: Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); @@ -2774,13 +2768,11 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); case ISD::SETUGT: - case ISD::SETOGT: case ISD::SETGT: Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); - case ISD::SETULE: case ISD::SETOLE: case ISD::SETLE: Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); diff --git a/test/CodeGen/PowerPC/fnegsel.ll b/test/CodeGen/PowerPC/fnegsel.ll index c223a49..62ed4dd 100644 --- a/test/CodeGen/PowerPC/fnegsel.ll +++ b/test/CodeGen/PowerPC/fnegsel.ll @@ -2,7 +2,7 @@ define double @test_FNEG_sel(double %A, double %B, double %C) { %D = sub double -0.000000e+00, %A ; <double> [#uses=1] - %Cond = fcmp ogt double %D, -0.000000e+00 ; <i1> [#uses=1] + %Cond = fcmp ugt double %D, -0.000000e+00 ; <i1> [#uses=1] %E = select i1 %Cond, double %B, double %C ; <double> [#uses=1] ret double %E } |