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-rw-r--r--include/llvm/IR/IntrinsicsMips.td17
-rw-r--r--lib/Target/Mips/MipsMSAInstrInfo.td32
-rw-r--r--test/CodeGen/Mips/msa/elm_insv.ll91
3 files changed, 140 insertions, 0 deletions
diff --git a/include/llvm/IR/IntrinsicsMips.td b/include/llvm/IR/IntrinsicsMips.td
index 9e6d202..eb86388 100644
--- a/include/llvm/IR/IntrinsicsMips.td
+++ b/include/llvm/IR/IntrinsicsMips.td
@@ -1039,6 +1039,23 @@ def int_mips_insert_h : GCCBuiltin<"__builtin_msa_insert_h">,
def int_mips_insert_w : GCCBuiltin<"__builtin_msa_insert_w">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
+def int_mips_insve_b : GCCBuiltin<"__builtin_msa_insve_b">,
+ Intrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+def int_mips_insve_h : GCCBuiltin<"__builtin_msa_insve_h">,
+ Intrinsic<[llvm_v8i16_ty],
+ [llvm_v8i16_ty, llvm_i32_ty, llvm_v8i16_ty],
+ [IntrNoMem]>;
+def int_mips_insve_w : GCCBuiltin<"__builtin_msa_insve_w">,
+ Intrinsic<[llvm_v4i32_ty],
+ [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
+ [IntrNoMem]>;
+def int_mips_insve_d : GCCBuiltin<"__builtin_msa_insve_d">,
+ Intrinsic<[llvm_v2i64_ty],
+ [llvm_v2i64_ty, llvm_i32_ty, llvm_v2i64_ty],
+ [IntrNoMem]>;
+
def int_mips_ldi_b : GCCBuiltin<"__builtin_msa_ldi_b">,
Intrinsic<[llvm_v16i8_ty], [llvm_i32_ty], []>;
def int_mips_ldi_h : GCCBuiltin<"__builtin_msa_ldi_h">,
diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td
index 1657962..5a33d75 100644
--- a/lib/Target/Mips/MipsMSAInstrInfo.td
+++ b/lib/Target/Mips/MipsMSAInstrInfo.td
@@ -403,6 +403,11 @@ class INSERT_B_ENC : MSA_ELM_B_FMT<0b0100, 0b011001>;
class INSERT_H_ENC : MSA_ELM_H_FMT<0b0100, 0b011001>;
class INSERT_W_ENC : MSA_ELM_W_FMT<0b0100, 0b011001>;
+class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
+class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
+class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
+class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
+
class LD_B_ENC : MSA_I5_FMT<0b110, 0b00, 0b000111>;
class LD_H_ENC : MSA_I5_FMT<0b110, 0b01, 0b000111>;
class LD_W_ENC : MSA_I5_FMT<0b110, 0b10, 0b000111>;
@@ -798,6 +803,19 @@ class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
string Constraints = "$wd = $wd_in";
}
+class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
+ InstrItinClass itin, RegisterClass RCD,
+ RegisterClass RCWS> {
+ dag OutOperandList = (outs RCD:$wd);
+ dag InOperandList = (ins RCD:$wd_in, uimm6:$n, RCWS:$ws);
+ string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[0]");
+ list<dag> Pattern = [(set RCD:$wd, (OpNode RCD:$wd_in,
+ immZExt6:$n,
+ RCWS:$ws))];
+ InstrItinClass Itinerary = itin;
+ string Constraints = "$wd = $wd_in";
+}
+
class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
InstrItinClass itin, RegisterClass RCWD,
RegisterClass RCWS, RegisterClass RCWT = RCWS> {
@@ -1490,6 +1508,15 @@ class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", int_mips_insert_h,
class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", int_mips_insert_w,
NoItinerary, MSA128, GPR32>;
+class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", int_mips_insve_b,
+ NoItinerary, MSA128, MSA128>;
+class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", int_mips_insve_h,
+ NoItinerary, MSA128, MSA128>;
+class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", int_mips_insve_w,
+ NoItinerary, MSA128, MSA128>;
+class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d,
+ NoItinerary, MSA128, MSA128>;
+
class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, InstrItinClass itin, RegisterClass RCWD,
Operand MemOpnd = mem, ComplexPattern Addr = addr> {
@@ -2304,6 +2331,11 @@ def INSERT_B : INSERT_B_ENC, INSERT_B_DESC, Requires<[HasMSA]>;
def INSERT_H : INSERT_H_ENC, INSERT_H_DESC, Requires<[HasMSA]>;
def INSERT_W : INSERT_W_ENC, INSERT_W_DESC, Requires<[HasMSA]>;
+def INSVE_B : INSVE_B_ENC, INSVE_B_DESC, Requires<[HasMSA]>;
+def INSVE_H : INSVE_H_ENC, INSVE_H_DESC, Requires<[HasMSA]>;
+def INSVE_W : INSVE_W_ENC, INSVE_W_DESC, Requires<[HasMSA]>;
+def INSVE_D : INSVE_D_ENC, INSVE_D_DESC, Requires<[HasMSA]>;
+
def LD_B: LD_B_ENC, LD_B_DESC, Requires<[HasMSA]>;
def LD_H: LD_H_ENC, LD_H_DESC, Requires<[HasMSA]>;
def LD_W: LD_W_ENC, LD_W_DESC, Requires<[HasMSA]>;
diff --git a/test/CodeGen/Mips/msa/elm_insv.ll b/test/CodeGen/Mips/msa/elm_insv.ll
index c5378eb..be0b5c4 100644
--- a/test/CodeGen/Mips/msa/elm_insv.ll
+++ b/test/CodeGen/Mips/msa/elm_insv.ll
@@ -1,4 +1,7 @@
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
+;
+; Test the MSA element insertion intrinsics that are encoded with the ELM
+; instruction format.
@llvm_mips_insert_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_insert_b_ARG3 = global i32 27, align 16
@@ -66,3 +69,91 @@ declare <4 x i32> @llvm.mips.insert.w(<4 x i32>, i32, i32) nounwind
; CHECK: st.w
; CHECK: .size llvm_mips_insert_w_test
;
+@llvm_mips_insve_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
+@llvm_mips_insve_b_ARG3 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
+@llvm_mips_insve_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
+
+define void @llvm_mips_insve_b_test() nounwind {
+entry:
+ %0 = load <16 x i8>* @llvm_mips_insve_b_ARG1
+ %1 = load <16 x i8>* @llvm_mips_insve_b_ARG3
+ %2 = tail call <16 x i8> @llvm.mips.insve.b(<16 x i8> %0, i32 1, <16 x i8> %1)
+ store <16 x i8> %2, <16 x i8>* @llvm_mips_insve_b_RES
+ ret void
+}
+
+declare <16 x i8> @llvm.mips.insve.b(<16 x i8>, i32, <16 x i8>) nounwind
+
+; CHECK: llvm_mips_insve_b_test:
+; CHECK: ld.b
+; CHECK: ld.b
+; CHECK: insve.b
+; CHECK: st.b
+; CHECK: .size llvm_mips_insve_b_test
+;
+@llvm_mips_insve_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
+@llvm_mips_insve_h_ARG3 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
+@llvm_mips_insve_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
+
+define void @llvm_mips_insve_h_test() nounwind {
+entry:
+ %0 = load <8 x i16>* @llvm_mips_insve_h_ARG1
+ %1 = load <8 x i16>* @llvm_mips_insve_h_ARG3
+ %2 = tail call <8 x i16> @llvm.mips.insve.h(<8 x i16> %0, i32 1, <8 x i16> %1)
+ store <8 x i16> %2, <8 x i16>* @llvm_mips_insve_h_RES
+ ret void
+}
+
+declare <8 x i16> @llvm.mips.insve.h(<8 x i16>, i32, <8 x i16>) nounwind
+
+; CHECK: llvm_mips_insve_h_test:
+; CHECK: ld.h
+; CHECK: ld.h
+; CHECK: insve.h
+; CHECK: st.h
+; CHECK: .size llvm_mips_insve_h_test
+;
+@llvm_mips_insve_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
+@llvm_mips_insve_w_ARG3 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
+@llvm_mips_insve_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_insve_w_test() nounwind {
+entry:
+ %0 = load <4 x i32>* @llvm_mips_insve_w_ARG1
+ %1 = load <4 x i32>* @llvm_mips_insve_w_ARG3
+ %2 = tail call <4 x i32> @llvm.mips.insve.w(<4 x i32> %0, i32 1, <4 x i32> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_insve_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.insve.w(<4 x i32>, i32, <4 x i32>) nounwind
+
+; CHECK: llvm_mips_insve_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: insve.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_insve_w_test
+;
+@llvm_mips_insve_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
+@llvm_mips_insve_d_ARG3 = global <2 x i64> <i64 2, i64 3>, align 16
+@llvm_mips_insve_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_insve_d_test() nounwind {
+entry:
+ %0 = load <2 x i64>* @llvm_mips_insve_d_ARG1
+ %1 = load <2 x i64>* @llvm_mips_insve_d_ARG3
+ %2 = tail call <2 x i64> @llvm.mips.insve.d(<2 x i64> %0, i32 1, <2 x i64> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_insve_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.insve.d(<2 x i64>, i32, <2 x i64>) nounwind
+
+; CHECK: llvm_mips_insve_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: insve.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_insve_d_test
+;
generated by cgit v1.1 at 2024-12-23 13:29:34 +0000