diff options
| -rw-r--r-- | lib/Target/X86/X86InstrAVX512.td | 5 | ||||
| -rw-r--r-- | test/CodeGen/X86/avx512-mov.ll | 16 |
2 files changed, 21 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index c9901bc..e73c73e 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -1467,6 +1467,10 @@ let Predicates = [HasAVX512] in { let AddedComplexity = 20 in { def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))), (VMOVDI2PDIZrm addr:$src)>; + def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))), + (VMOV64toPQIZrr GR64:$src)>; + def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))), + (VMOVDI2PDIZrr GR32:$src)>; def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))), (VMOVDI2PDIZrm addr:$src)>; @@ -1477,6 +1481,7 @@ let Predicates = [HasAVX512] in { def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))), (VMOVZPQILo2PQIZrr VR128X:$src)>; } + // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext. def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))), diff --git a/test/CodeGen/X86/avx512-mov.ll b/test/CodeGen/X86/avx512-mov.ll index 6ac4872..c44107b 100644 --- a/test/CodeGen/X86/avx512-mov.ll +++ b/test/CodeGen/X86/avx512-mov.ll @@ -100,3 +100,19 @@ define <2 x double> @test12(double* %x) { %res = insertelement <2 x double>zeroinitializer, double %y, i32 0 ret <2 x double>%res } + +; CHECK-LABEL: @test13 +; CHECK: vmovqz %rdi +; CHECK: ret +define <2 x i64> @test13(i64 %x) { + %res = insertelement <2 x i64>zeroinitializer, i64 %x, i32 0 + ret <2 x i64>%res +} + +; CHECK-LABEL: @test14 +; CHECK: vmovdz %edi +; CHECK: ret +define <4 x i32> @test14(i32 %x) { + %res = insertelement <4 x i32>zeroinitializer, i32 %x, i32 0 + ret <4 x i32>%res +} |