diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 14 |
2 files changed, 15 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index ca5f176..d7e92db 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -14,6 +14,7 @@ // IT block predicate field def it_pred : Operand<i32> { let PrintMethod = "printMandatoryPredicateOperand"; + let DecoderMethod = "DecodeITCond"; } // IT block condition mask diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index c4b2f61..346bd2b 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -228,6 +228,8 @@ static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); #include "ARMGenDisassemblerTables.inc" #include "ARMGenInstrInfo.inc" @@ -3289,3 +3291,15 @@ static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, return S; } +static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Cond, + uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + if (Cond == 0xF) { + Cond = 0xE; + CHECK(S, Unpredictable); + } + + Inst.addOperand(MCOperand::CreateImm(Cond)); + return S; +} + |