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1 files changed, 23 insertions, 1 deletions
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@@ -50,9 +50,15 @@ N: Cameron Buschardt
E: buschard@uiuc.edu
D: The `mem2reg' pass - promotes values stored in memory to registers
+N: Brendon Cahoon
+E: bcahoon@codeaurora.org
+D: Loop unrolling with run-time trip counts.
+
N: Chandler Carruth
E: chandlerc@gmail.com
-D: LinkTimeOptimizer for Linux, via binutils integration, and C API
+D: Hashing algorithms and interfaces
+D: Inline cost analysis
+D: Machine block placement pass
N: Casey Carter
E: ccarter@uiuc.edu
@@ -83,6 +89,10 @@ N: John T. Criswell
E: criswell@uiuc.edu
D: Original Autoconf support, documentation improvements, bug fixes
+N: Anshuman Dasgupta
+E: adasgupt@codeaurora.org
+D: Deterministic finite automaton based infrastructure for VLIW packetization
+
N: Stefanus Du Toit
E: stefanus.dutoit@rapidmind.com
D: Bug fixes and minor improvements
@@ -206,6 +216,10 @@ N: Benjamin Kramer
E: benny.kra@gmail.com
D: Miscellaneous bug fixes
+N: Sundeep Kushwaha
+E: sundeepk@codeaurora.org
+D: Implemented DFA-based target independent VLIW packetizer
+
N: Christopher Lamb
E: christopher.lamb@gmail.com
D: aligned load/store support, parts of noalias and restrict support
@@ -241,6 +255,10 @@ N: Nick Lewycky
E: nicholas@mxc.ca
D: PredicateSimplifier pass
+N: Tony Linthicum, et. al.
+E: tlinth@codeaurora.org
+D: Backend for Qualcomm's Hexagon VLIW processor.
+
N: Bruno Cardoso Lopes
E: bruno.cardoso@gmail.com
W: http://www.brunocardoso.org
@@ -267,6 +285,10 @@ N: Scott Michel
E: scottm@aero.org
D: Added STI Cell SPU backend.
+N: Kai Nacke
+E: kai@redstar.de
+D: Support for implicit TLS model used with MS VC runtime
+
N: Takumi Nakamura
E: geek4civic@gmail.com
E: chapuni@hf.rim.or.jp