diff options
Diffstat (limited to 'include/llvm/CodeGen')
| -rw-r--r-- | include/llvm/CodeGen/ScheduleDAG.h | 4 | ||||
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAGISel.h | 5 |
2 files changed, 5 insertions, 4 deletions
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index ed7801f..0225b12 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -265,7 +265,7 @@ namespace llvm { /// Run - perform scheduling. /// - MachineBasicBlock *Run(); + void Run(); /// isPassiveNode - Return true if the node is a non-scheduled leaf. /// @@ -336,7 +336,7 @@ namespace llvm { /// void EmitNoop(); - void EmitSchedule(); + MachineBasicBlock *EmitSchedule(); void dumpSchedule() const; diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index e0b26b9..72a836f 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -30,6 +30,7 @@ namespace llvm { class FunctionLoweringInfo; class HazardRecognizer; class CollectorMetadata; + class ScheduleDAG; /// SelectionDAGISel - This is the common base class used for SelectionDAG-based /// pattern-matching instruction selectors. @@ -191,9 +192,9 @@ private: void ComputeLiveOutVRegInfo(SelectionDAG &DAG); - /// Pick a safe ordering and emit instructions for each target node in the + /// Pick a safe ordering for instructions for each target node in the /// graph. - void ScheduleAndEmitDAG(SelectionDAG &DAG); + ScheduleDAG *Schedule(SelectionDAG &DAG); /// SwitchCases - Vector of CaseBlock structures used to communicate /// SwitchInst code generation information. |