diff options
Diffstat (limited to 'include/llvm/Target')
| -rw-r--r-- | include/llvm/Target/Target.td | 57 | ||||
| -rw-r--r-- | include/llvm/Target/TargetAsmInfo.h | 8 | ||||
| -rw-r--r-- | include/llvm/Target/TargetLowering.h | 3 | ||||
| -rw-r--r-- | include/llvm/Target/TargetLoweringObjectFile.h | 16 | ||||
| -rw-r--r-- | include/llvm/Target/TargetRegisterInfo.h | 27 |
5 files changed, 76 insertions, 35 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index 616087c..bc8be89 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -133,11 +133,21 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, // model instruction operand constraints, and should have isAllocatable = 0. bit isAllocatable = 1; - // MethodProtos/MethodBodies - These members can be used to insert arbitrary - // code into a generated register class. The normal usage of this is to - // overload virtual methods. - code MethodProtos = [{}]; - code MethodBodies = [{}]; + // AltOrders - List of alternative allocation orders. The default order is + // MemberList itself, and that is good enough for most targets since the + // register allocators automatically remove reserved registers and move + // callee-saved registers to the end. + list<dag> AltOrders = []; + + // AltOrderSelect - The body of a function that selects the allocation order + // to use in a given machine function. The code will be inserted in a + // function like this: + // + // static inline unsigned f(const MachineFunction &MF) { ... } + // + // The function should return 0 to select the default order defined by + // MemberList, 1 to select the first AltOrders entry and so on. + code AltOrderSelect = [{}]; } // The memberList in a RegisterClass is a dag of set operations. TableGen @@ -174,6 +184,43 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, def sequence; def decimate; +// RegisterTuples - Automatically generate super-registers by forming tuples of +// sub-registers. This is useful for modeling register sequence constraints +// with pseudo-registers that are larger than the architectural registers. +// +// The sub-register lists are zipped together: +// +// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; +// +// Generates the same registers as: +// +// let SubRegIndices = [sube, subo] in { +// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; +// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; +// } +// +// The generated pseudo-registers inherit super-classes and fields from their +// first sub-register. Most fields from the Register class are inferred, and +// the AsmName and Dwarf numbers are cleared. +// +// RegisterTuples instances can be used in other set operations to form +// register classes and so on. This is the only way of using the generated +// registers. +class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> { + // SubRegs - N lists of registers to be zipped up. Super-registers are + // synthesized from the first element of each SubRegs list, the second + // element and so on. + list<dag> SubRegs = Regs; + + // SubRegIndices - N SubRegIndex instances. This provides the names of the + // sub-registers in the synthesized super-registers. + list<SubRegIndex> SubRegIndices = Indices; + + // Compose sub-register indices like in a normal Register. + list<dag> CompositeIndices = []; +} + + //===----------------------------------------------------------------------===// // DwarfRegNum - This class provides a mapping of the llvm register enumeration // to the register numbering used by gcc and gdb. These values are used by a diff --git a/include/llvm/Target/TargetAsmInfo.h b/include/llvm/Target/TargetAsmInfo.h index 743a2d4..1dc725a 100644 --- a/include/llvm/Target/TargetAsmInfo.h +++ b/include/llvm/Target/TargetAsmInfo.h @@ -59,6 +59,10 @@ public: return TLOF->getEHFrameSection(); } + const MCSection *getCompactUnwindSection() const { + return TLOF->getCompactUnwindSection(); + } + const MCSection *getDwarfFrameSection() const { return TLOF->getDwarfFrameSection(); } @@ -79,6 +83,10 @@ public: return TLOF->isFunctionEHFrameSymbolPrivate(); } + bool getSupportsCompactUnwindInfo() const { + return TLOF->getSupportsCompactUnwindInfo(); + } + const unsigned *getCalleeSavedRegs(MachineFunction *MF = 0) const { return TRI->getCalleeSavedRegs(MF); } diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 093e79b..c3f5f2b 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -1836,9 +1836,8 @@ private: // Build a new vector type and check if it is legal. MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); - // Found a legal promoted vector type. - if (ValueTypeActions.getTypeAction(NVT) == TypeLegal) + if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) return LegalizeKind(TypePromoteInteger, EVT::getVectorVT(Context, EltVT, NumElts)); } diff --git a/include/llvm/Target/TargetLoweringObjectFile.h b/include/llvm/Target/TargetLoweringObjectFile.h index 3991035..a3d1f37 100644 --- a/include/llvm/Target/TargetLoweringObjectFile.h +++ b/include/llvm/Target/TargetLoweringObjectFile.h @@ -68,6 +68,11 @@ protected: /// LSDASection - If exception handling is supported by the target, this is /// the section the Language Specific Data Area information is emitted to. const MCSection *LSDASection; + + /// CompactUnwindSection - If exception handling is supported by the target + /// and the target can support a compact representation of the CIE and FDE, + /// this is the section to emit them into. + const MCSection *CompactUnwindSection; // Dwarf sections for debug info. If a target supports debug info, these must // be set. @@ -102,8 +107,12 @@ protected: /// private linkage, aka an L or .L label) or false if it should be a normal /// non-.globl label. This defaults to true. bool IsFunctionEHFrameSymbolPrivate; + + /// SupportsCompactUnwindInfo - This flag is set to true if the CIE and FDE + /// information should be emitted in a compact form. + bool SupportsCompactUnwindInfo; + public: - MCContext &getContext() const { return *Ctx; } virtual ~TargetLoweringObjectFile(); @@ -121,10 +130,12 @@ public: bool getSupportsWeakOmittedEHFrame() const { return SupportsWeakOmittedEHFrame; } - bool getCommDirectiveSupportsAlignment() const { return CommDirectiveSupportsAlignment; } + bool getSupportsCompactUnwindInfo() const { + return SupportsCompactUnwindInfo; + } const MCSection *getTextSection() const { return TextSection; } const MCSection *getDataSection() const { return DataSection; } @@ -132,6 +143,7 @@ public: const MCSection *getStaticCtorSection() const { return StaticCtorSection; } const MCSection *getStaticDtorSection() const { return StaticDtorSection; } const MCSection *getLSDASection() const { return LSDASection; } + const MCSection *getCompactUnwindSection() const{return CompactUnwindSection;} virtual const MCSection *getEHFrameSection() const = 0; virtual void emitPersonalityValue(MCStreamer &Streamer, const TargetMachine &TM, diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h index feb0929..840b048 100644 --- a/include/llvm/Target/TargetRegisterInfo.h +++ b/include/llvm/Target/TargetRegisterInfo.h @@ -237,29 +237,6 @@ public: return SuperClasses[0] != 0; } - /// allocation_order_begin/end - These methods define a range of registers - /// which specify the registers in this class that are valid to register - /// allocate, and the preferred order to allocate them in. For example, - /// callee saved registers should be at the end of the list, because it is - /// cheaper to allocate caller saved registers. - /// - /// These methods take a MachineFunction argument, which can be used to tune - /// the allocatable registers based on the characteristics of the function, - /// subtarget, or other criteria. - /// - /// Register allocators should account for the fact that an allocation - /// order iterator may return a reserved register and always check - /// if the register is allocatable (getAllocatableSet()) before using it. - /// - /// By default, these methods return all registers in the class. - /// - virtual iterator allocation_order_begin(const MachineFunction &MF) const { - return begin(); - } - virtual iterator allocation_order_end(const MachineFunction &MF) const { - return end(); - } - /// getRawAllocationOrder - Returns the preferred order for allocating /// registers from this register class in MF. The raw order comes directly /// from the .td file and may include reserved registers that are not @@ -276,9 +253,7 @@ public: /// virtual ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const { - iterator B = allocation_order_begin(MF); - iterator E = allocation_order_end(MF); - return ArrayRef<unsigned>(B, E - B); + return ArrayRef<unsigned>(begin(), getNumRegs()); } /// getSize - Return the size of the register in bytes, which is also the size |