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-rw-r--r--include/llvm/CodeGen/LiveInterval.h18
-rw-r--r--include/llvm/CodeGen/LiveIntervalAnalysis.h9
-rw-r--r--include/llvm/CodeGen/MachineInstr.h4
-rw-r--r--include/llvm/CodeGen/SSARegMap.h19
-rw-r--r--include/llvm/CodeGen/SimpleRegisterCoalescing.h4
5 files changed, 44 insertions, 10 deletions
diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h
index 50ac158..34e53a9 100644
--- a/include/llvm/CodeGen/LiveInterval.h
+++ b/include/llvm/CodeGen/LiveInterval.h
@@ -155,7 +155,7 @@ namespace llvm {
/// copyValNumInfo - Copy the value number info for one value number to
/// another.
- void copyValNumInfo(VNInfo *DstValNo, VNInfo *SrcValNo) {
+ void copyValNumInfo(VNInfo *DstValNo, const VNInfo *SrcValNo) {
DstValNo->def = SrcValNo->def;
DstValNo->reg = SrcValNo->reg;
DstValNo->kills = SrcValNo->kills;
@@ -241,11 +241,23 @@ namespace llvm {
void MergeInClobberRanges(const LiveInterval &Clobbers,
BumpPtrAllocator &VNInfoAllocator);
- /// MergeRangesInAsValue - Merge all of the intervals in RHS into this live
- /// interval as the specified value number. The LiveRanges in RHS are
+ /// MergeRangesInAsValue - Merge all of the live ranges in RHS into this
+ /// live interval as the specified value number. The LiveRanges in RHS are
/// allowed to overlap with LiveRanges in the current interval, but only if
/// the overlapping LiveRanges have the specified value number.
void MergeRangesInAsValue(const LiveInterval &RHS, VNInfo *LHSValNo);
+
+ /// MergeValueInAsValue - Merge all of the live ranges of a specific val#
+ /// in RHS into this live interval as the specified value number.
+ /// The LiveRanges in RHS are allowed to overlap with LiveRanges in the
+ /// current interval, but only if the overlapping LiveRanges have the
+ /// specified value number.
+ void MergeValueInAsValue(const LiveInterval &RHS,
+ VNInfo *RHSValNo, VNInfo *LHSValNo);
+
+ /// Copy - Copy the specified live interval. This copies all the fields
+ /// except for the register of the interval.
+ void Copy(const LiveInterval &RHS, BumpPtrAllocator &VNInfoAllocator);
bool empty() const { return ranges.empty(); }
diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h
index 671de02..bf0a829 100644
--- a/include/llvm/CodeGen/LiveIntervalAnalysis.h
+++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h
@@ -167,11 +167,6 @@ namespace llvm {
return I->second;
}
- /// CreateNewLiveInterval - Create a new live interval with the given live
- /// ranges. The new live interval will have an infinite spill weight.
- LiveInterval &CreateNewLiveInterval(const LiveInterval *LI,
- const std::vector<LiveRange> &LRs);
-
std::vector<LiveInterval*> addIntervalsForSpills(const LiveInterval& i,
VirtRegMap& vrm, unsigned reg);
@@ -254,8 +249,8 @@ namespace llvm {
/// MI. If it is successul, MI is updated with the newly created MI and
/// returns true.
bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
- unsigned index, unsigned i, bool isSS,
- MachineInstr *DefMI, int slot, unsigned reg);
+ MachineInstr *DefMI, unsigned index, unsigned i,
+ bool isSS, int slot, unsigned reg);
static LiveInterval createInterval(unsigned Reg);
diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 3dbda8d..beba692 100644
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -418,6 +418,10 @@ public:
/// none is found.
int findFirstPredOperandIdx() const;
+ /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
+ /// to two addr elimination.
+ bool isRegReDefinedByTwoAddr(unsigned Reg) const;
+
/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
///
void copyKillDeadInfo(const MachineInstr *MI);
diff --git a/include/llvm/CodeGen/SSARegMap.h b/include/llvm/CodeGen/SSARegMap.h
index 97d8d69..a92222a 100644
--- a/include/llvm/CodeGen/SSARegMap.h
+++ b/include/llvm/CodeGen/SSARegMap.h
@@ -26,6 +26,7 @@ class TargetRegisterClass;
class SSARegMap {
IndexedMap<const TargetRegisterClass*, VirtReg2IndexFunctor> RegClassMap;
+ IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegSubIdxMap;
unsigned NextRegNum;
public:
@@ -42,12 +43,30 @@ class SSARegMap {
assert(RegClass && "Cannot create register without RegClass!");
RegClassMap.grow(NextRegNum);
RegClassMap[NextRegNum] = RegClass;
+ RegSubIdxMap.grow(NextRegNum);
+ RegSubIdxMap[NextRegNum] = std::make_pair(0,0);
return NextRegNum++;
}
unsigned getLastVirtReg() const {
return NextRegNum - 1;
}
+
+ void setIsSubRegister(unsigned Reg, unsigned SuperReg, unsigned SubIdx) {
+ RegSubIdxMap[Reg] = std::make_pair(SuperReg, SubIdx);
+ }
+
+ bool isSubRegister(unsigned Reg) const {
+ return RegSubIdxMap[Reg].first != 0;
+ }
+
+ unsigned getSuperRegister(unsigned Reg) const {
+ return RegSubIdxMap[Reg].first;
+ }
+
+ unsigned getSubRegisterIndex(unsigned Reg) const {
+ return RegSubIdxMap[Reg].second;
+ }
};
} // End llvm namespace
diff --git a/include/llvm/CodeGen/SimpleRegisterCoalescing.h b/include/llvm/CodeGen/SimpleRegisterCoalescing.h
index 4e76081..00095dd 100644
--- a/include/llvm/CodeGen/SimpleRegisterCoalescing.h
+++ b/include/llvm/CodeGen/SimpleRegisterCoalescing.h
@@ -47,6 +47,10 @@ namespace llvm {
/// with other intervals.
BitVector JoinedLIs;
+ /// SubRegIdxes - Keep track of sub-register and sub-indexes.
+ ///
+ std::vector<std::pair<unsigned, unsigned> > SubRegIdxes;
+
public:
static char ID; // Pass identifcation, replacement for typeid
SimpleRegisterCoalescing() : MachineFunctionPass((intptr_t)&ID) {}