diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/MC/MCSchedule.h | 16 | ||||
-rw-r--r-- | include/llvm/MC/MCSubtargetInfo.h | 8 | ||||
-rw-r--r-- | include/llvm/Target/TargetSubtargetInfo.h | 10 |
3 files changed, 29 insertions, 5 deletions
diff --git a/include/llvm/MC/MCSchedule.h b/include/llvm/MC/MCSchedule.h index af68a29..cff175b 100644 --- a/include/llvm/MC/MCSchedule.h +++ b/include/llvm/MC/MCSchedule.h @@ -172,10 +172,8 @@ private: unsigned ProcID; const MCProcResourceDesc *ProcResourceTable; const MCSchedClassDesc *SchedClassTable; -#ifndef NDEBUG unsigned NumProcResourceKinds; unsigned NumSchedClasses; -#endif // Instruction itinerary tables used by InstrItineraryData. friend class InstrItineraryData; const InstrItinerary *InstrItineraries; @@ -190,14 +188,22 @@ public: LoadLatency(DefaultLoadLatency), HighLatency(DefaultHighLatency), MispredictPenalty(DefaultMispredictPenalty), - ProcID(0), InstrItineraries(0) {} + ProcID(0), ProcResourceTable(0), SchedClassTable(0), + NumProcResourceKinds(0), NumSchedClasses(0), + InstrItineraries(0) { + (void)NumProcResourceKinds; + (void)NumSchedClasses; + } // Table-gen driven ctor. MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl, unsigned mp, + unsigned pi, const MCProcResourceDesc *pr, + const MCSchedClassDesc *sc, unsigned npr, unsigned nsc, const InstrItinerary *ii): IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl), - MispredictPenalty(mp), ProcID(0), ProcResourceTable(0), - SchedClassTable(0), InstrItineraries(ii) {} + MispredictPenalty(mp), ProcID(pi), ProcResourceTable(pr), + SchedClassTable(sc), NumProcResourceKinds(npr), NumSchedClasses(nsc), + InstrItineraries(ii) {} unsigned getProcessorID() const { return ProcID; } diff --git a/include/llvm/MC/MCSubtargetInfo.h b/include/llvm/MC/MCSubtargetInfo.h index d1d4047..d5e15d4 100644 --- a/include/llvm/MC/MCSubtargetInfo.h +++ b/include/llvm/MC/MCSubtargetInfo.h @@ -36,6 +36,7 @@ class MCSubtargetInfo { const MCWriteProcResEntry *WriteProcResTable; const MCWriteLatencyEntry *WriteLatencyTable; const MCReadAdvanceEntry *ReadAdvanceTable; + const MCSchedModel *CPUSchedModel; const InstrStage *Stages; // Instruction itinerary stages const unsigned *OperandCycles; // Itinerary operand cycles @@ -49,6 +50,9 @@ public: const SubtargetFeatureKV *PF, const SubtargetFeatureKV *PD, const SubtargetInfoKV *ProcSched, + const MCWriteProcResEntry *WPR, + const MCWriteLatencyEntry *WL, + const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP, unsigned NF, unsigned NP); @@ -80,6 +84,10 @@ public: /// const MCSchedModel *getSchedModelForCPU(StringRef CPU) const; + /// getSchedModel - Get the machine model for this subtarget's CPU. + /// + const MCSchedModel *getSchedModel() const { return CPUSchedModel; } + /// Return an iterator at the first process resource consumed by the given /// scheduling class. const MCWriteProcResEntry *getWriteProcResBegin( diff --git a/include/llvm/Target/TargetSubtargetInfo.h b/include/llvm/Target/TargetSubtargetInfo.h index 8c6c695..bc357ac 100644 --- a/include/llvm/Target/TargetSubtargetInfo.h +++ b/include/llvm/Target/TargetSubtargetInfo.h @@ -14,6 +14,7 @@ #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H #define LLVM_TARGET_TARGETSUBTARGETINFO_H +#include "llvm/Codegen/TargetSchedule.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/CodeGen.h" @@ -43,6 +44,15 @@ public: virtual ~TargetSubtargetInfo(); + /// Initialize a copy of the scheduling model for this subtarget. + /// TargetSchedModel provides the interface for the subtarget's + /// instruction scheduling information. + void initSchedModel(TargetSchedModel &SchedModel, + const TargetInstrInfo *TII) const { + // CPUSchedModel is initialized to a static instance by InitMCSubtargetInfo. + SchedModel.init(*getSchedModel(), this, TII); + } + /// getSpecialAddressLatency - For targets where it is beneficial to /// backschedule instructions that compute addresses, return a value /// indicating the number of scheduling cycles of backscheduling that |