diff options
Diffstat (limited to 'lib/CodeGen/LowerSubregs.cpp')
| -rw-r--r-- | lib/CodeGen/LowerSubregs.cpp | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp index 668a9e5..4172b12 100644 --- a/lib/CodeGen/LowerSubregs.cpp +++ b/lib/CodeGen/LowerSubregs.cpp @@ -63,6 +63,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { MachineBasicBlock *MBB = MI->getParent(); MachineFunction &MF = *MBB->getParent(); const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); + const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() && MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() && @@ -88,7 +89,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) && "Extract subreg and Dst must be of same register class"); - MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC); + TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC); MachineBasicBlock::iterator dMI = MI; DOUT << "subreg: " << *(--dMI); } @@ -103,6 +104,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { MachineBasicBlock *MBB = MI->getParent(); MachineFunction &MF = *MBB->getParent(); const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); + const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); unsigned DstReg = 0; unsigned SrcReg = 0; unsigned InsReg = 0; @@ -157,7 +159,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { } else { TRC1 = MF.getRegInfo().getRegClass(InsReg); } - MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); + TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); #ifndef NDEBUG MachineBasicBlock::iterator dMI = MI; @@ -184,7 +186,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) && "Insert superreg and Dst must be of same register class"); - MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0); + TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0); #ifndef NDEBUG MachineBasicBlock::iterator dMI = MI; @@ -206,7 +208,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { } else { TRC1 = MF.getRegInfo().getRegClass(InsReg); } - MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); + TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); #ifndef NDEBUG MachineBasicBlock::iterator dMI = MI; |