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-rw-r--r--lib/CodeGen/SelectionDAG/InstrEmitter.cpp4
-rw-r--r--lib/CodeGen/SelectionDAG/InstrEmitter.h1
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp29
3 files changed, 18 insertions, 16 deletions
diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index ff77d82..1afca3d 100644
--- a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -507,7 +507,6 @@ InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
/// EmitDbgValue - Generate machine instruction for a dbg_value node.
///
MachineInstr *InstrEmitter::EmitDbgValue(SDDbgValue *SD,
- MachineBasicBlock *InsertBB,
DenseMap<SDValue, unsigned> &VRBaseMap,
DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
uint64_t Offset = SD->getOffset();
@@ -518,8 +517,7 @@ MachineInstr *InstrEmitter::EmitDbgValue(SDDbgValue *SD,
// Stack address; this needs to be lowered in target-dependent fashion.
// EmitTargetCodeForFrameDebugValue is responsible for allocation.
unsigned FrameIx = SD->getFrameIx();
- TLI->EmitTargetCodeForFrameDebugValue(InsertBB, FrameIx, Offset, MDPtr, DL);
- return 0;
+ return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL);
}
// Otherwise, we're going to create an instruction here.
const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.h b/lib/CodeGen/SelectionDAG/InstrEmitter.h
index baabb75..f8fd6ef 100644
--- a/lib/CodeGen/SelectionDAG/InstrEmitter.h
+++ b/lib/CodeGen/SelectionDAG/InstrEmitter.h
@@ -103,7 +103,6 @@ public:
/// EmitDbgValue - Generate machine instruction for a dbg_value node.
///
MachineInstr *EmitDbgValue(SDDbgValue *SD,
- MachineBasicBlock *InsertBB,
DenseMap<SDValue, unsigned> &VRBaseMap,
DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 50defc8..a4cadc3 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -449,9 +449,11 @@ static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,
continue;
unsigned DVOrder = DVs[i]->getOrder();
if (DVOrder == ++Order) {
- MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], BB, VRBaseMap, EM);
- Orders.push_back(std::make_pair(DVOrder, DbgMI));
- BB->insert(InsertPos, DbgMI);
+ MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap, EM);
+ if (DbgMI) {
+ Orders.push_back(std::make_pair(DVOrder, DbgMI));
+ BB->insert(InsertPos, DbgMI);
+ }
DVs[i]->setIsInvalidated();
}
}
@@ -540,13 +542,15 @@ EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
#endif
if ((*DI)->isInvalidated())
continue;
- MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, MIBB, VRBaseMap, EM);
- if (!LastOrder)
- // Insert to start of the BB (after PHIs).
- BB->insert(BBBegin, DbgMI);
- else {
- MachineBasicBlock::iterator Pos = MI;
- MIBB->insert(llvm::next(Pos), DbgMI);
+ MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap, EM);
+ if (DbgMI) {
+ if (!LastOrder)
+ // Insert to start of the BB (after PHIs).
+ BB->insert(BBBegin, DbgMI);
+ else {
+ MachineBasicBlock::iterator Pos = MI;
+ MIBB->insert(llvm::next(Pos), DbgMI);
+ }
}
}
LastOrder = Order;
@@ -558,8 +562,9 @@ EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
MachineBasicBlock *InsertBB = Emitter.getBlock();
MachineBasicBlock::iterator Pos= Emitter.getBlock()->getFirstTerminator();
if (!(*DI)->isInvalidated()) {
- MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, InsertBB, VRBaseMap, EM);
- InsertBB->insert(Pos, DbgMI);
+ MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, VRBaseMap, EM);
+ if (DbgMI)
+ InsertBB->insert(Pos, DbgMI);
}
++DI;
}