diff options
Diffstat (limited to 'lib/Target/ARM/ARMCallingConv.h')
| -rw-r--r-- | lib/Target/ARM/ARMCallingConv.h | 21 |
1 files changed, 6 insertions, 15 deletions
diff --git a/lib/Target/ARM/ARMCallingConv.h b/lib/Target/ARM/ARMCallingConv.h index dc41c1c..bd07236 100644 --- a/lib/Target/ARM/ARMCallingConv.h +++ b/lib/Target/ARM/ARMCallingConv.h @@ -12,8 +12,8 @@ // //===----------------------------------------------------------------------===// -#ifndef ARMCALLINGCONV_H -#define ARMCALLINGCONV_H +#ifndef LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H +#define LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H #include "ARM.h" #include "ARMBaseInstrInfo.h" @@ -177,8 +177,9 @@ static bool CC_ARM_AAPCS_Custom_HA(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { SmallVectorImpl<CCValAssign> &PendingHAMembers = State.getPendingLocs(); + // AAPCS HFAs must have 1-4 elements, all of the same type - assert(PendingHAMembers.size() < 8); + assert(PendingHAMembers.size() < 4); if (PendingHAMembers.size() > 0) assert(PendingHAMembers[0].getLocVT() == LocVT); @@ -188,7 +189,7 @@ static bool CC_ARM_AAPCS_Custom_HA(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo)); if (ArgFlags.isInConsecutiveRegsLast()) { - assert(PendingHAMembers.size() > 0 && PendingHAMembers.size() <= 8 && + assert(PendingHAMembers.size() > 0 && PendingHAMembers.size() <= 4 && "Homogeneous aggregates must have between 1 and 4 members"); // Try to allocate a contiguous block of registers, each of the correct @@ -196,7 +197,6 @@ static bool CC_ARM_AAPCS_Custom_HA(unsigned &ValNo, MVT &ValVT, MVT &LocVT, const uint16_t *RegList; unsigned NumRegs; switch (LocVT.SimpleTy) { - case MVT::i32: case MVT::f32: RegList = SRegList; NumRegs = 16; @@ -235,20 +235,11 @@ static bool CC_ARM_AAPCS_Custom_HA(unsigned &ValNo, MVT &ValVT, MVT &LocVT, State.AllocateReg(SRegList[regNo]); unsigned Size = LocVT.getSizeInBits() / 8; - unsigned Align = Size; - - if (LocVT.SimpleTy == MVT::v2f64 || LocVT.SimpleTy == MVT::i32) { - // Vectors are always aligned to 8 bytes. If we've seen an i32 here - // it's because it's been split from a larger type, also with align 8. - Align = 8; - } + unsigned Align = std::min(Size, 8U); for (auto It : PendingHAMembers) { It.convertToMem(State.AllocateStack(Size, Align)); State.addLoc(It); - - // Only the first member needs to be aligned. - Align = 1; } // All pending members have now been allocated |