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-rw-r--r--lib/Target/ARM/ARMCodeEmitter.cpp242
-rw-r--r--lib/Target/ARM/ARMRelocations.h4
-rw-r--r--lib/Target/ARM/ARMSubtarget.cpp2
-rw-r--r--lib/Target/ARM/Android.mk84
-rw-r--r--lib/Target/ARM/AsmParser/Android.mk61
-rw-r--r--lib/Target/ARM/Disassembler/Android.mk55
-rw-r--r--lib/Target/ARM/InstPrinter/Android.mk55
-rw-r--r--lib/Target/ARM/MCTargetDesc/Android.mk58
-rw-r--r--lib/Target/ARM/TargetInfo/Android.mk55
9 files changed, 561 insertions, 55 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 5e8e173..95decfe 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -88,9 +88,11 @@ namespace {
void emitWordLE(unsigned Binary);
void emitDWordLE(uint64_t Binary);
+ void emitConstantToMemory(unsigned CPI, const Constant *CV);
void emitConstPoolInstruction(const MachineInstr &MI);
void emitMOVi32immInstruction(const MachineInstr &MI);
void emitMOVi2piecesInstruction(const MachineInstr &MI);
+ void emitLEApcrelInstruction(const MachineInstr &MI);
void emitLEApcrelJTInstruction(const MachineInstr &MI);
void emitPseudoMoveInstruction(const MachineInstr &MI);
void addPCLabel(unsigned LabelID);
@@ -139,6 +141,8 @@ namespace {
void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
+ void emitMiscInstruction(const MachineInstr &MI);
+
void emitNEONLaneInstruction(const MachineInstr &MI);
void emitNEONDupInstruction(const MachineInstr &MI);
void emitNEON1RegModImmInstruction(const MachineInstr &MI);
@@ -168,7 +172,13 @@ namespace {
unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
const { return 0; }
unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val)
- const { return 0; }
+ const {
+ if (IsThumb) {
+ Val &= 0x0FFFFFFF;
+ Val |= 0xE0000000;
+ }
+ return Val;
+ }
unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
@@ -264,8 +274,20 @@ namespace {
return Binary;
}
- unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const {
- return 0;
+ unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op)
+ const {
+ const MCInstrDesc &MCID = MI.getDesc();
+ const MachineOperand &MO = MI.getOperand(Op);
+
+ unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ?
+ ARM::reloc_arm_movw : ARM::reloc_arm_movt);
+
+ if (!MO.isImm()) {
+ emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
+ return 0;
+ }
+ unsigned Imm16 = static_cast<unsigned>(MO.getImm());
+ return Imm16;
}
uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
@@ -287,9 +309,10 @@ namespace {
uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
- // {17-13} = reg
- // {12} = (U)nsigned (add == '1', sub == '0')
- // {11-0} = imm12
+ // {12-9} = reg
+ // {8} = (U)nsigned (add == '1', sub == '0')
+ // {7-0} = imm8
+ uint32_t Binary = 0;
const MachineOperand &MO = MI.getOperand(Op);
const MachineOperand &MO1 = MI.getOperand(Op + 1);
if (!MO.isReg()) {
@@ -311,10 +334,8 @@ namespace {
isAdd = false;
}
- uint32_t Binary = Imm12 & 0xfff;
- if (isAdd)
- Binary |= (1 << 12);
- Binary |= (Reg << 13);
+ // If immediate offset is omitted, default to +0.
+ Binary |= 1 << 8;
return Binary;
}
unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
@@ -453,6 +474,9 @@ unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
return II->getRegisterInfo().getEncodingValue(MO.getReg());
else if (MO.isImm())
return static_cast<unsigned>(MO.getImm());
+ else if (MO.isFPImm())
+ return static_cast<unsigned>(MO.getFPImm()->getValueAPF()
+ .bitcastToAPInt().getHiBits(32).getLimitedValue());
else if (MO.isGlobal())
emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
else if (MO.isSymbol())
@@ -605,7 +629,9 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
case ARMII::VFPLdStMulFrm:
emitVFPLoadStoreMultipleInstruction(MI);
break;
-
+ case ARMII::VFPMiscFrm:
+ emitMiscInstruction(MI);
+ break;
// NEON instructions.
case ARMII::NGetLnFrm:
case ARMII::NSetLnFrm:
@@ -627,6 +653,56 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
MCE.processDebugLoc(MI.getDebugLoc(), false);
}
+void ARMCodeEmitter::emitConstantToMemory(unsigned CPI, const Constant *C) {
+ DEBUG({
+ errs() << " ** Constant pool #" << CPI << " @ "
+ << (void*)MCE.getCurrentPCValue() << " ";
+ if (const Function *F = dyn_cast<Function>(C))
+ errs() << F->getName();
+ else
+ errs() << *C;
+ errs() << '\n';
+ });
+
+ switch (C->getValueID()) {
+ default: {
+ llvm_unreachable("Unable to handle this constantpool entry!");
+ break;
+ }
+ case Value::GlobalVariableVal: {
+ emitGlobalAddress(static_cast<const GlobalValue*>(C),
+ ARM::reloc_arm_absolute, isa<Function>(C), false);
+ emitWordLE(0);
+ break;
+ }
+ case Value::ConstantIntVal: {
+ const ConstantInt *CI = static_cast<const ConstantInt*>(C);
+ uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
+ emitWordLE(Val);
+ break;
+ }
+ case Value::ConstantFPVal: {
+ const ConstantFP *CFP = static_cast<const ConstantFP*>(C);
+ if (CFP->getType()->isFloatTy())
+ emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
+ else if (CFP->getType()->isDoubleTy())
+ emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
+ else {
+ llvm_unreachable("Unable to handle this constantpool entry!");
+ }
+ break;
+ }
+ case Value::ConstantArrayVal: {
+ const ConstantArray *CA = static_cast<const ConstantArray*>(C);
+ for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i)
+ emitConstantToMemory(CPI, CA->getOperand(i));
+ break;
+ }
+ }
+
+ return;
+}
+
void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
@@ -658,35 +734,7 @@ void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
}
emitWordLE(0);
} else {
- const Constant *CV = MCPE.Val.ConstVal;
-
- DEBUG({
- errs() << " ** Constant pool #" << CPI << " @ "
- << (void*)MCE.getCurrentPCValue() << " ";
- if (const Function *F = dyn_cast<Function>(CV))
- errs() << F->getName();
- else
- errs() << *CV;
- errs() << '\n';
- });
-
- if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
- emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
- emitWordLE(0);
- } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
- uint32_t Val = uint32_t(*CI->getValue().getRawData());
- emitWordLE(Val);
- } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
- if (CFP->getType()->isFloatTy())
- emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
- else if (CFP->getType()->isDoubleTy())
- emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
- else {
- llvm_unreachable("Unable to handle this constantpool entry!");
- }
- } else {
- llvm_unreachable("Unable to handle this constantpool entry!");
- }
+ emitConstantToMemory(CPI, MCPE.Val.ConstVal);
}
}
@@ -768,6 +816,32 @@ void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
emitWordLE(Binary);
}
+void ARMCodeEmitter::emitLEApcrelInstruction(const MachineInstr &MI) {
+ // It's basically add r, pc, (LCPI - $+8)
+ const MCInstrDesc &MCID = MI.getDesc();
+
+ unsigned Binary = 0;
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ // Encode S bit if MI modifies CPSR.
+ Binary |= getAddrModeSBit(MI, MCID);
+
+ // Encode Rd.
+ Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
+
+ // Encode Rn which is PC.
+ Binary |= II->getRegisterInfo().getEncodingValue(ARM::PC) << ARMII::RegRnShift;
+
+ // Encode the displacement which is a so_imm.
+ // Set bit I(25) to identify this is the immediate form of <shifter_op>
+ Binary |= 1 << ARMII::I_BitShift;
+ emitConstPoolAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_so_imm_cp_entry);
+
+ emitWordLE(Binary);
+}
+
void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
// It's basically add r, pc, (LJTI - $+8)
@@ -845,6 +919,14 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
switch (Opcode) {
default:
llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
+ case ARM::B:
+ emitBranchInstruction(MI);
+ break;
+ case ARM::BR_JTr:
+ case ARM::BR_JTm:
+ case ARM::BR_JTadd:
+ emitMiscBranchInstruction(MI);
+ break;
case ARM::BX_CALL:
case ARM::BMOVPCRX_CALL: {
// First emit mov lr, pc
@@ -875,6 +957,9 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
case ARM::CONSTPOOL_ENTRY:
emitConstPoolInstruction(MI);
break;
+ case ARM::LDMIA_RET:
+ emitLoadStoreMultipleInstruction(MI);
+ break;
case ARM::PICADD: {
// Remember of the address of the PC label for relocation later.
addPCLabel(MI.getOperand(2).getImm());
@@ -910,7 +995,10 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
else
emitMOVi2piecesInstruction(MI);
break;
-
+ case ARM::LEApcrel:
+ // Materialize constantpool index address.
+ emitLEApcrelInstruction(MI);
+ break;
case ARM::LEApcrelJT:
// Materialize jumptable address.
emitLEApcrelJTInstruction(MI);
@@ -1011,6 +1099,11 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
+ if (MCID.Opcode == ARM::MOVi16 || MCID.Opcode == ARM::MOVTi16) {
+ emitWordLE(Binary);
+ return;
+ }
+
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << ARMII::CondShift;
@@ -1113,11 +1206,17 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
// If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
- MI.getOpcode() == ARM::STRi12) {
+ MI.getOpcode() == ARM::STRi12 || MI.getOpcode() == ARM::LDRBi12 ||
+ MI.getOpcode() == ARM::STRBi12) {
emitWordLE(Binary);
return;
}
+ if (MI.getOpcode() == ARM::BR_JTm)
+ Binary = 0x710F000;
+ else if (MI.getOpcode() == ARM::BR_JTr)
+ Binary = 0x1A0F000;
+
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << ARMII::CondShift;
@@ -1273,6 +1372,11 @@ void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
+ if (MCID.getOpcode() == ARM::LDMIA_RET) {
+ IsUpdating = true;
+ Binary |= 0x8B00000;
+ }
+
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << ARMII::CondShift;
@@ -1480,6 +1584,10 @@ void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
+ if (MCID.Opcode == ARM::B) {
+ Binary = 0xEA000000;
+ }
+
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << ARMII::CondShift;
@@ -1554,9 +1662,10 @@ unsigned ARMCodeEmitter::encodeVFPRd(const MachineInstr &MI,
unsigned Binary = 0;
bool isSPVFP = ARM::SPRRegClass.contains(RegD);
RegD = II->getRegisterInfo().getEncodingValue(RegD);
- if (!isSPVFP)
- Binary |= RegD << ARMII::RegRdShift;
- else {
+ if (!isSPVFP) {
+ Binary |= (RegD & 0x0F) << ARMII::RegRdShift;
+ Binary |= ((RegD & 0x10) >> 4) << ARMII::D_BitShift;
+ } else {
Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
Binary |= (RegD & 0x01) << ARMII::D_BitShift;
}
@@ -1569,9 +1678,10 @@ unsigned ARMCodeEmitter::encodeVFPRn(const MachineInstr &MI,
unsigned Binary = 0;
bool isSPVFP = ARM::SPRRegClass.contains(RegN);
RegN = II->getRegisterInfo().getEncodingValue(RegN);
- if (!isSPVFP)
- Binary |= RegN << ARMII::RegRnShift;
- else {
+ if (!isSPVFP) {
+ Binary |= (RegN & 0x0F) << ARMII::RegRnShift;
+ Binary |= ((RegN & 0x10) >> 4) << ARMII::N_BitShift;
+ } else {
Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
Binary |= (RegN & 0x01) << ARMII::N_BitShift;
}
@@ -1584,9 +1694,10 @@ unsigned ARMCodeEmitter::encodeVFPRm(const MachineInstr &MI,
unsigned Binary = 0;
bool isSPVFP = ARM::SPRRegClass.contains(RegM);
RegM = II->getRegisterInfo().getEncodingValue(RegM);
- if (!isSPVFP)
- Binary |= RegM;
- else {
+ if (!isSPVFP) {
+ Binary |= (RegM & 0x0F);
+ Binary |= ((RegM & 0x10) >> 4) << ARMII::M_BitShift;
+ } else {
Binary |= ((RegM & 0x1E) >> 1);
Binary |= (RegM & 0x01) << ARMII::M_BitShift;
}
@@ -1603,9 +1714,6 @@ void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
Binary |= II->getPredicate(&MI) << ARMII::CondShift;
unsigned OpIdx = 0;
- assert((Binary & ARMII::D_BitShift) == 0 &&
- (Binary & ARMII::N_BitShift) == 0 &&
- (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
// Encode Dd / Sd.
Binary |= encodeVFPRd(MI, OpIdx++);
@@ -1695,6 +1803,12 @@ void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+ if (MI.getOpcode() == ARM::VLDRS || MI.getOpcode() == ARM::VLDRD ||
+ MI.getOpcode() == ARM::VSTRS || MI.getOpcode() == ARM::VSTRD){
+ emitWordLE(Binary);
+ return;
+ }
+
unsigned OpIdx = 0;
// Encode Dd / Sd.
@@ -1770,6 +1884,26 @@ ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
emitWordLE(Binary);
}
+void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
+ unsigned Opcode = MI.getDesc().Opcode;
+ // Part of binary is determined by TableGn.
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ if (Opcode == ARM::FCONSTS) {
+ unsigned Imm = getMachineOpValue(MI, 1);
+ Binary &= ~(0x780000 >> 19);
+ Binary |= (Imm & 0x780000) >> 19;
+ Binary &= ~(0x3800000 >> 7);
+ Binary |= (Imm & 0x3800000) >> 7;
+ Binary = VFPThumb2PostEncoder(MI, Binary);
+ }
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ emitWordLE(Binary);
+}
+
unsigned ARMCodeEmitter::encodeNEONRd(const MachineInstr &MI,
unsigned OpIdx) const {
unsigned RegD = MI.getOperand(OpIdx).getReg();
diff --git a/lib/Target/ARM/ARMRelocations.h b/lib/Target/ARM/ARMRelocations.h
index 21877fd..9c32b15 100644
--- a/lib/Target/ARM/ARMRelocations.h
+++ b/lib/Target/ARM/ARMRelocations.h
@@ -35,6 +35,10 @@ namespace llvm {
// should be divided by 4.
reloc_arm_vfp_cp_entry,
+ // reloc_arm_so_imm - Same as reloc_arm_cp_entry except contant should be
+ // encoded as so_imm value.
+ reloc_arm_so_imm_cp_entry,
+
// reloc_arm_machine_cp_entry - Relocation of a ARM machine constantpool
// entry.
reloc_arm_machine_cp_entry,
diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp
index e11314d..f4d568c 100644
--- a/lib/Target/ARM/ARMSubtarget.cpp
+++ b/lib/Target/ARM/ARMSubtarget.cpp
@@ -26,7 +26,7 @@
using namespace llvm;
-static cl::opt<bool>
+cl::opt<bool>
ReserveR9("arm-reserve-r9", cl::Hidden,
cl::desc("Reserve R9, making it unavailable as GPR"));
diff --git a/lib/Target/ARM/Android.mk b/lib/Target/ARM/Android.mk
new file mode 100644
index 0000000..0c8d7fd
--- /dev/null
+++ b/lib/Target/ARM/Android.mk
@@ -0,0 +1,84 @@
+LOCAL_PATH := $(call my-dir)
+
+arm_codegen_TBLGEN_TABLES := \
+ ARMGenRegisterInfo.inc \
+ ARMGenInstrInfo.inc \
+ ARMGenCodeEmitter.inc \
+ ARMGenMCCodeEmitter.inc \
+ ARMGenMCPseudoLowering.inc \
+ ARMGenAsmWriter.inc \
+ ARMGenAsmMatcher.inc \
+ ARMGenDAGISel.inc \
+ ARMGenFastISel.inc \
+ ARMGenCallingConv.inc \
+ ARMGenSubtargetInfo.inc \
+ ARMGenDisassemblerTables.inc
+
+arm_codegen_SRC_FILES := \
+ ARMAsmPrinter.cpp \
+ ARMBaseInstrInfo.cpp \
+ ARMBaseRegisterInfo.cpp \
+ ARMCodeEmitter.cpp \
+ ARMConstantIslandPass.cpp \
+ ARMConstantPoolValue.cpp \
+ ARMExpandPseudoInsts.cpp \
+ ARMFastISel.cpp \
+ ARMFrameLowering.cpp \
+ ARMHazardRecognizer.cpp \
+ ARMISelDAGToDAG.cpp \
+ ARMISelLowering.cpp \
+ ARMInstrInfo.cpp \
+ ARMJITInfo.cpp \
+ ARMLoadStoreOptimizer.cpp \
+ ARMMCInstLower.cpp \
+ ARMMachineFunctionInfo.cpp \
+ ARMRegisterInfo.cpp \
+ ARMSelectionDAGInfo.cpp \
+ ARMSubtarget.cpp \
+ ARMTargetMachine.cpp \
+ ARMTargetObjectFile.cpp \
+ ARMTargetTransformInfo.cpp \
+ MLxExpansionPass.cpp \
+ Thumb1FrameLowering.cpp \
+ Thumb1InstrInfo.cpp \
+ Thumb1RegisterInfo.cpp \
+ Thumb2ITBlockPass.cpp \
+ Thumb2InstrInfo.cpp \
+ Thumb2RegisterInfo.cpp \
+ Thumb2SizeReduction.cpp
+
+# For the host
+# =====================================================
+include $(CLEAR_VARS)
+include $(CLEAR_TBLGEN_VARS)
+
+LOCAL_MODULE:= libLLVMARMCodeGen
+LOCAL_MODULE_TAGS := optional
+
+LOCAL_SRC_FILES := $(arm_codegen_SRC_FILES)
+LOCAL_C_INCLUDES := $(LOCAL_PATH)/MCTargetDesc
+TBLGEN_TABLES := $(arm_codegen_TBLGEN_TABLES)
+
+include $(LLVM_HOST_BUILD_MK)
+include $(LLVM_TBLGEN_RULES_MK)
+include $(LLVM_GEN_INTRINSICS_MK)
+include $(BUILD_HOST_STATIC_LIBRARY)
+
+# For the device only
+# =====================================================
+ifeq ($(TARGET_ARCH),arm)
+include $(CLEAR_VARS)
+include $(CLEAR_TBLGEN_VARS)
+
+LOCAL_MODULE:= libLLVMARMCodeGen
+LOCAL_MODULE_TAGS := optional
+
+LOCAL_SRC_FILES := $(arm_codegen_SRC_FILES)
+LOCAL_C_INCLUDES := $(LOCAL_PATH)/MCTargetDesc
+TBLGEN_TABLES := $(arm_codegen_TBLGEN_TABLES)
+
+include $(LLVM_DEVICE_BUILD_MK)
+include $(LLVM_TBLGEN_RULES_MK)
+include $(LLVM_GEN_INTRINSICS_MK)
+include $(BUILD_STATIC_LIBRARY)
+endif
diff --git a/lib/Target/ARM/AsmParser/Android.mk b/lib/Target/ARM/AsmParser/Android.mk
new file mode 100644
index 0000000..e17a274
--- /dev/null
+++ b/lib/Target/ARM/AsmParser/Android.mk
@@ -0,0 +1,61 @@
+LOCAL_PATH := $(call my-dir)
+
+#===---------------------------------------------------------------===
+# libARMAsmParser (common)
+#===---------------------------------------------------------------===
+
+arm_asm_parser_SRC_FILES := \
+ ARMAsmParser.cpp
+
+arm_asm_parser_TBLGEN_TABLES := \
+ ARMGenInstrInfo.inc \
+ ARMGenRegisterInfo.inc \
+ ARMGenAsmMatcher.inc \
+ ARMGenSubtargetInfo.inc
+
+arm_asm_parser_TBLGEN_TD_DIR := $(LOCAL_PATH)/..
+
+arm_asm_parser_C_INCLUDES := $(LOCAL_PATH)/..
+
+
+#===---------------------------------------------------------------===
+# libARMAsmParser (host)
+#===---------------------------------------------------------------===
+include $(CLEAR_VARS)
+include $(CLEAR_TBLGEN_VARS)
+
+LOCAL_MODULE:= libLLVMARMAsmParser
+LOCAL_MODULE_TAGS := optional
+LOCAL_SRC_FILES := $(arm_asm_parser_SRC_FILES)
+LOCAL_C_INCLUDES += $(arm_asm_parser_C_INCLUDES)
+TBLGEN_TABLES := $(arm_asm_parser_TBLGEN_TABLES)
+TBLGEN_TD_DIR := $(arm_asm_parser_TBLGEN_TD_DIR)
+
+include $(LLVM_HOST_BUILD_MK)
+include $(LLVM_TBLGEN_RULES_MK)
+ifneq (,$(filter windows darwin,$(HOST_OS)))
+# Override the default optimization level to work around taking forever (~50m)
+# to compile ARMAsmParser.cpp on Mac with gcc 4.2,
+# or on Linux with mingw32msvc-gcc 4.2, which is used to cross-compile
+# the win_sdk.
+LOCAL_CFLAGS += -O0
+endif
+include $(BUILD_HOST_STATIC_LIBRARY)
+
+
+#===---------------------------------------------------------------===
+# libARMAsmParser (target)
+#===---------------------------------------------------------------===
+include $(CLEAR_VARS)
+include $(CLEAR_TBLGEN_VARS)
+
+LOCAL_MODULE:= libLLVMARMAsmParser
+LOCAL_MODULE_TAGS := optional
+LOCAL_SRC_FILES := $(arm_asm_parser_SRC_FILES)
+LOCAL_C_INCLUDES += $(arm_asm_parser_C_INCLUDES)
+TBLGEN_TABLES := $(arm_asm_parser_TBLGEN_TABLES)
+TBLGEN_TD_DIR := $(arm_asm_parser_TBLGEN_TD_DIR)
+
+include $(LLVM_DEVICE_BUILD_MK)
+include $(LLVM_TBLGEN_RULES_MK)
+include $(BUILD_STATIC_LIBRARY)
diff --git a/lib/Target/ARM/Disassembler/Android.mk b/lib/Target/ARM/Disassembler/Android.mk
new file mode 100644
index 0000000..51e364b
--- /dev/null
+++ b/lib/Target/ARM/Disassembler/Android.mk
@@ -0,0 +1,55 @@
+LOCAL_PATH := $(call my-dir)
+
+arm_disassembler_TBLGEN_TABLES := \
+ ARMGenDisassemblerTables.inc \
+ ARMGenInstrInfo.inc \
+ ARMGenSubtargetInfo.inc \
+ ARMGenRegisterInfo.inc
+
+arm_disassembler_SRC_FILES := \
+ ARMDisassembler.cpp
+
+# For the device
+# =====================================================
+ifeq ($(TARGET_ARCH),arm)
+include $(CLEAR_VARS)
+include $(CLEAR_TBLGEN_VARS)
+
+TBLGEN_TABLES := $(arm_disassembler_TBLGEN_TABLES)
+
+TBLGEN_TD_DIR := $(LOCAL_PATH)/..
+
+LOCAL_SRC_FILES := $(arm_disassembler_SRC_FILES)
+
+LOCAL_C_INCLUDES += $(LOCAL_PATH)/..
+
+LOCAL_MODULE:= libLLVMARMDisassembler
+
+LOCAL_MODULE_TAGS := optional
+
+include $(LLVM_DEVICE_BUILD_MK)
+include $(LLVM_TBLGEN_RULES_MK)
+include $(BUILD_STATIC_LIBRARY)
+endif
+
+# For the host
+# =====================================================
+include $(CLEAR_VARS)
+include $(CLEAR_TBLGEN_VARS)
+
+TBLGEN_TABLES := $(arm_disassembler_TBLGEN_TABLES)
+
+TBLGEN_TD_DIR := $(LOCAL_PATH)/..
+
+LOCAL_SRC_FILES := $(arm_disassembler_SRC_FILES)
+
+LOCAL_C_INCLUDES += $(LOCAL_PATH)/..
+
+LOCAL_MODULE:= libLLVMARMDisassembler
+
+LOCAL_MODULE_TAGS := optional
+
+include $(LLVM_HOST_BUILD_MK)
+include $(LLVM_TBLGEN_RULES_MK)
+include $(BUILD_HOST_STATIC_LIBRARY)
+
diff --git a/lib/Target/ARM/InstPrinter/Android.mk b/lib/Target/ARM/InstPrinter/Android.mk
new file mode 100644
index 0000000..a047f6f
--- /dev/null
+++ b/lib/Target/ARM/InstPrinter/Android.mk
@@ -0,0 +1,55 @@
+LOCAL_PATH := $(call my-dir)
+
+arm_asm_printer_TBLGEN_TABLES := \
+ ARMGenAsmWriter.inc \
+ ARMGenRegisterInfo.inc \
+ ARMGenSubtargetInfo.inc \
+ ARMGenInstrInfo.inc
+
+arm_asm_printer_SRC_FILES := \
+ ARMInstPrinter.cpp
+
+# For the host
+# =====================================================
+include $(CLEAR_VARS)
+include $(CLEAR_TBLGEN_VARS)
+
+TBLGEN_TABLES := $(arm_asm_printer_TBLGEN_TABLES)
+
+TBLGEN_TD_DIR := $(LOCAL_PATH)/..
+
+LOCAL_SRC_FILES := $(arm_asm_printer_SRC_FILES)
+
+LOCAL_MODULE:= libLLVMARMAsmPrinter
+
+LOCAL_C_INCLUDES += \
+ $(LOCAL_PATH)/..
+
+LOCAL_MODULE_TAGS := optional
+
+include $(LLVM_HOST_BUILD_MK)
+include $(LLVM_TBLGEN_RULES_MK)
+include $(BUILD_HOST_STATIC_LIBRARY)
+
+# For the device only
+# =====================================================
+include $(CLEAR_VARS)
+include $(CLEAR_TBLGEN_VARS)
+
+TBLGEN_TABLES := $(arm_asm_printer_TBLGEN_TABLES)
+
+TBLGEN_TD_DIR := $(LOCAL_PATH)/..
+
+LOCAL_SRC_FILES := $(arm_asm_printer_SRC_FILES)
+
+LOCAL_C_INCLUDES+= \
+ $(LOCAL_PATH)/..
+
+LOCAL_MODULE:= libLLVMARMAsmPrinter
+
+LOCAL_MODULE_TAGS := optional
+
+include $(LLVM_DEVICE_BUILD_MK)
+include $(LLVM_TBLGEN_RULES_MK)
+include $(BUILD_STATIC_LIBRARY)
+
diff --git a/lib/Target/ARM/MCTargetDesc/Android.mk b/lib/Target/ARM/MCTargetDesc/Android.mk
new file mode 100644
index 0000000..b283ec5
--- /dev/null
+++ b/lib/Target/ARM/MCTargetDesc/Android.mk
@@ -0,0 +1,58 @@
+LOCAL_PATH := $(call my-dir)
+
+arm_mc_desc_TBLGEN_TABLES := \
+ ARMGenRegisterInfo.inc \
+ ARMGenInstrInfo.inc \
+ ARMGenMCCodeEmitter.inc \
+ ARMGenSubtargetInfo.inc
+
+arm_mc_desc_SRC_FILES := \
+ ARMAsmBackend.cpp \
+ ARMELFObjectWriter.cpp \
+ ARMELFStreamer.cpp \
+ ARMMCAsmInfo.cpp \
+ ARMMCCodeEmitter.cpp \
+ ARMMCExpr.cpp \
+ ARMMCTargetDesc.cpp \
+ ARMMachObjectWriter.cpp
+
+# For the host
+# =====================================================
+include $(CLEAR_VARS)
+include $(CLEAR_TBLGEN_VARS)
+
+
+LOCAL_MODULE:= libLLVMARMDesc
+LOCAL_MODULE_TAGS := optional
+
+LOCAL_SRC_FILES := $(arm_mc_desc_SRC_FILES)
+LOCAL_C_INCLUDES := $(LOCAL_PATH)/..
+
+TBLGEN_TD_DIR := $(LOCAL_PATH)/..
+TBLGEN_TABLES := $(arm_mc_desc_TBLGEN_TABLES)
+
+include $(LLVM_HOST_BUILD_MK)
+include $(LLVM_TBLGEN_RULES_MK)
+include $(LLVM_GEN_INTRINSICS_MK)
+include $(BUILD_HOST_STATIC_LIBRARY)
+
+# For the device only
+# =====================================================
+ifeq ($(TARGET_ARCH),arm)
+include $(CLEAR_VARS)
+include $(CLEAR_TBLGEN_VARS)
+
+LOCAL_MODULE:= libLLVMARMDesc
+LOCAL_MODULE_TAGS := optional
+
+LOCAL_SRC_FILES := $(arm_mc_desc_SRC_FILES)
+LOCAL_C_INCLUDES := $(LOCAL_PATH)/..
+
+TBLGEN_TD_DIR := $(LOCAL_PATH)/..
+TBLGEN_TABLES := $(arm_mc_desc_TBLGEN_TABLES)
+
+include $(LLVM_DEVICE_BUILD_MK)
+include $(LLVM_TBLGEN_RULES_MK)
+include $(LLVM_GEN_INTRINSICS_MK)
+include $(BUILD_STATIC_LIBRARY)
+endif
diff --git a/lib/Target/ARM/TargetInfo/Android.mk b/lib/Target/ARM/TargetInfo/Android.mk
new file mode 100644
index 0000000..d1af6ae
--- /dev/null
+++ b/lib/Target/ARM/TargetInfo/Android.mk
@@ -0,0 +1,55 @@
+LOCAL_PATH := $(call my-dir)
+
+arm_target_info_TBLGEN_TABLES := \
+ ARMGenSubtargetInfo.inc \
+ ARMGenRegisterInfo.inc \
+ ARMGenInstrInfo.inc
+
+arm_target_info_SRC_FILES := \
+ ARMTargetInfo.cpp
+
+# For the host
+# =====================================================
+include $(CLEAR_VARS)
+include $(CLEAR_TBLGEN_VARS)
+
+TBLGEN_TABLES := $(arm_target_info_TBLGEN_TABLES)
+
+TBLGEN_TD_DIR := $(LOCAL_PATH)/..
+
+LOCAL_SRC_FILES := $(arm_target_info_SRC_FILES)
+
+LOCAL_C_INCLUDES += \
+ $(LOCAL_PATH)/..
+
+LOCAL_MODULE:= libLLVMARMInfo
+
+LOCAL_MODULE_TAGS := optional
+
+include $(LLVM_HOST_BUILD_MK)
+include $(LLVM_TBLGEN_RULES_MK)
+include $(BUILD_HOST_STATIC_LIBRARY)
+
+# For the device
+# =====================================================
+ifeq ($(TARGET_ARCH),arm)
+include $(CLEAR_VARS)
+include $(CLEAR_TBLGEN_VARS)
+
+TBLGEN_TABLES := $(arm_target_info_TBLGEN_TABLES)
+
+TBLGEN_TD_DIR := $(LOCAL_PATH)/..
+
+LOCAL_SRC_FILES := $(arm_target_info_SRC_FILES)
+
+LOCAL_C_INCLUDES += \
+ $(LOCAL_PATH)/..
+
+LOCAL_MODULE:= libLLVMARMInfo
+
+LOCAL_MODULE_TAGS := optional
+
+include $(LLVM_DEVICE_BUILD_MK)
+include $(LLVM_TBLGEN_RULES_MK)
+include $(BUILD_STATIC_LIBRARY)
+endif
generated by cgit v1.1 at 2025-05-14 16:44:13 +0000