diff options
Diffstat (limited to 'lib/Target/R600/SIInstrInfo.h')
| -rw-r--r-- | lib/Target/R600/SIInstrInfo.h | 80 |
1 files changed, 65 insertions, 15 deletions
diff --git a/lib/Target/R600/SIInstrInfo.h b/lib/Target/R600/SIInstrInfo.h index 87eff4d..4af6348 100644 --- a/lib/Target/R600/SIInstrInfo.h +++ b/lib/Target/R600/SIInstrInfo.h @@ -1,4 +1,4 @@ -//===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===// +//===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -25,6 +25,14 @@ class SIInstrInfo : public AMDGPUInstrInfo { private: const SIRegisterInfo RI; + MachineInstrBuilder buildIndirectIndexLoop(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned OffsetVGPR, + unsigned MovRelOp, + unsigned Dst, + unsigned Src0) const; + // If you add or remove instructions from this function, you will + public: explicit SIInstrInfo(AMDGPUTargetMachine &tm); @@ -40,25 +48,65 @@ public: virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI=false) const; - virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg, - int64_t Imm) const; - virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;} + MachineInstr *buildMovInstr(MachineBasicBlock *MBB, + MachineBasicBlock::iterator I, + unsigned DstReg, unsigned SrcReg) const; virtual bool isMov(unsigned Opcode) const; virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; - - virtual int getIndirectIndexBegin(const MachineFunction &MF) const; - - virtual int getIndirectIndexEnd(const MachineFunction &MF) const; + int isMIMG(uint16_t Opcode) const; + int isSMRD(uint16_t Opcode) const; + bool isVOP1(uint16_t Opcode) const; + bool isVOP2(uint16_t Opcode) const; + bool isVOP3(uint16_t Opcode) const; + bool isVOPC(uint16_t Opcode) const; + bool isInlineConstant(const MachineOperand &MO) const; + bool isLiteralConstant(const MachineOperand &MO) const; + + virtual bool verifyInstruction(const MachineInstr *MI, + StringRef &ErrInfo) const; + + bool isSALUInstr(const MachineInstr &MI) const; + static unsigned getVALUOp(const MachineInstr &MI); + bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const; + + /// \brief Return the correct register class for \p OpNo. For target-specific + /// instructions, this will return the register class that has been defined + /// in tablegen. For generic instructions, like REG_SEQUENCE it will return + /// the register class of its machine operand. + /// to infer the correct register class base on the other operands. + const TargetRegisterClass *getOpRegClass(const MachineInstr &MI, + unsigned OpNo) const;\ + + /// \returns true if it is legal for the operand at index \p OpNo + /// to read a VGPR. + bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const; + + /// \brief Legalize the \p OpIndex operand of this instruction by inserting + /// a MOV. For example: + /// ADD_I32_e32 VGPR0, 15 + /// to + /// MOV VGPR1, 15 + /// ADD_I32_e32 VGPR0, VGPR1 + /// + /// If the operand being legalized is a register, then a COPY will be used + /// instead of MOV. + void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const; + + /// \brief Legalize all operands in this instruction. This function may + /// create new instruction and insert them before \p MI. + void legalizeOperands(MachineInstr *MI) const; + + /// \brief Replace this instruction's opcode with the equivalent VALU + /// opcode. This function will also move the users of \p MI to the + /// VALU if necessary. + void moveToVALU(MachineInstr &MI) const; virtual unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const; - virtual const TargetRegisterClass *getIndirectAddrStoreRegClass( - unsigned SourceReg) const; - - virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const; + virtual const TargetRegisterClass *getIndirectAddrRegClass() const; virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, @@ -71,16 +119,18 @@ public: unsigned ValueReg, unsigned Address, unsigned OffsetReg) const; + void reserveIndirectRegisters(BitVector &Reserved, + const MachineFunction &MF) const; - virtual const TargetRegisterClass *getSuperIndirectRegClass() const; - }; + void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I, + unsigned SavReg, unsigned IndexReg) const; +}; namespace AMDGPU { int getVOPe64(uint16_t Opcode); int getCommuteRev(uint16_t Opcode); int getCommuteOrig(uint16_t Opcode); - int isMIMG(uint16_t Opcode); } // End namespace AMDGPU |