diff options
Diffstat (limited to 'lib/Target/Sparc')
27 files changed, 125 insertions, 53 deletions
diff --git a/lib/Target/Sparc/CMakeLists.txt b/lib/Target/Sparc/CMakeLists.txt index 56ee7c2..ae4af0f 100644 --- a/lib/Target/Sparc/CMakeLists.txt +++ b/lib/Target/Sparc/CMakeLists.txt @@ -16,6 +16,7 @@ add_llvm_target(SparcCodeGen SparcISelDAGToDAG.cpp SparcISelLowering.cpp SparcFrameLowering.cpp + SparcMachineFunctionInfo.cpp SparcRegisterInfo.cpp SparcSubtarget.cpp SparcTargetMachine.cpp diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp index 9295408..883aa3a 100644 --- a/lib/Target/Sparc/DelaySlotFiller.cpp +++ b/lib/Target/Sparc/DelaySlotFiller.cpp @@ -282,7 +282,7 @@ bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) if (RegSet.count(Reg)) return true; // check Aliased Registers - for (const unsigned *Alias = TM.getRegisterInfo()->getAliasSet(Reg); + for (const uint16_t *Alias = TM.getRegisterInfo()->getAliasSet(Reg); *Alias; ++ Alias) if (RegSet.count(*Alias)) return true; diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp index 6a7e090..f5e10fc 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp @@ -16,6 +16,8 @@ using namespace llvm; +void SparcELFMCAsmInfo::anchor() { } + SparcELFMCAsmInfo::SparcELFMCAsmInfo(const Target &T, StringRef TT) { IsLittleEndian = false; Triple TheTriple(TT); diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h b/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h index 0cb6827..616e1c5 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h @@ -1,4 +1,4 @@ -//=====-- SparcMCAsmInfo.h - Sparc asm properties -------------*- C++ -*--====// +//===-- SparcMCAsmInfo.h - Sparc asm properties ----------------*- C++ -*--===// // // The LLVM Compiler Infrastructure // @@ -20,7 +20,9 @@ namespace llvm { class Target; - struct SparcELFMCAsmInfo : public MCAsmInfo { + class SparcELFMCAsmInfo : public MCAsmInfo { + virtual void anchor(); + public: explicit SparcELFMCAsmInfo(const Target &T, StringRef TT); }; diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp index eda04c3..7fdb0c3 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -1,4 +1,4 @@ -//===-- SparcMCTargetDesc.cpp - Sparc Target Descriptions --------*- C++ -*-===// +//===-- SparcMCTargetDesc.cpp - Sparc Target Descriptions -----------------===// // // The LLVM Compiler Infrastructure // @@ -17,6 +17,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h index 7b2c614..ce6ae17 100644 --- a/lib/Target/Sparc/Sparc.h +++ b/lib/Target/Sparc/Sparc.h @@ -18,7 +18,6 @@ #include "MCTargetDesc/SparcMCTargetDesc.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetMachine.h" -#include <cassert> namespace llvm { class FunctionPass; @@ -74,7 +73,6 @@ namespace llvm { inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { switch (CC) { - default: llvm_unreachable("Unknown condition code"); case SPCC::ICC_NE: return "ne"; case SPCC::ICC_E: return "e"; case SPCC::ICC_G: return "g"; @@ -103,7 +101,8 @@ namespace llvm { case SPCC::FCC_LE: return "le"; case SPCC::FCC_ULE: return "ule"; case SPCC::FCC_O: return "o"; - } + } + llvm_unreachable("Invalid cond code"); } } // end namespace llvm #endif diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td index 7643366..611f8e8 100644 --- a/lib/Target/Sparc/Sparc.td +++ b/lib/Target/Sparc/Sparc.td @@ -1,10 +1,10 @@ -//===- Sparc.td - Describe the Sparc Target Machine --------*- tablegen -*-===// -// +//===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp index 7548bbf..c14b3d4 100644 --- a/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -62,6 +62,8 @@ namespace { virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const; + + virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const; }; } // end of anonymous namespace @@ -140,7 +142,7 @@ bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum, std::string operand = ""; const MachineOperand &MO = MI->getOperand(opNum); switch (MO.getType()) { - default: assert(0 && "Operand is not a register "); + default: llvm_unreachable("Operand is not a register"); case MachineOperand::MO_Register: assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && "Operand is not a physical register "); @@ -241,7 +243,14 @@ isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const { return I == Pred->end() || !I->isBarrier(); } - +MachineLocation SparcAsmPrinter:: +getDebugValueLocation(const MachineInstr *MI) const { + assert(MI->getNumOperands() == 4 && "Invalid number of operands!"); + assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() && + "Unexpected MachineOperand types"); + return MachineLocation(MI->getOperand(0).getReg(), + MI->getOperand(1).getImm()); +} // Force static initialization. extern "C" void LLVMInitializeSparcAsmPrinter() { diff --git a/lib/Target/Sparc/SparcCallingConv.td b/lib/Target/Sparc/SparcCallingConv.td index 856f87a..d471220 100644 --- a/lib/Target/Sparc/SparcCallingConv.td +++ b/lib/Target/Sparc/SparcCallingConv.td @@ -1,10 +1,10 @@ -//===- SparcCallingConv.td - Calling Conventions Sparc -----*- tablegen -*-===// -// +//===-- SparcCallingConv.td - Calling Conventions Sparc ----*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This describes the calling conventions for the Sparc architectures. diff --git a/lib/Target/Sparc/SparcFrameLowering.cpp b/lib/Target/Sparc/SparcFrameLowering.cpp index 320c8ca..1c5c89e 100644 --- a/lib/Target/Sparc/SparcFrameLowering.cpp +++ b/lib/Target/Sparc/SparcFrameLowering.cpp @@ -1,4 +1,4 @@ -//====- SparcFrameLowering.cpp - Sparc Frame Information -------*- C++ -*-====// +//===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/Sparc/SparcFrameLowering.h b/lib/Target/Sparc/SparcFrameLowering.h index 9a2ddc8..210705e 100644 --- a/lib/Target/Sparc/SparcFrameLowering.h +++ b/lib/Target/Sparc/SparcFrameLowering.h @@ -1,4 +1,4 @@ -//===- SparcFrameLowering.h - Define frame lowering for Sparc --*- C++ -*--===// +//===-- SparcFrameLowering.h - Define frame lowering for Sparc --*- C++ -*-===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 8c6103d..93710c4 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -176,7 +176,6 @@ SDNode *SparcDAGToDAGISel::Select(SDNode *N) { MulLHS, MulRHS); // The high part is in the Y register. return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1)); - return NULL; } } diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 3608d3b..a6b63fb 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -25,7 +25,6 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" -#include "llvm/ADT/VectorExtras.h" #include "llvm/Support/ErrorHandling.h" using namespace llvm; @@ -348,7 +347,7 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain, SDValue SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, - bool &isTailCall, + bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h index 8a1886a..4a7c479 100644 --- a/lib/Target/Sparc/SparcISelLowering.h +++ b/lib/Target/Sparc/SparcISelLowering.h @@ -77,9 +77,8 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals) const; virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, - CallingConv::ID CallConv, bool isVarArg, - bool &isTailCall, + LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, + bool isVarArg, bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/lib/Target/Sparc/SparcInstrFormats.td b/lib/Target/Sparc/SparcInstrFormats.td index 6535259..dce3312 100644 --- a/lib/Target/Sparc/SparcInstrFormats.td +++ b/lib/Target/Sparc/SparcInstrFormats.td @@ -1,10 +1,10 @@ -//===- SparcInstrFormats.td - Sparc Instruction Formats ----*- tablegen -*-===// -// +//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index 5290d42..faff468 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -1,4 +1,4 @@ -//===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===// +//===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===// // // The LLVM Compiler Infrastructure // @@ -79,7 +79,6 @@ static bool IsIntegerCC(unsigned CC) static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) { switch(CC) { - default: llvm_unreachable("Unknown condition code"); case SPCC::ICC_NE: return SPCC::ICC_E; case SPCC::ICC_E: return SPCC::ICC_NE; case SPCC::ICC_G: return SPCC::ICC_LE; @@ -110,6 +109,18 @@ static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) case SPCC::FCC_NE: return SPCC::FCC_E; case SPCC::FCC_E: return SPCC::FCC_NE; } + llvm_unreachable("Invalid cond code"); +} + +MachineInstr * +SparcInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, + int FrameIx, + uint64_t Offset, + const MDNode *MDPtr, + DebugLoc dl) const { + MachineInstrBuilder MIB = BuildMI(MF, dl, get(SP::DBG_VALUE)) + .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); + return &*MIB; } diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h index eda64ef..4932531 100644 --- a/lib/Target/Sparc/SparcInstrInfo.h +++ b/lib/Target/Sparc/SparcInstrInfo.h @@ -1,4 +1,4 @@ -//===- SparcInstrInfo.h - Sparc Instruction Information ---------*- C++ -*-===// +//===-- SparcInstrInfo.h - Sparc Instruction Information --------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -62,6 +62,13 @@ public: virtual unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; + /// emitFrameIndexDebugValue - Emit a target-dependent form of + /// DBG_VALUE encoding the address of a frame index. + virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, + int FrameIx, + uint64_t Offset, + const MDNode *MDPtr, + DebugLoc dl) const; virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index cf5c48f..15541ef 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -1,10 +1,10 @@ -//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===// -// +//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file describes the Sparc instructions in TableGen format. diff --git a/lib/Target/Sparc/SparcMachineFunctionInfo.cpp b/lib/Target/Sparc/SparcMachineFunctionInfo.cpp new file mode 100644 index 0000000..e744282 --- /dev/null +++ b/lib/Target/Sparc/SparcMachineFunctionInfo.cpp @@ -0,0 +1,14 @@ +//===-- SparcMachineFunctionInfo.cpp - Sparc Machine Function Info --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "SparcMachineFunctionInfo.h" + +using namespace llvm; + +void SparcMachineFunctionInfo::anchor() { } diff --git a/lib/Target/Sparc/SparcMachineFunctionInfo.h b/lib/Target/Sparc/SparcMachineFunctionInfo.h index 0b74308..90c27a4 100644 --- a/lib/Target/Sparc/SparcMachineFunctionInfo.h +++ b/lib/Target/Sparc/SparcMachineFunctionInfo.h @@ -18,6 +18,7 @@ namespace llvm { class SparcMachineFunctionInfo : public MachineFunctionInfo { + virtual void anchor(); private: unsigned GlobalBaseReg; diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index 8c16251..c392fcc 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -1,4 +1,4 @@ -//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===// +//===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===// // // The LLVM Compiler Infrastructure // @@ -33,9 +33,9 @@ SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, : SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) { } -const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) +const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { - static const unsigned CalleeSavedRegs[] = { 0 }; + static const uint16_t CalleeSavedRegs[] = { 0 }; return CalleeSavedRegs; } @@ -118,10 +118,8 @@ unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const { unsigned SparcRegisterInfo::getEHExceptionRegister() const { llvm_unreachable("What is the exception register"); - return 0; } unsigned SparcRegisterInfo::getEHHandlerRegister() const { llvm_unreachable("What is the exception handler register"); - return 0; } diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h index f845667..9515ad3 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.h +++ b/lib/Target/Sparc/SparcRegisterInfo.h @@ -1,4 +1,4 @@ -//===- SparcRegisterInfo.h - Sparc Register Information Impl ----*- C++ -*-===// +//===-- SparcRegisterInfo.h - Sparc Register Information Impl ---*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -32,7 +32,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo { SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii); /// Code Generation virtual methods... - const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const; + const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const; BitVector getReservedRegs(const MachineFunction &MF) const; diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index cf92829..81bff6c 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -1,10 +1,10 @@ -//===- SparcRegisterInfo.td - Sparc Register defs ----------*- tablegen -*-===// -// +//===-- SparcRegisterInfo.td - Sparc Register defs ---------*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// @@ -39,6 +39,7 @@ class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> { let Num = num; let SubRegs = subregs; let SubRegIndices = [sub_even, sub_odd]; + let CoveredBySubRegs = 1; } // Control Registers diff --git a/lib/Target/Sparc/SparcSubtarget.cpp b/lib/Target/Sparc/SparcSubtarget.cpp index 6c501cf..e5b2aeb 100644 --- a/lib/Target/Sparc/SparcSubtarget.cpp +++ b/lib/Target/Sparc/SparcSubtarget.cpp @@ -1,4 +1,4 @@ -//===- SparcSubtarget.cpp - SPARC Subtarget Information -------------------===// +//===-- SparcSubtarget.cpp - SPARC Subtarget Information ------------------===// // // The LLVM Compiler Infrastructure // @@ -21,6 +21,8 @@ using namespace llvm; +void SparcSubtarget::anchor() { } + SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) : SparcGenSubtargetInfo(TT, CPU, FS), diff --git a/lib/Target/Sparc/SparcSubtarget.h b/lib/Target/Sparc/SparcSubtarget.h index 00a04c3..a81931b 100644 --- a/lib/Target/Sparc/SparcSubtarget.h +++ b/lib/Target/Sparc/SparcSubtarget.h @@ -1,4 +1,4 @@ -//=====-- SparcSubtarget.h - Define Subtarget for the SPARC ----*- C++ -*-====// +//===-- SparcSubtarget.h - Define Subtarget for the SPARC -------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -24,6 +24,7 @@ namespace llvm { class StringRef; class SparcSubtarget : public SparcGenSubtargetInfo { + virtual void anchor(); bool IsV9; bool V8DeprecatedInsts; bool IsVIS; diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index 8e16fd7..80a3be6 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -13,6 +13,7 @@ #include "Sparc.h" #include "SparcTargetMachine.h" #include "llvm/PassManager.h" +#include "llvm/CodeGen/Passes.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -24,7 +25,7 @@ extern "C" void LLVMInitializeSparcTarget() { /// SparcTargetMachine ctor - Create an ILP32 architecture model /// -SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, +SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, @@ -37,20 +38,42 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, FrameLowering(Subtarget) { } -bool SparcTargetMachine::addInstSelector(PassManagerBase &PM) { - PM.add(createSparcISelDag(*this)); +namespace { +/// Sparc Code Generator Pass Configuration Options. +class SparcPassConfig : public TargetPassConfig { +public: + SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} + + SparcTargetMachine &getSparcTargetMachine() const { + return getTM<SparcTargetMachine>(); + } + + virtual bool addInstSelector(); + virtual bool addPreEmitPass(); +}; +} // namespace + +TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) { + return new SparcPassConfig(this, PM); +} + +bool SparcPassConfig::addInstSelector() { + PM.add(createSparcISelDag(getSparcTargetMachine())); return false; } /// addPreEmitPass - This pass may be implemented by targets that want to run /// passes immediately before machine code is emitted. This should return /// true if -print-machineinstrs should print out the code after the passes. -bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM){ - PM.add(createSparcFPMoverPass(*this)); - PM.add(createSparcDelaySlotFillerPass(*this)); +bool SparcPassConfig::addPreEmitPass(){ + PM.add(createSparcFPMoverPass(getSparcTargetMachine())); + PM.add(createSparcDelaySlotFillerPass(getSparcTargetMachine())); return true; } +void SparcV8TargetMachine::anchor() { } + SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, @@ -61,7 +84,9 @@ SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { } -SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, +void SparcV9TargetMachine::anchor() { } + +SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h index cedc1e3..b203dfa 100644 --- a/lib/Target/Sparc/SparcTargetMachine.h +++ b/lib/Target/Sparc/SparcTargetMachine.h @@ -55,13 +55,13 @@ public: virtual const TargetData *getTargetData() const { return &DataLayout; } // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM); - virtual bool addPreEmitPass(PassManagerBase &PM); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); }; /// SparcV8TargetMachine - Sparc 32-bit target machine /// class SparcV8TargetMachine : public SparcTargetMachine { + virtual void anchor(); public: SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, @@ -73,6 +73,7 @@ public: /// SparcV9TargetMachine - Sparc 64-bit target machine /// class SparcV9TargetMachine : public SparcTargetMachine { + virtual void anchor(); public: SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, |