diff options
Diffstat (limited to 'lib/Target/SparcV9')
| -rw-r--r-- | lib/Target/SparcV9/InstrSched/InstrScheduling.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/SparcV9/InstrSelection/InstrForest.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/SparcV9/InstrSelection/InstrSelection.cpp | 6 |
3 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp index 392ae04..cf4f294 100644 --- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp +++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp @@ -1060,7 +1060,7 @@ NodeCanFillDelaySlot(const SchedulingManager& S, if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode())) return false; - // Finally, if the instruction preceeds the branch, we make sure the + // Finally, if the instruction precedes the branch, we make sure the // instruction can be reordered relative to the branch. We simply check // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch. // @@ -1092,7 +1092,7 @@ MarkNodeForDelaySlot(SchedulingManager& S, bool nodeIsPredecessor) { if (nodeIsPredecessor) { - // If node is in the same basic block (i.e., preceeds brNode), + // If node is in the same basic block (i.e., precedes brNode), // remove it and all its incident edges from the graph. Make sure we // add dummy edges for pred/succ nodes that become entry/exit nodes. graph->eraseIncidentEdges(node, /*addDummyEdges*/ true); diff --git a/lib/Target/SparcV9/InstrSelection/InstrForest.cpp b/lib/Target/SparcV9/InstrSelection/InstrForest.cpp index ceaefd8..f4736b5 100644 --- a/lib/Target/SparcV9/InstrSelection/InstrForest.cpp +++ b/lib/Target/SparcV9/InstrSelection/InstrForest.cpp @@ -4,7 +4,7 @@ // tree if one or more of them might be potentially combined into a single // complex instruction in the target machine. // Since this grouping is completely machine-independent, we do it as -// aggressive as possible to exploit any possible taret instructions. +// aggressive as possible to exploit any possible target instructions. // In particular, we group two instructions O and I if: // (1) Instruction O computes an operand used by instruction I, // and (2) O and I are part of the same basic block, diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp index 49a599f..ae910b8 100644 --- a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp +++ b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp @@ -81,7 +81,7 @@ TmpInstruction::TmpInstruction(MachineCodeForInstruction& mcfi, { mcfi.addTemp(this); - Operands.push_back(Use(s1, this)); // s1 must be nonnull + Operands.push_back(Use(s1, this)); // s1 must be non-null if (s2) { Operands.push_back(Use(s2, this)); } @@ -239,7 +239,7 @@ InstructionSelection::InsertPhiElimInstructions(BasicBlock *BB, MachineFunction &MF = MachineFunction::get(BB->getParent()); // FIXME: if PHI instructions existed in the machine code, this would be - // unnecesary. + // unnecessary. MachineBasicBlock *MBB = 0; for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) if (I->getBasicBlock() == BB) { @@ -342,7 +342,7 @@ InstructionSelection::SelectInstructionsForTree(InstrTreeNode* treeRoot, } } - // Finally, do any postprocessing on this node after its children + // Finally, do any post-processing on this node after its children // have been translated // if (treeRoot->opLabel != VRegListOp) |