diff options
Diffstat (limited to 'lib/Target/X86/X86InstrFPStack.td')
| -rw-r--r-- | lib/Target/X86/X86InstrFPStack.td | 237 |
1 files changed, 119 insertions, 118 deletions
diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td index 11aeb07..3ef1cde6f 100644 --- a/lib/Target/X86/X86InstrFPStack.td +++ b/lib/Target/X86/X86InstrFPStack.td @@ -71,34 +71,34 @@ def fpimmneg1 : PatLeaf<(fpimm), [{ // Some 'special' instructions let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. def FP32_TO_INT16_IN_MEM : I<0, Pseudo, - (ops i16mem:$dst, RFP32:$src), + (outs), (ins i16mem:$dst, RFP32:$src), "#FP32_TO_INT16_IN_MEM PSEUDO!", [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; def FP32_TO_INT32_IN_MEM : I<0, Pseudo, - (ops i32mem:$dst, RFP32:$src), + (outs), (ins i32mem:$dst, RFP32:$src), "#FP32_TO_INT32_IN_MEM PSEUDO!", [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; def FP32_TO_INT64_IN_MEM : I<0, Pseudo, - (ops i64mem:$dst, RFP32:$src), + (outs), (ins i64mem:$dst, RFP32:$src), "#FP32_TO_INT64_IN_MEM PSEUDO!", [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; def FP64_TO_INT16_IN_MEM : I<0, Pseudo, - (ops i16mem:$dst, RFP64:$src), + (outs), (ins i16mem:$dst, RFP64:$src), "#FP64_TO_INT16_IN_MEM PSEUDO!", [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; def FP64_TO_INT32_IN_MEM : I<0, Pseudo, - (ops i32mem:$dst, RFP64:$src), + (outs), (ins i32mem:$dst, RFP64:$src), "#FP64_TO_INT32_IN_MEM PSEUDO!", [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; def FP64_TO_INT64_IN_MEM : I<0, Pseudo, - (ops i64mem:$dst, RFP64:$src), + (outs), (ins i64mem:$dst, RFP64:$src), "#FP64_TO_INT64_IN_MEM PSEUDO!", [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; } let isTerminator = 1 in let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in - def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>; + def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "#FP_REG_KILL", []>; // All FP Stack operations are represented with three instructions here. The // first two instructions, generated by the instruction selector, uses "RFP32" @@ -120,81 +120,82 @@ let isTerminator = 1 in // encoding and asm printing info). // FPI - Floating Point Instruction template. -class FPI<bits<8> o, Format F, dag ops, string asm> : I<o, F, ops, asm, []> {} +class FPI<bits<8> o, Format F, dag outs, dag ins, string asm> + : I<o, F, outs, ins, asm, []> {} // FpI_ - Floating Point Psuedo Instruction template. Not Predicated. -class FpI_<dag ops, FPFormat fp, list<dag> pattern> - : X86Inst<0, Pseudo, NoImm, ops, ""> { +class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern> + : X86Inst<0, Pseudo, NoImm, outs, ins, ""> { let FPForm = fp; let FPFormBits = FPForm.Value; let Pattern = pattern; } // Random Pseudo Instructions. -def FpGETRESULT32 : FpI_<(ops RFP32:$dst), SpecialFP, +def FpGETRESULT32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, [(set RFP32:$dst, X86fpget)]>; // FPR = ST(0) -def FpGETRESULT64 : FpI_<(ops RFP64:$dst), SpecialFP, +def FpGETRESULT64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, [(set RFP64:$dst, X86fpget)]>; // FPR = ST(0) let noResults = 1 in { - def FpSETRESULT32 : FpI_<(ops RFP32:$src), SpecialFP, + def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, [(X86fpset RFP32:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR - def FpSETRESULT64 : FpI_<(ops RFP64:$src), SpecialFP, + def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, [(X86fpset RFP64:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR } // FpI - Floating Point Psuedo Instruction template. Predicated on FPStack. -class FpI<dag ops, FPFormat fp, list<dag> pattern> : - FpI_<ops, fp, pattern>, Requires<[FPStack]>; +class FpI<dag outs, dag ins, FPFormat fp, list<dag> pattern> : + FpI_<outs, ins, fp, pattern>, Requires<[FPStack]>; // Register copies. Just copies, the 64->32 version does not truncate. -def MOV_Fp3232 : FpI<(ops RFP32:$dst, RFP32:$src), SpecialFP, []>; -def MOV_Fp3264 : FpI<(ops RFP64:$dst, RFP32:$src), SpecialFP, []>; -def MOV_Fp6432 : FpI<(ops RFP32:$dst, RFP64:$src), SpecialFP, []>; -def MOV_Fp6464 : FpI<(ops RFP64:$dst, RFP64:$src), SpecialFP, []>; +def MOV_Fp3232 : FpI<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>; +def MOV_Fp3264 : FpI<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>; +def MOV_Fp6432 : FpI<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>; +def MOV_Fp6464 : FpI<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>; // Factoring for arithmetic. multiclass FPBinary_rr<SDNode OpNode> { // Register op register -> register // These are separated out because they have no reversed form. -def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP, +def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; -def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP, +def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; } // The FopST0 series are not included here because of the irregularities // in where the 'r' goes in assembly output. multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> { // ST(0) = ST(0) + [mem] -def _Fp32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, +def _Fp32m : FpI<(outs RFP32:$dst), (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, [(set RFP32:$dst, (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>; -def _Fp64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, +def _Fp64m : FpI<(outs RFP64:$dst), (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, [(set RFP64:$dst, (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>; -def _Fp64m32: FpI<(ops RFP64:$dst, RFP64:$src1, f32mem:$src2), OneArgFPRW, +def _Fp64m32: FpI<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, [(set RFP64:$dst, (OpNode RFP64:$src1, (extloadf32 addr:$src2)))]>; -def _F32m : FPI<0xD8, fp, (ops f32mem:$src), +def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), !strconcat("f", !strconcat(asmstring, "{s} $src"))>; -def _F64m : FPI<0xDC, fp, (ops f64mem:$src), +def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), !strconcat("f", !strconcat(asmstring, "{l} $src"))>; // ST(0) = ST(0) + [memint] -def _FpI16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, +def _FpI16m32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW, [(set RFP32:$dst, (OpNode RFP32:$src1, (X86fild addr:$src2, i16)))]>; -def _FpI32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, +def _FpI32m32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), OneArgFPRW, [(set RFP32:$dst, (OpNode RFP32:$src1, (X86fild addr:$src2, i32)))]>; -def _FpI16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, +def _FpI16m64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFPRW, [(set RFP64:$dst, (OpNode RFP64:$src1, (X86fild addr:$src2, i16)))]>; -def _FpI32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, +def _FpI32m64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW, [(set RFP64:$dst, (OpNode RFP64:$src1, (X86fild addr:$src2, i32)))]>; -def _FI16m : FPI<0xDE, fp, (ops i16mem:$src), +def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), !strconcat("fi", !strconcat(asmstring, "{s} $src"))>; -def _FI32m : FPI<0xDA, fp, (ops i32mem:$src), +def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), !strconcat("fi", !strconcat(asmstring, "{l} $src"))>; } @@ -210,11 +211,11 @@ defm DIV : FPBinary<fdiv, MRM6m, "div">; defm DIVR: FPBinary<fdiv, MRM7m, "divr">; class FPST0rInst<bits<8> o, string asm> - : FPI<o, AddRegFrm, (ops RST:$op), asm>, D8; + : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8; class FPrST0Inst<bits<8> o, string asm> - : FPI<o, AddRegFrm, (ops RST:$op), asm>, DC; + : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC; class FPrST0PInst<bits<8> o, string asm> - : FPI<o, AddRegFrm, (ops RST:$op), asm>, DE; + : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE; // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion // of some of the 'reverse' forms of the fsub and fdiv instructions. As such, @@ -240,11 +241,11 @@ def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">; // Unary operations. multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> { -def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src), OneArgFPRW, +def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, [(set RFP32:$dst, (OpNode RFP32:$src))]>; -def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src), OneArgFPRW, +def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, [(set RFP64:$dst, (OpNode RFP64:$src))]>; -def _F : FPI<opcode, RawFrm, (ops), asmstring>, D9; +def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9; } defm CHS : FPUnary<fneg, 0xE0, "fchs">; @@ -253,18 +254,18 @@ defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">; defm SIN : FPUnary<fsin, 0xFE, "fsin">; defm COS : FPUnary<fcos, 0xFF, "fcos">; -def TST_Fp32 : FpI<(ops RFP32:$src), OneArgFP, +def TST_Fp32 : FpI<(outs), (ins RFP32:$src), OneArgFP, []>; -def TST_Fp64 : FpI<(ops RFP64:$src), OneArgFP, +def TST_Fp64 : FpI<(outs), (ins RFP64:$src), OneArgFP, []>; -def TST_F : FPI<0xE4, RawFrm, (ops), "ftst">, D9; +def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9; // Floating point cmovs. multiclass FPCMov<PatLeaf cc> { - def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, + def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), CondMovFP, [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, cc))]>; - def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, + def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), CondMovFP, [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, cc))]>; } @@ -280,154 +281,154 @@ defm CMOVNP : FPCMov<X86_COND_NP>; } // These are not factored because there's no clean way to pass DA/DB. -def CMOVB_F : FPI<0xC0, AddRegFrm, (ops RST:$op), +def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins), "fcmovb {$op, %st(0)|%ST(0), $op}">, DA; -def CMOVBE_F : FPI<0xD0, AddRegFrm, (ops RST:$op), +def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins), "fcmovbe {$op, %st(0)|%ST(0), $op}">, DA; -def CMOVE_F : FPI<0xC8, AddRegFrm, (ops RST:$op), +def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins), "fcmove {$op, %st(0)|%ST(0), $op}">, DA; -def CMOVP_F : FPI<0xD8, AddRegFrm, (ops RST:$op), +def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins), "fcmovu {$op, %st(0)|%ST(0), $op}">, DA; -def CMOVNB_F : FPI<0xC0, AddRegFrm, (ops RST:$op), +def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins), "fcmovnb {$op, %st(0)|%ST(0), $op}">, DB; -def CMOVNBE_F: FPI<0xD0, AddRegFrm, (ops RST:$op), +def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins), "fcmovnbe {$op, %st(0)|%ST(0), $op}">, DB; -def CMOVNE_F : FPI<0xC8, AddRegFrm, (ops RST:$op), +def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins), "fcmovne {$op, %st(0)|%ST(0), $op}">, DB; -def CMOVNP_F : FPI<0xD8, AddRegFrm, (ops RST:$op), +def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins), "fcmovnu {$op, %st(0)|%ST(0), $op}">, DB; // Floating point loads & stores. -def LD_Fp32m : FpI<(ops RFP32:$dst, f32mem:$src), ZeroArgFP, +def LD_Fp32m : FpI<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, [(set RFP32:$dst, (loadf32 addr:$src))]>; -def LD_Fp64m : FpI<(ops RFP64:$dst, f64mem:$src), ZeroArgFP, +def LD_Fp64m : FpI<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, [(set RFP64:$dst, (loadf64 addr:$src))]>; -def ILD_Fp16m32: FpI<(ops RFP32:$dst, i16mem:$src), ZeroArgFP, +def ILD_Fp16m32: FpI<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, [(set RFP32:$dst, (X86fild addr:$src, i16))]>; -def ILD_Fp32m32: FpI<(ops RFP32:$dst, i32mem:$src), ZeroArgFP, +def ILD_Fp32m32: FpI<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, [(set RFP32:$dst, (X86fild addr:$src, i32))]>; -def ILD_Fp64m32: FpI<(ops RFP32:$dst, i64mem:$src), ZeroArgFP, +def ILD_Fp64m32: FpI<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, [(set RFP32:$dst, (X86fild addr:$src, i64))]>; -def ILD_Fp16m64: FpI<(ops RFP64:$dst, i16mem:$src), ZeroArgFP, +def ILD_Fp16m64: FpI<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, [(set RFP64:$dst, (X86fild addr:$src, i16))]>; -def ILD_Fp32m64: FpI<(ops RFP64:$dst, i32mem:$src), ZeroArgFP, +def ILD_Fp32m64: FpI<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, [(set RFP64:$dst, (X86fild addr:$src, i32))]>; -def ILD_Fp64m64: FpI<(ops RFP64:$dst, i64mem:$src), ZeroArgFP, +def ILD_Fp64m64: FpI<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, [(set RFP64:$dst, (X86fild addr:$src, i64))]>; -def ST_Fp32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP, +def ST_Fp32m : FpI<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, [(store RFP32:$src, addr:$op)]>; -def ST_Fp64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP, +def ST_Fp64m32 : FpI<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, [(truncstoref32 RFP64:$src, addr:$op)]>; -def ST_Fp64m : FpI<(ops f64mem:$op, RFP64:$src), OneArgFP, +def ST_Fp64m : FpI<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, [(store RFP64:$src, addr:$op)]>; -def ST_FpP32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP, []>; -def ST_FpP64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP, []>; -def ST_FpP64m : FpI<(ops f64mem:$op, RFP64:$src), OneArgFP, []>; -def IST_Fp16m32 : FpI<(ops i16mem:$op, RFP32:$src), OneArgFP, []>; -def IST_Fp32m32 : FpI<(ops i32mem:$op, RFP32:$src), OneArgFP, []>; -def IST_Fp64m32 : FpI<(ops i64mem:$op, RFP32:$src), OneArgFP, []>; -def IST_Fp16m64 : FpI<(ops i16mem:$op, RFP64:$src), OneArgFP, []>; -def IST_Fp32m64 : FpI<(ops i32mem:$op, RFP64:$src), OneArgFP, []>; -def IST_Fp64m64 : FpI<(ops i64mem:$op, RFP64:$src), OneArgFP, []>; - -def LD_F32m : FPI<0xD9, MRM0m, (ops f32mem:$src), "fld{s} $src">; -def LD_F64m : FPI<0xDD, MRM0m, (ops f64mem:$src), "fld{l} $src">; -def ILD_F16m : FPI<0xDF, MRM0m, (ops i16mem:$src), "fild{s} $src">; -def ILD_F32m : FPI<0xDB, MRM0m, (ops i32mem:$src), "fild{l} $src">; -def ILD_F64m : FPI<0xDF, MRM5m, (ops i64mem:$src), "fild{ll} $src">; -def ST_F32m : FPI<0xD9, MRM2m, (ops f32mem:$dst), "fst{s} $dst">; -def ST_F64m : FPI<0xDD, MRM2m, (ops f64mem:$dst), "fst{l} $dst">; -def ST_FP32m : FPI<0xD9, MRM3m, (ops f32mem:$dst), "fstp{s} $dst">; -def ST_FP64m : FPI<0xDD, MRM3m, (ops f64mem:$dst), "fstp{l} $dst">; -def IST_F16m : FPI<0xDF, MRM2m, (ops i16mem:$dst), "fist{s} $dst">; -def IST_F32m : FPI<0xDB, MRM2m, (ops i32mem:$dst), "fist{l} $dst">; -def IST_FP16m : FPI<0xDF, MRM3m, (ops i16mem:$dst), "fistp{s} $dst">; -def IST_FP32m : FPI<0xDB, MRM3m, (ops i32mem:$dst), "fistp{l} $dst">; -def IST_FP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">; +def ST_FpP32m : FpI<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; +def ST_FpP64m32 : FpI<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; +def ST_FpP64m : FpI<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; +def IST_Fp16m32 : FpI<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; +def IST_Fp32m32 : FpI<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; +def IST_Fp64m32 : FpI<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; +def IST_Fp16m64 : FpI<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; +def IST_Fp32m64 : FpI<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; +def IST_Fp64m64 : FpI<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; + +def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s} $src">; +def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l} $src">; +def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s} $src">; +def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l} $src">; +def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll} $src">; +def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s} $dst">; +def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l} $dst">; +def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s} $dst">; +def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l} $dst">; +def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s} $dst">; +def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l} $dst">; +def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s} $dst">; +def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l} $dst">; +def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll} $dst">; // FISTTP requires SSE3 even though it's a FPStack op. -def ISTT_Fp16m32 : FpI_<(ops i16mem:$op, RFP32:$src), OneArgFP, +def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, [(X86fp_to_i16mem RFP32:$src, addr:$op)]>, Requires<[HasSSE3]>; -def ISTT_Fp32m32 : FpI_<(ops i32mem:$op, RFP32:$src), OneArgFP, +def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, [(X86fp_to_i32mem RFP32:$src, addr:$op)]>, Requires<[HasSSE3]>; -def ISTT_Fp64m32 : FpI_<(ops i64mem:$op, RFP32:$src), OneArgFP, +def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, [(X86fp_to_i64mem RFP32:$src, addr:$op)]>, Requires<[HasSSE3]>; -def ISTT_Fp16m64 : FpI_<(ops i16mem:$op, RFP64:$src), OneArgFP, +def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, [(X86fp_to_i16mem RFP64:$src, addr:$op)]>, Requires<[HasSSE3]>; -def ISTT_Fp32m64 : FpI_<(ops i32mem:$op, RFP64:$src), OneArgFP, +def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, [(X86fp_to_i32mem RFP64:$src, addr:$op)]>, Requires<[HasSSE3]>; -def ISTT_Fp64m64 : FpI_<(ops i64mem:$op, RFP64:$src), OneArgFP, +def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, [(X86fp_to_i64mem RFP64:$src, addr:$op)]>, Requires<[HasSSE3]>; -def ISTT_FP16m : FPI<0xDF, MRM1m, (ops i16mem:$dst), "fisttp{s} $dst">; -def ISTT_FP32m : FPI<0xDB, MRM1m, (ops i32mem:$dst), "fisttp{l} $dst">; -def ISTT_FP64m : FPI<0xDD, MRM1m, (ops i64mem:$dst), "fisttp{ll} $dst">; +def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s} $dst">; +def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l} $dst">; +def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll} $dst">; // FP Stack manipulation instructions. -def LD_Frr : FPI<0xC0, AddRegFrm, (ops RST:$op), "fld $op">, D9; -def ST_Frr : FPI<0xD0, AddRegFrm, (ops RST:$op), "fst $op">, DD; -def ST_FPrr : FPI<0xD8, AddRegFrm, (ops RST:$op), "fstp $op">, DD; -def XCH_F : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9; +def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld $op">, D9; +def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst $op">, DD; +def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp $op">, DD; +def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch $op">, D9; // Floating point constant loads. let isReMaterializable = 1 in { -def LD_Fp032 : FpI<(ops RFP32:$dst), ZeroArgFP, +def LD_Fp032 : FpI<(outs RFP32:$dst), (ins), ZeroArgFP, [(set RFP32:$dst, fpimm0)]>; -def LD_Fp132 : FpI<(ops RFP32:$dst), ZeroArgFP, +def LD_Fp132 : FpI<(outs RFP32:$dst), (ins), ZeroArgFP, [(set RFP32:$dst, fpimm1)]>; -def LD_Fp064 : FpI<(ops RFP64:$dst), ZeroArgFP, +def LD_Fp064 : FpI<(outs RFP64:$dst), (ins), ZeroArgFP, [(set RFP64:$dst, fpimm0)]>; -def LD_Fp164 : FpI<(ops RFP64:$dst), ZeroArgFP, +def LD_Fp164 : FpI<(outs RFP64:$dst), (ins), ZeroArgFP, [(set RFP64:$dst, fpimm1)]>; } -def LD_F0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9; -def LD_F1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9; +def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9; +def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9; // Floating point compares. -def UCOM_Fpr32 : FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP, +def UCOM_Fpr32 : FpI<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, []>; // FPSW = cmp ST(0) with ST(i) -def UCOM_FpIr32: FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP, +def UCOM_FpIr32: FpI<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, [(X86cmp RFP32:$lhs, RFP32:$rhs)]>; // CC = ST(0) cmp ST(i) -def UCOM_Fpr64 : FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP, +def UCOM_Fpr64 : FpI<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, []>; // FPSW = cmp ST(0) with ST(i) -def UCOM_FpIr64: FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP, +def UCOM_FpIr64: FpI<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, [(X86cmp RFP64:$lhs, RFP64:$rhs)]>; // CC = ST(0) cmp ST(i) def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i) - (ops RST:$reg), + (outs), (ins RST:$reg), "fucom $reg">, DD, Imp<[ST0],[]>; def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop - (ops RST:$reg), + (outs), (ins RST:$reg), "fucomp $reg">, DD, Imp<[ST0],[]>; def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop - (ops), + (outs), (ins), "fucompp">, DA, Imp<[ST0],[]>; def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i) - (ops RST:$reg), + (outs), (ins RST:$reg), "fucomi {$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>; def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop - (ops RST:$reg), + (outs), (ins RST:$reg), "fucomip {$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>; // Floating point flag ops. def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags - (ops), "fnstsw", []>, DF, Imp<[],[AX]>; + (outs), (ins), "fnstsw", []>, DF, Imp<[],[AX]>; def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world - (ops i16mem:$dst), "fnstcw $dst", []>; + (outs), (ins i16mem:$dst), "fnstcw $dst", []>; def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] - (ops i16mem:$dst), "fldcw $dst", []>; + (outs), (ins i16mem:$dst), "fldcw $dst", []>; //===----------------------------------------------------------------------===// // Non-Instruction Patterns |