diff options
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/Alpha/AlphaISelDAGToDAG.cpp | 75 | ||||
-rw-r--r-- | lib/Target/IA64/IA64ISelDAGToDAG.cpp | 142 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 147 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcISelDAGToDAG.cpp | 53 | ||||
-rw-r--r-- | lib/Target/X86/X86ISelDAGToDAG.cpp | 36 |
5 files changed, 247 insertions, 206 deletions
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 19328c0..1a442c0 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -194,10 +194,11 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { Chain.getValue(1)); Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0, Chain.getValue(1)); - Chain = CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag, - Chain, Chain.getValue(1)); + SDNode *CNode = + CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag, + Chain, Chain.getValue(1)); Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64, - Chain.getValue(1)); + SDOperand(CNode, 1)); Result = CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain); return; } @@ -255,10 +256,11 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { MachineConstantPool *CP = BB->getParent()->getConstantPool(); ConstantUInt *C = ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval); - SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64); - Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg()); + SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64); + SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, + getGlobalBaseReg()); Result = CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, - CPI, Tmp, CurDAG->getEntryNode()); + CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode()); return; } case ISD::TargetConstantFP: { @@ -299,30 +301,31 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { SDOperand tmp1, tmp2; Select(tmp1, N->getOperand(0)); Select(tmp2, N->getOperand(1)); - SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64, - rev?tmp2:tmp1, - rev?tmp1:tmp2); + SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, + rev?tmp2:tmp1, + rev?tmp1:tmp2); if (isNE) - cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, cmp, + cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0), CurDAG->getRegister(Alpha::F31, MVT::f64)); SDOperand LD; if (AlphaLowering.hasITOF()) { - LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, cmp); + LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0)); } else { int FrameIdx = CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8); SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64); - SDOperand ST = CurDAG->getTargetNode(Alpha::STT, MVT::Other, - cmp, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)); - LD = CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI, - CurDAG->getRegister(Alpha::R31, MVT::i64), - ST); + SDOperand ST = + SDOperand(CurDAG->getTargetNode(Alpha::STT, MVT::Other, + SDOperand(cmp, 0), FI, + CurDAG->getRegister(Alpha::R31, MVT::i64)), 0); + LD = SDOperand(CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI, + CurDAG->getRegister(Alpha::R31, MVT::i64), + ST), 0); } - SDOperand FP = CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, - CurDAG->getRegister(Alpha::R31, MVT::i64), - LD); - Result = FP; + Result = SDOperand(CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, + CurDAG->getRegister(Alpha::R31, MVT::i64), + LD), 0); return; } break; @@ -347,15 +350,15 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { int FrameIdx = CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8); SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64); - SDOperand ST = CurDAG->getTargetNode(Alpha::STQ, MVT::Other, - cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)); - LD = CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI, - CurDAG->getRegister(Alpha::R31, MVT::i64), - ST); + SDOperand ST = + SDOperand(CurDAG->getTargetNode(Alpha::STQ, MVT::Other, + cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)), 0); + LD = SDOperand(CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI, + CurDAG->getRegister(Alpha::R31, MVT::i64), + ST), 0); } - SDOperand FP = CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES, - MVT::f64, FV, TV, LD); - Result = FP; + Result = SDOperand(CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES, + MVT::f64, FV, TV, LD), 0); return; } break; @@ -401,10 +404,10 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { Opc = Alpha::STT; } else assert(0 && "Unknown operand"); - Chain = CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i], - getI64Imm((i - 6) * 8), - CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64), - Chain); + Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i], + getI64Imm((i - 6) * 8), + CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64), + Chain), 0); } for (int i = 0; i < std::min(6, count); ++i) { if (MVT::isInteger(TypeOperands[i])) { @@ -424,14 +427,14 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { SDOperand GOT = getGlobalBaseReg(); Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag); InFlag = Chain.getValue(1); - Chain = CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag, - Addr.getOperand(0), Chain, InFlag); + Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag, + Addr.getOperand(0), Chain, InFlag), 0); } else { Select(Addr, Addr); Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag); InFlag = Chain.getValue(1); - Chain = CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag, - Chain, InFlag ); + Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag, + Chain, InFlag), 0); } InFlag = Chain.getValue(1); diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp index 295b382..0f4d84e 100644 --- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -186,7 +186,7 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) { SDOperand TmpPR, TmpPR2; SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8; SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15; - SDOperand Result; + SDNode *Result; // we'll need copies of F0 and F1 SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64); @@ -196,21 +196,27 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) { if(!isFP) { // first, load the inputs into FP regs. - TmpF1 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1); + TmpF1 = + SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0); Chain = TmpF1.getValue(1); - TmpF2 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2); + TmpF2 = + SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0); Chain = TmpF2.getValue(1); // next, convert the inputs to FP if(isSigned) { - TmpF3 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1); + TmpF3 = + SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0); Chain = TmpF3.getValue(1); - TmpF4 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2); + TmpF4 = + SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0); Chain = TmpF4.getValue(1); } else { // is unsigned - TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1); + TmpF3 = + SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0); Chain = TmpF3.getValue(1); - TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2); + TmpF4 = + SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0); Chain = TmpF4.getValue(1); } @@ -223,11 +229,11 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) { // we start by computing an approximate reciprocal (good to 9 bits?) // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate) if(isFP) - TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1, - TmpF3, TmpF4); + TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1, + TmpF3, TmpF4), 0); else - TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1, - TmpF3, TmpF4); + TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1, + TmpF3, TmpF4), 0); TmpPR = TmpF5.getValue(1); Chain = TmpF5.getValue(2); @@ -235,24 +241,24 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) { SDOperand minusB; if(isModulus) { // for remainders, it'll be handy to have // copies of -input_b - minusB = CurDAG->getTargetNode(IA64::SUB, MVT::i64, - CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2); + minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64, + CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0); Chain = minusB.getValue(1); } SDOperand TmpE0, TmpY1, TmpE1, TmpY2; - TmpE0 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64, - TmpF4, TmpF5, F1, TmpPR); + TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64, + TmpF4, TmpF5, F1, TmpPR), 0); Chain = TmpE0.getValue(1); - TmpY1 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, - TmpF5, TmpE0, TmpF5, TmpPR); + TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpF5, TmpE0, TmpF5, TmpPR), 0); Chain = TmpY1.getValue(1); - TmpE1 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, - TmpE0, TmpE0, F0, TmpPR); + TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpE0, TmpE0, F0, TmpPR), 0); Chain = TmpE1.getValue(1); - TmpY2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, - TmpY1, TmpE1, TmpY1, TmpPR); + TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpY1, TmpE1, TmpY1, TmpPR), 0); Chain = TmpY2.getValue(1); if(isFP) { // if this is an FP divide, we finish up here and exit early @@ -261,42 +267,44 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) { SDOperand TmpE2, TmpY3, TmpQ0, TmpR0; - TmpE2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, - TmpE1, TmpE1, F0, TmpPR); + TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpE1, TmpE1, F0, TmpPR), 0); Chain = TmpE2.getValue(1); - TmpY3 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, - TmpY2, TmpE2, TmpY2, TmpPR); + TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpY2, TmpE2, TmpY2, TmpPR), 0); Chain = TmpY3.getValue(1); - TmpQ0 = CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec! - Tmp1, TmpY3, F0, TmpPR); + TmpQ0 = + SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec! + Tmp1, TmpY3, F0, TmpPR), 0); Chain = TmpQ0.getValue(1); - TmpR0 = CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec! - Tmp2, TmpQ0, Tmp1, TmpPR); + TmpR0 = + SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec! + Tmp2, TmpQ0, Tmp1, TmpPR), 0); Chain = TmpR0.getValue(1); // we want Result to have the same target register as the frcpa, so // we two-address hack it. See the comment "for this to work..." on // page 48 of Intel application note #245415 Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg! - TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR); - Chain = Result.getValue(1); - return Result; // XXX: early exit! + TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR); + Chain = SDOperand(Result, 1); + return SDOperand(Result, 0); // XXX: early exit! } else { // this is *not* an FP divide, so there's a bit left to do: SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ; - TmpQ2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, - TmpF3, TmpY2, F0, TmpPR); + TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpF3, TmpY2, F0, TmpPR), 0); Chain = TmpQ2.getValue(1); - TmpR2 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64, - TmpF4, TmpQ2, TmpF3, TmpPR); + TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64, + TmpF4, TmpQ2, TmpF3, TmpPR), 0); Chain = TmpR2.getValue(1); // we want TmpQ3 to have the same target register as the frcpa? maybe we // should two-address hack it. See the comment "for this to work..." on page // 48 of Intel application note #245415 - TmpQ3 = CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64, - TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR); + TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64, + TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR), 0); Chain = TmpQ3.getValue(1); // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0) @@ -304,27 +312,30 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) { // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0. if(isSigned) - TmpQ = CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, MVT::f64, TmpQ3); + TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, + MVT::f64, TmpQ3), 0); else - TmpQ = CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, MVT::f64, TmpQ3); + TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, + MVT::f64, TmpQ3), 0); Chain = TmpQ.getValue(1); if(isModulus) { - SDOperand FPminusB = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, - minusB); + SDOperand FPminusB = + SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0); Chain = FPminusB.getValue(1); - SDOperand Remainder = CurDAG->getTargetNode(IA64::XMAL, MVT::f64, - TmpQ, FPminusB, TmpF1); + SDOperand Remainder = + SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64, + TmpQ, FPminusB, TmpF1), 0); Chain = Remainder.getValue(1); Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder); - Chain = Result.getValue(1); + Chain = SDOperand(Result, 1); } else { // just an integer divide Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ); - Chain = Result.getValue(1); + Chain = SDOperand(Result, 1); } - return Result; + return SDOperand(Result, 0); } // wasn't an FP divide } @@ -380,14 +391,15 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { // load the branch target's entry point [mem] and // GP value [mem+8] - SDOperand targetEntryPoint=CurDAG->getTargetNode(IA64::LD8, MVT::i64, - FnDescriptor); + SDOperand targetEntryPoint= + SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, FnDescriptor), 0); Chain = targetEntryPoint.getValue(1); - SDOperand targetGPAddr=CurDAG->getTargetNode(IA64::ADDS, MVT::i64, - FnDescriptor, CurDAG->getConstant(8, MVT::i64)); + SDOperand targetGPAddr= + SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64, + FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0); Chain = targetGPAddr.getValue(1); - SDOperand targetGP=CurDAG->getTargetNode(IA64::LD8, MVT::i64, - targetGPAddr); + SDOperand targetGP= + SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0); Chain = targetGP.getValue(1); Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag); @@ -401,9 +413,11 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { // Finally, once everything is setup, emit the call itself if(InFlag.Val) - Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, InFlag); + Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, + CallOperand, InFlag), 0); else // there might be no arguments - Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, Chain); + Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, + CallOperand, Chain), 0); InFlag = Chain.getValue(1); std::vector<SDOperand> CallResults; @@ -420,7 +434,7 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { case IA64ISD::GETFD: { SDOperand Input; Select(Input, N->getOperand(0)); - Result = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input); + Result = SDOperand(CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input), 0); CodeGenMap[Op] = Result; return; } @@ -451,8 +465,8 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { Result = CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64, CurDAG->getTargetFrameIndex(FI, MVT::i64)); else - Result = CodeGenMap[Op] = CurDAG->getTargetNode(IA64::MOV, MVT::i64, - CurDAG->getTargetFrameIndex(FI, MVT::i64)); + Result = CodeGenMap[Op] = SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64, + CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0); return; } @@ -462,17 +476,17 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { Constant *C = CP->get(); SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64, CP->getAlignment()); - Result = CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ? - CurDAG->getRegister(IA64::r1, MVT::i64), CPI); + Result = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ? + CurDAG->getRegister(IA64::r1, MVT::i64), CPI), 0); return; } case ISD::GlobalAddress: { GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal(); SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64); - SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, - CurDAG->getRegister(IA64::r1, MVT::i64), GA); - Result = CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp); + SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, + CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0); + Result = SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp), 0); return; } @@ -501,7 +515,7 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { Opc = IA64::LD1; // first we load a byte, then compare for != 0 if(N->getValueType(0) == MVT::i1) { // XXX: early exit! Result = CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, - CurDAG->getTargetNode(Opc, MVT::i64, Address), + SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0), CurDAG->getRegister(IA64::r0, MVT::i64), Chain).getValue(Op.ResNo); return; diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 828fd45..08fdcb4 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -368,17 +368,15 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) { SDOperand Tmp; Select(Tmp, N->getOperand(0).getOperand(0)); - Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Tmp, - getI32Imm(SH), getI32Imm(0), getI32Imm(31)); - return Op0.Val; + return CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Tmp, + getI32Imm(SH), getI32Imm(0), getI32Imm(31)); } SDOperand Tmp1, Tmp2; Select(Tmp1, ((Op0IsAND && fullMask) ? Op0.getOperand(0) : Op0)); Select(Tmp2, (IsAndWithShiftOp ? Op1.getOperand(0).getOperand(0) : Op1.getOperand(0))); - Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2, - getI32Imm(SH), getI32Imm(MB), getI32Imm(ME)); - return Op0.Val; + return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2, + getI32Imm(SH), getI32Imm(MB), getI32Imm(ME)); } return 0; } @@ -467,17 +465,17 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, unsigned Imm; if (isIntImmediate(RHS, Imm) && ((U && isUInt16(Imm)) || (!U && isInt16(Imm)))) - return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32, - LHS, getI32Imm(Imm & 0xFFFF)); + return SDOperand(CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, + MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0); Select(RHS, RHS); - return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32, - LHS, RHS); + return SDOperand(CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32, + LHS, RHS), 0); } else if (LHS.getValueType() == MVT::f32) { Select(RHS, RHS); - return CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, RHS); + return SDOperand(CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, RHS), 0); } else { Select(RHS, RHS); - return CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, RHS); + return SDOperand(CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, RHS), 0); } } @@ -552,7 +550,8 @@ SDOperand PPCDAGToDAGISel::SelectADD_PARTS(SDOperand Op) { } std::vector<SDOperand> Result; - SDOperand CarryFromLo, Tmp; + SDOperand Tmp; + SDNode *CarryFromLo; if (isIntImmediate(N->getOperand(2), Imm) && ((signed)Imm >= -32768 || (signed)Imm < 32768)) { // Codegen the low 32 bits of the add. Interestingly, there is no @@ -564,21 +563,22 @@ SDOperand PPCDAGToDAGISel::SelectADD_PARTS(SDOperand Op) { CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag, LHSL, Tmp); } - CarryFromLo = CarryFromLo.getValue(1); // Codegen the high 32 bits, adding zero, minus one, or the full value // along with the carry flag produced by addc/addic. SDOperand ResultHi; if (ZE) - ResultHi = CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, CarryFromLo); + ResultHi = SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, + SDOperand(CarryFromLo, 1)), 0); else if (ME) - ResultHi = CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, CarryFromLo); + ResultHi = SDOperand(CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, + SDOperand(CarryFromLo, 1)), 0); else { Select(Tmp, N->getOperand(3)); - ResultHi = CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH, - Tmp, CarryFromLo); + ResultHi = SDOperand(CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH, + Tmp, SDOperand(CarryFromLo, 1)), 0); } - Result.push_back(CarryFromLo.getValue(0)); + Result.push_back(SDOperand(CarryFromLo, 0)); Result.push_back(ResultHi); CodeGenMap[Op.getValue(0)] = Result[0]; @@ -594,10 +594,11 @@ SDOperand PPCDAGToDAGISel::SelectSUB_PARTS(SDOperand Op) { Select(RHSH, N->getOperand(3)); std::vector<SDOperand> Result; - Result.push_back(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, MVT::Flag, - RHSL, LHSL)); - Result.push_back(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, RHSH, LHSH, - Result[0].getValue(1))); + Result.push_back(SDOperand(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, + MVT::Flag, RHSL, LHSL), 0)); + Result.push_back(SDOperand(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, + RHSH, LHSH, + Result[0].getValue(1)), 0)); CodeGenMap[Op.getValue(0)] = Result[0]; CodeGenMap[Op.getValue(1)] = Result[1]; return Result[Op.ResNo]; @@ -617,12 +618,13 @@ SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { switch (CC) { default: break; case ISD::SETEQ: - Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op); + Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0); return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27), getI32Imm(5), getI32Imm(31)); case ISD::SETNE: { - SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, - Op, getI32Imm(~0U)); + SDOperand AD = + SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, + Op, getI32Imm(~0U)), 0); return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1)); } @@ -630,8 +632,9 @@ SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1), getI32Imm(31), getI32Imm(31)); case ISD::SETGT: { - SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op); - T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);; + SDOperand T = + SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0); + T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0); return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1), getI32Imm(31), getI32Imm(31)); } @@ -642,29 +645,31 @@ SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { switch (CC) { default: break; case ISD::SETEQ: - Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, - Op, getI32Imm(1)); + Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, + Op, getI32Imm(1)), 0); return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, - CurDAG->getTargetNode(PPC::LI, MVT::i32, - getI32Imm(0)), + SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32, + getI32Imm(0)), 0), Op.getValue(1)); case ISD::SETNE: { - Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op); - SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, - Op, getI32Imm(~0U)); - return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, - AD.getValue(1)); + Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0); + SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, + Op, getI32Imm(~0U)); + return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0), Op, + SDOperand(AD, 1)); } case ISD::SETLT: { - SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op, - getI32Imm(1)); - SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op); + SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op, + getI32Imm(1)), 0); + SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, + Op), 0); return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1), getI32Imm(31), getI32Imm(31)); } case ISD::SETGT: - Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1), - getI32Imm(31), getI32Imm(31)); + Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, + getI32Imm(1), getI32Imm(31), + getI32Imm(31)), 0); return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1)); } } @@ -683,9 +688,10 @@ SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { InFlag).getValue(1); if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor()) - IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg); + IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, + CCReg), 0); else - IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg); + IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0); if (!Inv) { return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR, @@ -693,9 +699,9 @@ SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { getI32Imm(31), getI32Imm(31)); } else { SDOperand Tmp = - CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR, - getI32Imm((32-(3-Idx)) & 31), - getI32Imm(31),getI32Imm(31)); + SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR, + getI32Imm((32-(3-Idx)) & 31), + getI32Imm(31),getI32Imm(31)), 0); return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); } } @@ -733,7 +739,8 @@ SDOperand PPCDAGToDAGISel::SelectCALL(SDOperand Op) { // Copy the callee address into the CTR register. SDOperand Callee; Select(Callee, N->getOperand(1)); - Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain); + Chain = SDOperand(CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, + Chain), 0); // Copy the callee address into R12 on darwin. SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32); @@ -783,8 +790,8 @@ SDOperand PPCDAGToDAGISel::SelectCALL(SDOperand Op) { CallOperands.push_back(InFlag); // Strong dep on register copies. else CallOperands.push_back(Chain); // Weak dep on whatever occurs before - Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, - CallOperands); + Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, + CallOperands), 0); std::vector<SDOperand> CallResults; @@ -864,9 +871,9 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { return; } Result = CodeGenMap[Op] = - CurDAG->getTargetNode(PPC::ADDI, MVT::i32, - CurDAG->getTargetFrameIndex(FI, MVT::i32), - getI32Imm(0)); + SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, + CurDAG->getTargetFrameIndex(FI, MVT::i32), + getI32Imm(0)), 0); return; } case ISD::SDIV: { @@ -880,18 +887,19 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { SDOperand N0; Select(N0, N->getOperand(0)); if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { - SDOperand Op = + SDNode *Op = CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, N0, getI32Imm(Log2_32(Imm))); Result = CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, - Op.getValue(0), Op.getValue(1)); + SDOperand(Op, 0), SDOperand(Op, 1)); } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { - SDOperand Op = + SDNode *Op = CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, N0, getI32Imm(Log2_32(-Imm))); SDOperand PT = - CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, Op.getValue(0), - Op.getValue(1)); + SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, + SDOperand(Op, 0), SDOperand(Op, 1)), + 0); Result = CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); } return; @@ -935,9 +943,10 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { SDOperand Tmp1, Tmp2; Select(Tmp1, N->getOperand(0).getOperand(0)); Select(Tmp2, N->getOperand(0).getOperand(1)); - Result = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2, - getI32Imm(0), getI32Imm(MB), - getI32Imm(ME)); + Result = SDOperand(CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, + Tmp1, Tmp2, + getI32Imm(0), getI32Imm(MB), + getI32Imm(ME)), 0); return; } } @@ -994,11 +1003,12 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { N2C->getValue() == 1ULL && CC == ISD::SETNE) { SDOperand LHS; Select(LHS, N->getOperand(0)); - SDOperand Tmp = + SDNode *Tmp = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, LHS, getI32Imm(~0U)); - Result = CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, Tmp, LHS, - Tmp.getValue(1)); + Result = CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, + SDOperand(Tmp, 0), LHS, + SDOperand(Tmp, 1)); return; } @@ -1048,10 +1058,11 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { } unsigned Opc = getBCCForSetCC(CC); - SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other, - CondCode, getI32Imm(Opc), - CondTrueBlock, CondFalseBlock, - Chain); + SDOperand CB = + SDOperand(CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other, + CondCode, getI32Imm(Opc), + CondTrueBlock, CondFalseBlock, + Chain), 0); Result = CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, CondFalseBlock, CB); } else { // Iterate to the next basic block diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 2924e7e..a58b2c1 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -1052,9 +1052,9 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { } Result = CodeGenMap[Op] = - CurDAG->getTargetNode(SP::ADDri, MVT::i32, - CurDAG->getTargetFrameIndex(FI, MVT::i32), - CurDAG->getTargetConstant(0, MVT::i32)); + SDOperand(CurDAG->getTargetNode(SP::ADDri, MVT::i32, + CurDAG->getTargetFrameIndex(FI, MVT::i32), + CurDAG->getTargetConstant(0, MVT::i32)), 0); return; } case ISD::ADD_PARTS: { @@ -1064,10 +1064,12 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { Select(RHSL, N->getOperand(2)); Select(RHSH, N->getOperand(3)); // FIXME, handle immediate RHS. - SDOperand Low = CurDAG->getTargetNode(SP::ADDCCrr, MVT::i32, MVT::Flag, - LHSL, RHSL); - SDOperand Hi = CurDAG->getTargetNode(SP::ADDXrr, MVT::i32, LHSH, RHSH, - Low.getValue(1)); + SDOperand Low = + SDOperand(CurDAG->getTargetNode(SP::ADDCCrr, MVT::i32, MVT::Flag, + LHSL, RHSL), 0); + SDOperand Hi = + SDOperand(CurDAG->getTargetNode(SP::ADDXrr, MVT::i32, LHSH, RHSH, + Low.getValue(1)), 0); CodeGenMap[SDOperand(N, 0)] = Low; CodeGenMap[SDOperand(N, 1)] = Hi; Result = Op.ResNo ? Hi : Low; @@ -1079,10 +1081,12 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { Select(LHSH, N->getOperand(1)); Select(RHSL, N->getOperand(2)); Select(RHSH, N->getOperand(3)); - SDOperand Low = CurDAG->getTargetNode(SP::SUBCCrr, MVT::i32, MVT::Flag, - LHSL, RHSL); - SDOperand Hi = CurDAG->getTargetNode(SP::SUBXrr, MVT::i32, LHSH, RHSH, - Low.getValue(1)); + SDOperand Low = + SDOperand(CurDAG->getTargetNode(SP::SUBCCrr, MVT::i32, MVT::Flag, + LHSL, RHSL), 0); + SDOperand Hi = + SDOperand(CurDAG->getTargetNode(SP::SUBXrr, MVT::i32, LHSH, RHSH, + Low.getValue(1)), 0); CodeGenMap[SDOperand(N, 0)] = Low; CodeGenMap[SDOperand(N, 1)] = Hi; Result = Op.ResNo ? Hi : Low; @@ -1098,13 +1102,13 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { // Set the Y register to the high-part. SDOperand TopPart; if (N->getOpcode() == ISD::SDIV) { - TopPart = CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, - CurDAG->getTargetConstant(31, MVT::i32)); + TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, + CurDAG->getTargetConstant(31, MVT::i32)), 0); } else { TopPart = CurDAG->getRegister(SP::G0, MVT::i32); } - TopPart = CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, - CurDAG->getRegister(SP::G0, MVT::i32)); + TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, + CurDAG->getRegister(SP::G0, MVT::i32)), 0); // FIXME: Handle div by immediate. unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; @@ -1118,10 +1122,10 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { Select(MulLHS, N->getOperand(0)); Select(MulRHS, N->getOperand(1)); unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; - SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, + SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, MulLHS, MulRHS); // The high part is in the Y register. - Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, Mul.getValue(1)); + Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); return; } case SPISD::CALL: @@ -1136,17 +1140,18 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { SDOperand Chain = N->getOperand(0); SDOperand Tmp0 = N1; Select(Chain, Chain); + SDNode *ResNode; if (N->getNumOperands() == 3) { Select(InFlag, N->getOperand(2)); - Result = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0, - Chain, InFlag); + ResNode = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0, + Chain, InFlag); } else { - Result = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0, - Chain); + ResNode = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0, + Chain); } - Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); - CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); - Result = Result.getValue(Op.ResNo); + Chain = CodeGenMap[SDOperand(N, 0)] = SDOperand(ResNode, 0); + CodeGenMap[SDOperand(N, 1)] = SDOperand(ResNode, 1); + Result = SDOperand(ResNode, Op.ResNo); return; } P47Fail:; diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index d2bfc58..b387d1b 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -521,12 +521,15 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) { Select(Tmp1, Tmp1); Select(Tmp2, Tmp2); Select(Tmp3, Tmp3); - Chain = CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1, - Tmp2, Tmp3, Chain, InFlag); - InFlag = Chain.getValue(1); + SDNode *CNode = + CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1, + Tmp2, Tmp3, Chain, InFlag); + Chain = SDOperand(CNode, 0); + InFlag = SDOperand(CNode, 1); } else { Select(N1, N1); - InFlag = CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag); + InFlag = + SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0); } Result = CurDAG->getCopyFromReg(Chain, HiReg, NVT, InFlag); @@ -601,12 +604,13 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) { if (isSigned) { // Sign extend the low part into the high part. - InFlag = CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag); + InFlag = + SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0); } else { // Zero out the high part, effectively zero extending the input. SDOperand ClrNode = - CurDAG->getTargetNode(ClrOpcode, NVT, - CurDAG->getTargetConstant(0, NVT)); + SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT, + CurDAG->getTargetConstant(0, NVT)), 0); Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(HiReg, NVT), ClrNode, InFlag); InFlag = Chain.getValue(1); @@ -617,12 +621,15 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) { Select(Tmp1, Tmp1); Select(Tmp2, Tmp2); Select(Tmp3, Tmp3); - Chain = CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1, - Tmp2, Tmp3, Chain, InFlag); - InFlag = Chain.getValue(1); + SDNode *CNode = + CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1, + Tmp2, Tmp3, Chain, InFlag); + Chain = SDOperand(CNode, 0); + InFlag = SDOperand(CNode, 1); } else { Select(N1, N1); - InFlag = CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag); + InFlag = + SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0); } Result = CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg, @@ -645,7 +652,7 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) { } SDOperand Tmp0, Tmp1; Select(Tmp0, Node->getOperand(0)); - Select(Tmp1, CurDAG->getTargetNode(Opc, VT, Tmp0)); + Select(Tmp1, SDOperand(CurDAG->getTargetNode(Opc, VT, Tmp0), 0)); SDOperand InFlag = SDOperand(0,0); Result = CurDAG->getCopyToReg(CurDAG->getEntryNode(), Reg, Tmp1, InFlag); SDOperand Chain = Result.getValue(0); @@ -659,9 +666,10 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) { Result = CurDAG->getCopyFromReg(Chain, Reg, VT, InFlag); if (N.Val->hasOneUse()) - Result =CurDAG->SelectNodeTo(N.Val, Opc, VT, Result); + Result = CurDAG->SelectNodeTo(N.Val, Opc, VT, Result); else - Result = CodeGenMap[N] = CurDAG->getTargetNode(Opc, VT, Result); + Result = CodeGenMap[N] = + SDOperand(CurDAG->getTargetNode(Opc, VT, Result), 0); return; } } |