diff options
Diffstat (limited to 'lib/Target')
22 files changed, 262 insertions, 259 deletions
diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp index e7da3cf..f577de5 100644 --- a/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -288,8 +288,8 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &Fn) { void ARMConstantIslands::DoInitialPlacement(MachineFunction &Fn, std::vector<MachineInstr*> &CPEMIs){ // Create the basic block to hold the CPE's. - MachineBasicBlock *BB = new MachineBasicBlock(); - Fn.getBasicBlockList().push_back(BB); + MachineBasicBlock *BB = Fn.CreateMachineBasicBlock(); + Fn.push_back(BB); // Add all of the constants from the constant pool to the end block, use an // identity mapping of CPI's to CPE's. @@ -558,11 +558,12 @@ void ARMConstantIslands::UpdateForInsertedWaterBlock(MachineBasicBlock *NewBB) { /// account for this change and returns the newly created block. MachineBasicBlock *ARMConstantIslands::SplitBlockBeforeInstr(MachineInstr *MI) { MachineBasicBlock *OrigBB = MI->getParent(); + MachineFunction &MF = *OrigBB->getParent(); // Create a new MBB for the code after the OrigBB. - MachineBasicBlock *NewBB = new MachineBasicBlock(OrigBB->getBasicBlock()); + MachineBasicBlock *NewBB = MF.CreateMachineBasicBlock(OrigBB->getBasicBlock()); MachineFunction::iterator MBBI = OrigBB; ++MBBI; - OrigBB->getParent()->getBasicBlockList().insert(MBBI, NewBB); + MF.insert(MBBI, NewBB); // Splice the instructions starting with MI over to NewBB. NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end()); @@ -590,7 +591,7 @@ MachineBasicBlock *ARMConstantIslands::SplitBlockBeforeInstr(MachineInstr *MI) { // Update internal data structures to account for the newly inserted MBB. // This is almost the same as UpdateForInsertedWaterBlock, except that // the Water goes after OrigBB, not NewBB. - NewBB->getParent()->RenumberBlocks(NewBB); + MF.RenumberBlocks(NewBB); // Insert a size into BBSizes to align it properly with the (newly // renumbered) block numbers. @@ -1031,8 +1032,8 @@ bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &Fn, } // Okay, we know we can put an island before NewMBB now, do it! - MachineBasicBlock *NewIsland = new MachineBasicBlock(); - Fn.getBasicBlockList().insert(NewMBB, NewIsland); + MachineBasicBlock *NewIsland = Fn.CreateMachineBasicBlock(); + Fn.insert(NewMBB, NewIsland); // Update internal data structures to account for the newly inserted MBB. UpdateForInsertedWaterBlock(NewIsland); @@ -1201,7 +1202,7 @@ ARMConstantIslands::FixUpConditionalBr(MachineFunction &Fn, ImmBranch &Br) { NumCBrFixed++; if (BMI != MI) { - if (next(MachineBasicBlock::iterator(MI)) == MBB->back() && + if (next(MachineBasicBlock::iterator(MI)) == prior(MBB->end()) && BMI->getOpcode() == Br.UncondBr) { // Last MI in the BB is a unconditional branch. Can we simply invert the // condition and swap destinations: diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 57044e5..07c88fd 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -1446,7 +1446,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // destination vreg to set, the condition code register to branch on, the // true/false values to select between, and a branch opcode to use. const BasicBlock *LLVM_BB = BB->getBasicBlock(); - ilist<MachineBasicBlock>::iterator It = BB; + MachineFunction::iterator It = BB; ++It; // thisMBB: @@ -1456,13 +1456,13 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // bCC copy1MBB // fallthrough --> copy0MBB MachineBasicBlock *thisMBB = BB; - MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); - MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); + MachineFunction *F = BB->getParent(); + MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB) .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); - MachineFunction *F = BB->getParent(); - F->getBasicBlockList().insert(It, copy0MBB); - F->getBasicBlockList().insert(It, sinkMBB); + F->insert(It, copy0MBB); + F->insert(It, sinkMBB); // Update machine-CFG edges by first adding all successors of the current // block to the new block which will contain the Phi node for the select. for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), @@ -1491,7 +1491,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); - delete MI; // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } } diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 95e4000..9a8d7da 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -152,7 +152,7 @@ void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB, return; } - MachineInstr *MI = Orig->clone(); + MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); MI->getOperand(0).setReg(DestReg); MBB.insert(I, MI); } @@ -196,6 +196,7 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, return NULL; MachineInstr *MI = MBBI; + MachineFunction &MF = *MI->getParent()->getParent(); unsigned TSFlags = MI->getDesc().TSFlags; bool isPre = false; switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { @@ -240,17 +241,17 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, // Can't encode it in a so_imm operand. This transformation will // add more than 1 instruction. Abandon! return NULL; - UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) + UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) .addReg(BaseReg).addImm(SOImmVal) .addImm(Pred).addReg(0).addReg(0); } else if (Amt != 0) { ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); - UpdateMI = BuildMI(get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) + UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) .addImm(Pred).addReg(0).addReg(0); } else - UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) + UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) .addReg(BaseReg).addReg(OffReg) .addImm(Pred).addReg(0).addReg(0); break; @@ -260,11 +261,11 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, unsigned Amt = ARM_AM::getAM3Offset(OffImm); if (OffReg == 0) // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. - UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) + UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) .addReg(BaseReg).addImm(Amt) .addImm(Pred).addReg(0).addReg(0); else - UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) + UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) .addReg(BaseReg).addReg(OffReg) .addImm(Pred).addReg(0).addReg(0); break; @@ -274,19 +275,19 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, std::vector<MachineInstr*> NewMIs; if (isPre) { if (isLoad) - MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg()) + MemMI = BuildMI(MF, get(MemOpc), MI->getOperand(0).getReg()) .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); else - MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg()) + MemMI = BuildMI(MF, get(MemOpc)).addReg(MI->getOperand(1).getReg()) .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); NewMIs.push_back(MemMI); NewMIs.push_back(UpdateMI); } else { if (isLoad) - MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg()) + MemMI = BuildMI(MF, get(MemOpc), MI->getOperand(0).getReg()) .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); else - MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg()) + MemMI = BuildMI(MF, get(MemOpc)).addReg(MI->getOperand(1).getReg()) .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); if (WB.isDead()) UpdateMI->getOperand(0).setIsDead(); @@ -537,7 +538,7 @@ void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, if (AFI->isThumbFunction()) { Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR; MachineInstrBuilder MIB = - BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); NewMIs.push_back(MIB); @@ -552,7 +553,7 @@ void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } MachineInstrBuilder MIB = - BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); AddDefaultPred(MIB); @@ -592,7 +593,7 @@ void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); if (AFI->isThumbFunction()) { Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR; - MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); NewMIs.push_back(MIB); @@ -606,7 +607,7 @@ void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, Opc = ARM::FLDS; } - MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); AddDefaultPred(MIB); @@ -641,7 +642,7 @@ bool ARMInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, return false; bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; - MachineInstr *PopMI = new MachineInstr(get(ARM::tPOP)); + MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP)); MBB.insert(MI, PopMI); for (unsigned i = CSI.size(); i != 0; --i) { unsigned Reg = CSI[i-1].getReg(); @@ -678,12 +679,12 @@ MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineFunction &MF, if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(get(ARM::STR)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, get(ARM::STR)).addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(get(ARM::LDR)).addReg(DstReg, true, false, false, isDead) + NewMI = BuildMI(MF, get(ARM::LDR)).addReg(DstReg, true, false, false, isDead) .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } break; @@ -695,7 +696,7 @@ MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineFunction &MF, if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg)) // tSpill cannot take a high register operand. break; - NewMI = BuildMI(get(ARM::tSpill)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); @@ -703,7 +704,7 @@ MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineFunction &MF, // tRestore cannot target a high register operand. break; bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(get(ARM::tRestore)) + NewMI = BuildMI(MF, get(ARM::tRestore)) .addReg(DstReg, true, false, false, isDead) .addFrameIndex(FI).addImm(0); } @@ -714,11 +715,11 @@ MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineFunction &MF, unsigned PredReg = MI->getOperand(3).getReg(); if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); - NewMI = BuildMI(get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) + NewMI = BuildMI(MF, get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) .addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); - NewMI = BuildMI(get(ARM::FLDS), DstReg).addFrameIndex(FI) + NewMI = BuildMI(MF, get(ARM::FLDS), DstReg).addFrameIndex(FI) .addImm(0).addImm(Pred).addReg(PredReg); } break; @@ -729,12 +730,12 @@ MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineFunction &MF, if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(get(ARM::FSTD)).addReg(SrcReg, false, false, isKill) + NewMI = BuildMI(MF, get(ARM::FSTD)).addReg(SrcReg, false, false, isKill) .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(get(ARM::FLDD)).addReg(DstReg, true, false, false, isDead) + NewMI = BuildMI(MF, get(ARM::FLDD)).addReg(DstReg, true, false, false, isDead) .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } break; @@ -924,7 +925,7 @@ unsigned ARMInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { MachineOperand JTOP = MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); unsigned JTI = JTOP.getIndex(); - MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); + const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); assert(JTI < JT.size()); // Thumb instructions are 2 byte aligned, but JT entries are 4 byte diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index bf3a31d..0f7fd80 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -662,18 +662,18 @@ AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, //test sc and maybe branck to start //exit: const BasicBlock *LLVM_BB = BB->getBasicBlock(); - ilist<MachineBasicBlock>::iterator It = BB; + MachineFunction::iterator It = BB; ++It; MachineBasicBlock *thisMBB = BB; - MachineBasicBlock *llscMBB = new MachineBasicBlock(LLVM_BB); - MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); + MachineFunction *F = BB->getParent(); + MachineBasicBlock *llscMBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); sinkMBB->transferSuccessors(thisMBB); - MachineFunction *F = BB->getParent(); - F->getBasicBlockList().insert(It, llscMBB); - F->getBasicBlockList().insert(It, sinkMBB); + F->insert(It, llscMBB); + F->insert(It, sinkMBB); BuildMI(thisMBB, TII->get(Alpha::BR)).addMBB(llscMBB); @@ -719,7 +719,7 @@ AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, thisMBB->addSuccessor(llscMBB); llscMBB->addSuccessor(llscMBB); llscMBB->addSuccessor(sinkMBB); - delete MI; // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return sinkMBB; } diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 6f96ff0..a602770 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -194,7 +194,7 @@ void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, else abort(); MachineInstrBuilder MIB = - BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isRegister()) @@ -239,7 +239,7 @@ void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, else abort(); MachineInstrBuilder MIB = - BuildMI(get(Opc), DestReg); + BuildMI(MF, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isRegister()) @@ -272,7 +272,7 @@ MachineInstr *AlphaInstrInfo::foldMemoryOperand(MachineFunction &MF, bool isKill = MI->getOperand(1).isKill(); Opc = (Opc == Alpha::BISr) ? Alpha::STQ : ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); - NewMI = BuildMI(get(Opc)).addReg(InReg, false, false, isKill) + NewMI = BuildMI(MF, get(Opc)).addReg(InReg, false, false, isKill) .addFrameIndex(FrameIndex) .addReg(Alpha::F31); } else { // load -> move @@ -280,7 +280,7 @@ MachineInstr *AlphaInstrInfo::foldMemoryOperand(MachineFunction &MF, bool isDead = MI->getOperand(0).isDead(); Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); - NewMI = BuildMI(get(Opc)).addReg(OutReg, true, false, false, isDead) + NewMI = BuildMI(MF, get(Opc)).addReg(OutReg, true, false, false, isDead) .addFrameIndex(FrameIndex) .addReg(Alpha::F31); } diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index e0859b5..dd8460a 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -103,7 +103,7 @@ BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const { // if frame pointer elimination is disabled. // bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const { - MachineFrameInfo *MFI = MF.getFrameInfo(); + const MachineFrameInfo *MFI = MF.getFrameInfo(); return MFI->hasVarSizedObjects(); } @@ -125,11 +125,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineInstr *New; if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) { - New=BuildMI(TII.get(Alpha::LDA), Alpha::R30) + New=BuildMI(MF, TII.get(Alpha::LDA), Alpha::R30) .addImm(-Amount).addReg(Alpha::R30); } else { assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP); - New=BuildMI(TII.get(Alpha::LDA), Alpha::R30) + New=BuildMI(MF, TII.get(Alpha::LDA), Alpha::R30) .addImm(Amount).addReg(Alpha::R30); } @@ -188,7 +188,7 @@ void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false); MI.getOperand(i).ChangeToImmediate(getLower16(Offset)); //insert the new - MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28) + MachineInstr* nMI=BuildMI(MF, TII.get(Alpha::LDAH), Alpha::R28) .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); MBB.insert(II, nMI); } else { diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index aef3611..3998b98 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -291,7 +291,7 @@ void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(get(Opc)) + MachineInstrBuilder MIB = BuildMI(MF, get(Opc)) .addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; @@ -378,7 +378,7 @@ void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isRegister()) @@ -414,7 +414,7 @@ SPUInstrInfo::foldMemoryOperand(MachineFunction &MF, unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); if (FrameIndex < SPUFrameInfo::maxFrameOffset()) { - NewMI = addFrameReference(BuildMI(TII.get(SPU::STQDr32)) + NewMI = addFrameReference(BuildMI(MF, TII.get(SPU::STQDr32)) .addReg(InReg, false, false, isKill), FrameIndex); } @@ -423,7 +423,7 @@ SPUInstrInfo::foldMemoryOperand(MachineFunction &MF, bool isDead = MI->getOperand(0).isDead(); Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) ? SPU::STQDr32 : SPU::STQXr32; - NewMI = addFrameReference(BuildMI(TII.get(Opc)) + NewMI = addFrameReference(BuildMI(MF, TII.get(Opc)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } } diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp index 2ba2c8f..211c63e 100644 --- a/lib/Target/IA64/IA64InstrInfo.cpp +++ b/lib/Target/IA64/IA64InstrInfo.cpp @@ -117,7 +117,7 @@ void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, "sorry, I don't know how to store this sort of reg\n"); } - MachineInstrBuilder MIB = BuildMI(get(Opc)); + MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isRegister()) @@ -169,7 +169,7 @@ void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, "sorry, I don't know how to store this sort of reg\n"); } - MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isRegister()) diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp index 8da2ed8..848eab8 100644 --- a/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/lib/Target/IA64/IA64RegisterInfo.cpp @@ -94,18 +94,15 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); Amount = (Amount+Align-1)/Align*Align; - MachineInstr *New; + // Replace the pseudo instruction with a new instruction... if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) { - New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12) + BuildMI(MBB, I, TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12) .addImm(-Amount); } else { assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP); - New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12) + BuildMI(MBB, I, TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12) .addImm(Amount); } - - // Replace the pseudo instruction with a new instruction... - MBB.insert(I, New); } } @@ -148,18 +145,14 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // Fix up the old: MI.getOperand(i).ChangeToRegister(IA64::r22, false); //insert the new - MachineInstr* nMI=BuildMI(TII.get(IA64::ADDIMM22), IA64::r22) + BuildMI(MBB, II, TII.get(IA64::ADDIMM22), IA64::r22) .addReg(BaseRegister).addImm(Offset); - MBB.insert(II, nMI); } else { // it's big //fix up the old: MI.getOperand(i).ChangeToRegister(IA64::r22, false); - MachineInstr* nMI; - nMI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset); - MBB.insert(II, nMI); - nMI=BuildMI(TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister) + BuildMI(MBB, II, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset); + BuildMI(MBB, II, TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister) .addReg(IA64::r22); - MBB.insert(II, nMI); } } @@ -168,7 +161,6 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); - MachineInstr *MI; bool FP = hasFP(MF); // first, we handle the 'alloc' instruction, that should be right up the @@ -212,9 +204,9 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const { } } - MI=BuildMI(TII.get(IA64::ALLOC)).addReg(dstRegOfPseudoAlloc).addImm(0). \ + BuildMI(MBB, MBBI, TII.get(IA64::ALLOC)). + addReg(dstRegOfPseudoAlloc).addImm(0). addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0); - MBB.insert(MBBI, MI); // Get the number of bytes to allocate from the FrameInfo unsigned NumBytes = MFI->getStackSize(); @@ -237,24 +229,23 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const { // adjust stack pointer: r12 -= numbytes if (NumBytes <= 8191) { - MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12). + BuildMI(MBB, MBBI, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12). addImm(-NumBytes); - MBB.insert(MBBI, MI); } else { // we use r22 as a scratch register here - MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes); + // first load the decrement into r22 + BuildMI(MBB, MBBI, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes); // FIXME: MOVLSI32 expects a _u_32imm - MBB.insert(MBBI, MI); // first load the decrement into r22 - MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).addReg(IA64::r22); - MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr) + // then add (subtract) it to r12 (stack ptr) + BuildMI(MBB, MBBI, TII.get(IA64::ADD), IA64::r12) + .addReg(IA64::r12).addReg(IA64::r22); + } // now if we need to, save the old FP and set the new if (FP) { - MI = BuildMI(TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5); - MBB.insert(MBBI, MI); + BuildMI(MBB, MBBI, TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5); // this must be the last instr in the prolog ? (XXX: why??) - MI = BuildMI(TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12); - MBB.insert(MBBI, MI); + BuildMI(MBB, MBBI, TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12); } } @@ -263,7 +254,6 @@ void IA64RegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); MachineBasicBlock::iterator MBBI = prior(MBB.end()); - MachineInstr *MI; assert(MBBI->getOpcode() == IA64::RET && "Can only insert epilog into returning blocks"); @@ -276,25 +266,21 @@ void IA64RegisterInfo::emitEpilogue(MachineFunction &MF, if (FP) { //copy the FP into the SP (discards allocas) - MI=BuildMI(TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5); - MBB.insert(MBBI, MI); + BuildMI(MBB, MBBI, TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5); //restore the FP - MI=BuildMI(TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5); - MBB.insert(MBBI, MI); + BuildMI(MBB, MBBI, TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5); } if (NumBytes != 0) { if (NumBytes <= 8191) { - MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12). + BuildMI(MBB, MBBI, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12). addImm(NumBytes); - MBB.insert(MBBI, MI); } else { - MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(NumBytes); - MBB.insert(MBBI, MI); - MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12). + BuildMI(MBB, MBBI, TII.get(IA64::MOVLIMM64), IA64::r22). + addImm(NumBytes); + BuildMI(MBB, MBBI, TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12). addReg(IA64::r22); - MBB.insert(MBBI, MI); } } diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 830534b..323af2a 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -169,7 +169,7 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // destination vreg to set, the condition code register to branch on, the // true/false values to select between, and a branch opcode to use. const BasicBlock *LLVM_BB = BB->getBasicBlock(); - ilist<MachineBasicBlock>::iterator It = BB; + MachineFunction::iterator It = BB; ++It; // thisMBB: @@ -179,13 +179,13 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // bNE r1, r0, copy1MBB // fallthrough --> copy0MBB MachineBasicBlock *thisMBB = BB; - MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); - MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); + MachineFunction *F = BB->getParent(); + MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg()) .addReg(Mips::ZERO).addMBB(sinkMBB); - MachineFunction *F = BB->getParent(); - F->getBasicBlockList().insert(It, copy0MBB); - F->getBasicBlockList().insert(It, sinkMBB); + F->insert(It, copy0MBB); + F->insert(It, sinkMBB); // Update machine-CFG edges by first adding all successors of the current // block to the new block which will contain the Phi node for the select. for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), @@ -214,7 +214,7 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB); - delete MI; // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } } diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index cc29bae..403adec 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -190,7 +190,7 @@ void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, else assert(0 && "Can't store this register"); - MachineInstrBuilder MIB = BuildMI(get(Opc)) + MachineInstrBuilder MIB = BuildMI(MF, get(Opc)) .addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; @@ -241,7 +241,7 @@ void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, else assert(0 && "Can't load this register"); - MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isRegister()) @@ -273,12 +273,12 @@ foldMemoryOperand(MachineFunction &MF, if (Ops[0] == 0) { // COPY -> STORE unsigned SrcReg = MI->getOperand(2).getReg(); bool isKill = MI->getOperand(2).isKill(); - NewMI = BuildMI(get(Mips::SW)).addFrameIndex(FI) + NewMI = BuildMI(MF, get(Mips::SW)).addFrameIndex(FI) .addImm(0).addReg(SrcReg, false, false, isKill); } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(get(Mips::LW)) + NewMI = BuildMI(MF, get(Mips::LW)) .addReg(DstReg, true, false, false, isDead) .addImm(0).addFrameIndex(FI); } @@ -304,12 +304,12 @@ foldMemoryOperand(MachineFunction &MF, if (Ops[0] == 0) { // COPY -> STORE unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(get(StoreOpc)).addFrameIndex(FI) + NewMI = BuildMI(MF, get(StoreOpc)).addFrameIndex(FI) .addImm(0).addReg(SrcReg, false, false, isKill); } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(get(LoadOpc)) + NewMI = BuildMI(MF, get(LoadOpc)) .addReg(DstReg, true, false, false, isDead) .addImm(0).addFrameIndex(FI); } diff --git a/lib/Target/PIC16/PIC16RegisterInfo.cpp b/lib/Target/PIC16/PIC16RegisterInfo.cpp index 88e84ac..9a83155 100644 --- a/lib/Target/PIC16/PIC16RegisterInfo.cpp +++ b/lib/Target/PIC16/PIC16RegisterInfo.cpp @@ -61,7 +61,7 @@ void PIC16RegisterInfo::reMaterialize(MachineBasicBlock &MBB, unsigned DestReg, const MachineInstr *Orig) const { - MachineInstr *MI = Orig->clone(); + MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); MI->getOperand(0).setReg(DestReg); MBB.insert(I, MI); } diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index d44dc5d..4650ad7 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -3992,7 +3992,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // to set, the condition code register to branch on, the true/false values to // select between, and a branch opcode to use. const BasicBlock *LLVM_BB = BB->getBasicBlock(); - ilist<MachineBasicBlock>::iterator It = BB; + MachineFunction::iterator It = BB; ++It; // thisMBB: @@ -4002,14 +4002,14 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // bCC copy1MBB // fallthrough --> copy0MBB MachineBasicBlock *thisMBB = BB; - MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); - MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); + MachineFunction *F = BB->getParent(); + MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); unsigned SelectPred = MI->getOperand(4).getImm(); BuildMI(BB, TII->get(PPC::BCC)) .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); - MachineFunction *F = BB->getParent(); - F->getBasicBlockList().insert(It, copy0MBB); - F->getBasicBlockList().insert(It, sinkMBB); + F->insert(It, copy0MBB); + F->insert(It, sinkMBB); // Update machine-CFG edges by transferring all successors of the current // block to the new block which will contain the Phi node for the select. sinkMBB->transferSuccessors(BB); @@ -4033,7 +4033,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); - delete MI; // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index a387f38..2bf92e9 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -138,6 +138,8 @@ unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI, // rotate amt is zero. We also have to munge the immediates a bit. MachineInstr * PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { + MachineFunction &MF = *MI->getParent()->getParent(); + // Normal instructions can be commuted the obvious way. if (MI->getOpcode() != PPC::RLWIMI) return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); @@ -178,7 +180,8 @@ PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { // Create a new instruction. unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); bool Reg0IsDead = MI->getOperand(0).isDead(); - return BuildMI(MI->getDesc()).addReg(Reg0, true, false, false, Reg0IsDead) + return BuildMI(MF, MI->getDesc()) + .addReg(Reg0, true, false, false, Reg0IsDead) .addReg(Reg2, false, false, Reg2IsKill) .addReg(Reg1, false, false, Reg1IsKill) .addImm((ME+1) & 31) @@ -343,47 +346,48 @@ void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB, } bool -PPCInstrInfo::StoreRegToStackSlot(unsigned SrcReg, bool isKill, +PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, + unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const{ if (RC == PPC::GPRCRegisterClass) { if (SrcReg != PPC::LR) { - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW)) + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else { // FIXME: this spills LR immediately to memory in one step. To do this, // we use R11, which we know cannot be used in the prolog/epilog. This is // a hack. - NewMIs.push_back(BuildMI(get(PPC::MFLR), PPC::R11)); - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW)) + NewMIs.push_back(BuildMI(MF, get(PPC::MFLR), PPC::R11)); + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW)) .addReg(PPC::R11, false, false, isKill), FrameIdx)); } } else if (RC == PPC::G8RCRegisterClass) { if (SrcReg != PPC::LR8) { - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STD)) + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else { // FIXME: this spills LR immediately to memory in one step. To do this, // we use R11, which we know cannot be used in the prolog/epilog. This is // a hack. - NewMIs.push_back(BuildMI(get(PPC::MFLR8), PPC::X11)); - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STD)) + NewMIs.push_back(BuildMI(MF, get(PPC::MFLR8), PPC::X11)); + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD)) .addReg(PPC::X11, false, false, isKill), FrameIdx)); } } else if (RC == PPC::F8RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STFD)) + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFD)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else if (RC == PPC::F4RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STFS)) + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFS)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else if (RC == PPC::CRRCRegisterClass) { if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { // FIXME (64-bit): Enable - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::SPILL_CR)) + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::SPILL_CR)) .addReg(SrcReg, false, false, isKill), FrameIdx)); return true; @@ -391,18 +395,18 @@ PPCInstrInfo::StoreRegToStackSlot(unsigned SrcReg, bool isKill, // FIXME: We use R0 here, because it isn't available for RA. We need to // store the CR in the low 4-bits of the saved value. First, issue a MFCR // to save all of the CRBits. - NewMIs.push_back(BuildMI(get(PPC::MFCR), PPC::R0)); + NewMIs.push_back(BuildMI(MF, get(PPC::MFCR), PPC::R0)); // If the saved register wasn't CR0, shift the bits left so that they are // in CR0's slot. if (SrcReg != PPC::CR0) { unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; // rlwinm r0, r0, ShiftBits, 0, 31. - NewMIs.push_back(BuildMI(get(PPC::RLWINM), PPC::R0) + NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0) .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31)); } - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW)) + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW)) .addReg(PPC::R0, false, false, isKill), FrameIdx)); } @@ -429,7 +433,7 @@ PPCInstrInfo::StoreRegToStackSlot(unsigned SrcReg, bool isKill, else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN) Reg = PPC::CR7; - return StoreRegToStackSlot(Reg, isKill, FrameIdx, + return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx, PPC::CRRCRegisterClass, NewMIs); } else if (RC == PPC::VRRCRegisterClass) { @@ -438,9 +442,9 @@ PPCInstrInfo::StoreRegToStackSlot(unsigned SrcReg, bool isKill, // STVX VAL, 0, R0 // // FIXME: We use R0 here, because it isn't available for RA. - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::ADDI), PPC::R0), + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0), FrameIdx, 0, 0)); - NewMIs.push_back(BuildMI(get(PPC::STVX)) + NewMIs.push_back(BuildMI(MF, get(PPC::STVX)) .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0)); } else { assert(0 && "Unknown regclass!"); @@ -455,10 +459,11 @@ PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC) const { + MachineFunction &MF = *MBB.getParent(); SmallVector<MachineInstr*, 4> NewMIs; - if (StoreRegToStackSlot(SrcReg, isKill, FrameIdx, RC, NewMIs)) { - PPCFunctionInfo *FuncInfo = MBB.getParent()->getInfo<PPCFunctionInfo>(); + if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) { + PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); FuncInfo->setSpillsCR(); } @@ -472,7 +477,8 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const{ if (Addr[0].isFrameIndex()) { - if (StoreRegToStackSlot(SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs)) { + if (StoreRegToStackSlot(MF, SrcReg, isKill, + Addr[0].getIndex(), RC, NewMIs)) { PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); FuncInfo->setSpillsCR(); } @@ -495,7 +501,7 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(get(Opc)) + MachineInstrBuilder MIB = BuildMI(MF, get(Opc)) .addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; @@ -511,36 +517,37 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } void -PPCInstrInfo::LoadRegFromStackSlot(unsigned DestReg, int FrameIdx, +PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, + unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs)const{ if (RC == PPC::GPRCRegisterClass) { if (DestReg != PPC::LR) { - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), DestReg), + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), DestReg), FrameIdx)); } else { - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), PPC::R11), + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R11), FrameIdx)); - NewMIs.push_back(BuildMI(get(PPC::MTLR)).addReg(PPC::R11)); + NewMIs.push_back(BuildMI(MF, get(PPC::MTLR)).addReg(PPC::R11)); } } else if (RC == PPC::G8RCRegisterClass) { if (DestReg != PPC::LR8) { - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LD), DestReg), + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), DestReg), FrameIdx)); } else { - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LD), PPC::R11), + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), PPC::R11), FrameIdx)); - NewMIs.push_back(BuildMI(get(PPC::MTLR8)).addReg(PPC::R11)); + NewMIs.push_back(BuildMI(MF, get(PPC::MTLR8)).addReg(PPC::R11)); } } else if (RC == PPC::F8RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LFD), DestReg), + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFD), DestReg), FrameIdx)); } else if (RC == PPC::F4RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LFS), DestReg), + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFS), DestReg), FrameIdx)); } else if (RC == PPC::CRRCRegisterClass) { // FIXME: We use R0 here, because it isn't available for RA. - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), PPC::R0), + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R0), FrameIdx)); // If the reloaded register isn't CR0, shift the bits right so that they are @@ -548,11 +555,11 @@ PPCInstrInfo::LoadRegFromStackSlot(unsigned DestReg, int FrameIdx, if (DestReg != PPC::CR0) { unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; // rlwinm r11, r11, 32-ShiftBits, 0, 31. - NewMIs.push_back(BuildMI(get(PPC::RLWINM), PPC::R0) + NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0) .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31)); } - NewMIs.push_back(BuildMI(get(PPC::MTCRF), DestReg).addReg(PPC::R0)); + NewMIs.push_back(BuildMI(MF, get(PPC::MTCRF), DestReg).addReg(PPC::R0)); } else if (RC == PPC::CRBITRCRegisterClass) { unsigned Reg = 0; @@ -573,7 +580,7 @@ PPCInstrInfo::LoadRegFromStackSlot(unsigned DestReg, int FrameIdx, else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN) Reg = PPC::CR7; - return LoadRegFromStackSlot(Reg, FrameIdx, + return LoadRegFromStackSlot(MF, Reg, FrameIdx, PPC::CRRCRegisterClass, NewMIs); } else if (RC == PPC::VRRCRegisterClass) { @@ -582,9 +589,9 @@ PPCInstrInfo::LoadRegFromStackSlot(unsigned DestReg, int FrameIdx, // Dest = LVX 0, R0 // // FIXME: We use R0 here, because it isn't available for RA. - NewMIs.push_back(addFrameReference(BuildMI(get(PPC::ADDI), PPC::R0), + NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0), FrameIdx, 0, 0)); - NewMIs.push_back(BuildMI(get(PPC::LVX),DestReg).addReg(PPC::R0) + NewMIs.push_back(BuildMI(MF, get(PPC::LVX),DestReg).addReg(PPC::R0) .addReg(PPC::R0)); } else { assert(0 && "Unknown regclass!"); @@ -597,8 +604,9 @@ PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC) const { + MachineFunction &MF = *MBB.getParent(); SmallVector<MachineInstr*, 4> NewMIs; - LoadRegFromStackSlot(DestReg, FrameIdx, RC, NewMIs); + LoadRegFromStackSlot(MF, DestReg, FrameIdx, RC, NewMIs); for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) MBB.insert(MI, NewMIs[i]); } @@ -608,7 +616,7 @@ void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs)const{ if (Addr[0].isFrameIndex()) { - LoadRegFromStackSlot(DestReg, Addr[0].getIndex(), RC, NewMIs); + LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs); return; } @@ -629,7 +637,7 @@ void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isRegister()) @@ -662,13 +670,13 @@ MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF, if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(get(PPC::STW)) + NewMI = addFrameReference(BuildMI(MF, get(PPC::STW)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(get(PPC::LWZ)) + NewMI = addFrameReference(BuildMI(MF, get(PPC::LWZ)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } @@ -677,13 +685,13 @@ MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF, if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(get(PPC::STD)) + NewMI = addFrameReference(BuildMI(MF, get(PPC::STD)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(get(PPC::LD)) + NewMI = addFrameReference(BuildMI(MF, get(PPC::LD)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } @@ -691,13 +699,13 @@ MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF, if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(get(PPC::STFD)) + NewMI = addFrameReference(BuildMI(MF, get(PPC::STFD)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(get(PPC::LFD)) + NewMI = addFrameReference(BuildMI(MF, get(PPC::LFD)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } @@ -705,13 +713,13 @@ MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF, if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = addFrameReference(BuildMI(get(PPC::STFS)) + NewMI = addFrameReference(BuildMI(MF, get(PPC::STFS)) .addReg(InReg, false, false, isKill), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = addFrameReference(BuildMI(get(PPC::LFS)) + NewMI = addFrameReference(BuildMI(MF, get(PPC::LFS)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h index df36e9a..2337da6 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.h +++ b/lib/Target/PowerPC/PPCInstrInfo.h @@ -65,10 +65,12 @@ class PPCInstrInfo : public TargetInstrInfoImpl { PPCTargetMachine &TM; const PPCRegisterInfo RI; - bool StoreRegToStackSlot(unsigned SrcReg, bool isKill, int FrameIdx, + bool StoreRegToStackSlot(MachineFunction &MF, + unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const; - void LoadRegFromStackSlot(unsigned DestReg, int FrameIdx, + void LoadRegFromStackSlot(MachineFunction &MF, + unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const; public: diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 2f41813..342caf8 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -901,7 +901,7 @@ SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // to set, the condition code register to branch on, the true/false values to // select between, and a branch opcode to use. const BasicBlock *LLVM_BB = BB->getBasicBlock(); - ilist<MachineBasicBlock>::iterator It = BB; + MachineFunction::iterator It = BB; ++It; // thisMBB: @@ -910,12 +910,12 @@ SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // [f]bCC copy1MBB // fallthrough --> copy0MBB MachineBasicBlock *thisMBB = BB; - MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); - MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); - BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); MachineFunction *F = BB->getParent(); - F->getBasicBlockList().insert(It, copy0MBB); - F->getBasicBlockList().insert(It, sinkMBB); + MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); + BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); + F->insert(It, copy0MBB); + F->insert(It, sinkMBB); // Update machine-CFG edges by transferring all successors of the current // block to the new block which will contain the Phi node for the select. sinkMBB->transferSuccessors(BB); @@ -939,7 +939,7 @@ SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); - delete MI; // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index 67df87b..2476f4c 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -162,7 +162,7 @@ void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, Opc = SP::STDFri; else assert(0 && "Can't load this register"); - MachineInstrBuilder MIB = BuildMI(get(Opc)); + MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isRegister()) @@ -206,7 +206,7 @@ void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, Opc = SP::LDDFri; else assert(0 && "Can't load this register"); - MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) @@ -236,10 +236,10 @@ MachineInstr *SparcInstrInfo::foldMemoryOperand(MachineFunction &MF, if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&& MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) { if (OpNum == 0) // COPY -> STORE - NewMI = BuildMI(get(SP::STri)).addFrameIndex(FI).addImm(0) + NewMI = BuildMI(MF, get(SP::STri)).addFrameIndex(FI).addImm(0) .addReg(MI->getOperand(2).getReg()); else // COPY -> LOAD - NewMI = BuildMI(get(SP::LDri), MI->getOperand(0).getReg()) + NewMI = BuildMI(MF, get(SP::LDri), MI->getOperand(0).getReg()) .addFrameIndex(FI).addImm(0); } break; @@ -250,12 +250,12 @@ MachineInstr *SparcInstrInfo::foldMemoryOperand(MachineFunction &MF, if (OpNum == 0) { // COPY -> STORE unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(get(isFloat ? SP::STFri : SP::STDFri)) + NewMI = BuildMI(MF, get(isFloat ? SP::STFri : SP::STDFri)) .addFrameIndex(FI).addImm(0).addReg(SrcReg, false, false, isKill); } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(get(isFloat ? SP::LDFri : SP::LDDFri)) + NewMI = BuildMI(MF, get(isFloat ? SP::LDFri : SP::LDDFri)) .addReg(DstReg, true, false, false, isDead).addFrameIndex(FI).addImm(0); } break; diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index 3cda300..6525136 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -858,7 +858,7 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { assert(UpdatedSlot < StackTop && Dest < 7); Stack[UpdatedSlot] = Dest; RegMap[Dest] = UpdatedSlot; - delete MI; // Remove the old instruction + MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction } /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index c80c547..958f742 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -5955,16 +5955,16 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, // fallthrough -->nextMBB const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); const BasicBlock *LLVM_BB = MBB->getBasicBlock(); - ilist<MachineBasicBlock>::iterator MBBIter = MBB; + MachineFunction::iterator MBBIter = MBB; ++MBBIter; /// First build the CFG MachineFunction *F = MBB->getParent(); MachineBasicBlock *thisMBB = MBB; - MachineBasicBlock *newMBB = new MachineBasicBlock(LLVM_BB); - MachineBasicBlock *nextMBB = new MachineBasicBlock(LLVM_BB); - F->getBasicBlockList().insert(MBBIter, newMBB); - F->getBasicBlockList().insert(MBBIter, nextMBB); + MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(MBBIter, newMBB); + F->insert(MBBIter, nextMBB); // Move all successors to thisMBB to nextMBB nextMBB->transferSuccessors(thisMBB); @@ -6024,7 +6024,7 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, // insert branch BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB); - delete bInstr; // The pseudo instruction is gone now. + F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. return nextMBB; } @@ -6047,16 +6047,16 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, // const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); const BasicBlock *LLVM_BB = MBB->getBasicBlock(); - ilist<MachineBasicBlock>::iterator MBBIter = MBB; + MachineFunction::iterator MBBIter = MBB; ++MBBIter; /// First build the CFG MachineFunction *F = MBB->getParent(); MachineBasicBlock *thisMBB = MBB; - MachineBasicBlock *newMBB = new MachineBasicBlock(LLVM_BB); - MachineBasicBlock *nextMBB = new MachineBasicBlock(LLVM_BB); - F->getBasicBlockList().insert(MBBIter, newMBB); - F->getBasicBlockList().insert(MBBIter, nextMBB); + MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(MBBIter, newMBB); + F->insert(MBBIter, nextMBB); // Move all successors to thisMBB to nextMBB nextMBB->transferSuccessors(thisMBB); @@ -6121,7 +6121,7 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, // insert branch BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB); - delete mInstr; // The pseudo instruction is gone now. + F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now. return nextMBB; } @@ -6142,7 +6142,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // destination vreg to set, the condition code register to branch on, the // true/false values to select between, and a branch opcode to use. const BasicBlock *LLVM_BB = BB->getBasicBlock(); - ilist<MachineBasicBlock>::iterator It = BB; + MachineFunction::iterator It = BB; ++It; // thisMBB: @@ -6152,14 +6152,14 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // bCC copy1MBB // fallthrough --> copy0MBB MachineBasicBlock *thisMBB = BB; - MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); - MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); + MachineFunction *F = BB->getParent(); + MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); unsigned Opc = X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB); - MachineFunction *F = BB->getParent(); - F->getBasicBlockList().insert(It, copy0MBB); - F->getBasicBlockList().insert(It, sinkMBB); + F->insert(It, copy0MBB); + F->insert(It, sinkMBB); // Update machine-CFG edges by transferring all successors of the current // block to the new block which will contain the Phi node for the select. sinkMBB->transferSuccessors(BB); @@ -6184,7 +6184,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); - delete MI; // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } @@ -6261,7 +6261,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // Reload the original control word now. addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); - delete MI; // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } case X86::ATOMAND32: diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 76aa455..7822ed7 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -750,7 +750,7 @@ unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI, /// regIsPICBase - Return true if register is PIC base (i.e.g defined by /// X86::MOVPC32r. -static bool regIsPICBase(unsigned BaseReg, MachineRegisterInfo &MRI) { +static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { bool isPICBase = false; for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), E = MRI.def_end(); I != E; ++I) { @@ -799,7 +799,8 @@ X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const { // Allow re-materialization of PIC load. if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) return false; - MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); + const MachineFunction &MF = *MI->getParent()->getParent(); + const MachineRegisterInfo &MRI = MF.getRegInfo(); bool isPICBase = false; for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), E = MRI.def_end(); I != E; ++I) { @@ -825,7 +826,8 @@ X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const { if (BaseReg == 0) return true; // Allow re-materialization of lea PICBase + x. - MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); + const MachineFunction &MF = *MI->getParent()->getParent(); + const MachineRegisterInfo &MRI = MF.getRegInfo(); return regIsPICBase(BaseReg, MRI); } return false; @@ -909,7 +911,7 @@ void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, } if (!Emitted) { - MachineInstr *MI = Orig->clone(); + MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); MI->getOperand(0).setReg(DestReg); MBB.insert(I, MI); } @@ -985,6 +987,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { MachineInstr *MI = MBBI; + MachineFunction &MF = *MI->getParent()->getParent(); // All instructions input are two-addr instructions. Get the known operands. unsigned Dest = MI->getOperand(0).getReg(); unsigned Src = MI->getOperand(1).getReg(); @@ -1007,7 +1010,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, if (B != C) return 0; unsigned A = MI->getOperand(0).getReg(); unsigned M = MI->getOperand(3).getImm(); - NewMI = BuildMI(get(X86::PSHUFDri)).addReg(A, true, false, false, isDead) + NewMI = BuildMI(MF, get(X86::PSHUFDri)).addReg(A, true, false, false, isDead) .addReg(B, false, false, isKill).addImm(M); break; } @@ -1018,7 +1021,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, unsigned ShAmt = MI->getOperand(2).getImm(); if (ShAmt == 0 || ShAmt >= 4) return 0; - NewMI = BuildMI(get(X86::LEA64r)).addReg(Dest, true, false, false, isDead) + NewMI = BuildMI(MF, get(X86::LEA64r)).addReg(Dest, true, false, false, isDead) .addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0); break; } @@ -1031,7 +1034,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ? X86::LEA64_32r : X86::LEA32r; - NewMI = BuildMI(get(Opc)).addReg(Dest, true, false, false, isDead) + NewMI = BuildMI(MF, get(Opc)).addReg(Dest, true, false, false, isDead) .addReg(0).addImm(1 << ShAmt) .addReg(Src, false, false, isKill).addImm(0); break; @@ -1053,22 +1056,17 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, // Build and insert into an implicit UNDEF value. This is OK because // well be shifting and then extracting the lower 16-bits. - MachineInstr *Undef = BuildMI(get(X86::IMPLICIT_DEF), leaInReg); - MachineInstr *InsMI = BuildMI(get(X86::INSERT_SUBREG),leaInReg) + BuildMI(*MFI, MBBI, get(X86::IMPLICIT_DEF), leaInReg); + MachineInstr *InsMI = BuildMI(*MFI, MBBI, get(X86::INSERT_SUBREG),leaInReg) .addReg(leaInReg).addReg(Src, false, false, isKill) .addImm(X86::SUBREG_16BIT); - NewMI = BuildMI(get(Opc), leaOutReg).addReg(0).addImm(1 << ShAmt) + NewMI = BuildMI(*MFI, MBBI, get(Opc), leaOutReg).addReg(0).addImm(1 << ShAmt) .addReg(leaInReg, false, false, true).addImm(0); - MachineInstr *ExtMI = BuildMI(get(X86::EXTRACT_SUBREG)) + MachineInstr *ExtMI = BuildMI(*MFI, MBBI, get(X86::EXTRACT_SUBREG)) .addReg(Dest, true, false, false, isDead) .addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT); - - MFI->insert(MBBI, Undef); - MFI->insert(MBBI, InsMI); // Insert the insert_subreg - MFI->insert(MBBI, NewMI); // Insert the lea inst - MFI->insert(MBBI, ExtMI); // Insert the extract_subreg if (LV) { // Update live variables LV->getVarInfo(leaInReg).Kills.push_back(NewMI); @@ -1080,7 +1078,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, } return ExtMI; } else { - NewMI = BuildMI(get(X86::LEA16r)).addReg(Dest, true, false, false, isDead) + NewMI = BuildMI(MF, get(X86::LEA16r)).addReg(Dest, true, false, false, isDead) .addReg(0).addImm(1 << ShAmt) .addReg(Src, false, false, isKill).addImm(0); } @@ -1101,7 +1099,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r : (is64Bit ? X86::LEA64_32r : X86::LEA32r); - NewMI = addRegOffset(BuildMI(get(Opc)) + NewMI = addRegOffset(BuildMI(MF, get(Opc)) .addReg(Dest, true, false, false, isDead), Src, isKill, 1); break; @@ -1110,7 +1108,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, case X86::INC64_16r: if (DisableLEA16) return 0; assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); - NewMI = addRegOffset(BuildMI(get(X86::LEA16r)) + NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r)) .addReg(Dest, true, false, false, isDead), Src, isKill, 1); break; @@ -1119,7 +1117,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r : (is64Bit ? X86::LEA64_32r : X86::LEA32r); - NewMI = addRegOffset(BuildMI(get(Opc)) + NewMI = addRegOffset(BuildMI(MF, get(Opc)) .addReg(Dest, true, false, false, isDead), Src, isKill, -1); break; @@ -1128,7 +1126,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, case X86::DEC64_16r: if (DisableLEA16) return 0; assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); - NewMI = addRegOffset(BuildMI(get(X86::LEA16r)) + NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r)) .addReg(Dest, true, false, false, isDead), Src, isKill, -1); break; @@ -1139,7 +1137,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, : (is64Bit ? X86::LEA64_32r : X86::LEA32r); unsigned Src2 = MI->getOperand(2).getReg(); bool isKill2 = MI->getOperand(2).isKill(); - NewMI = addRegReg(BuildMI(get(Opc)) + NewMI = addRegReg(BuildMI(MF, get(Opc)) .addReg(Dest, true, false, false, isDead), Src, isKill, Src2, isKill2); if (LV && isKill2) @@ -1151,7 +1149,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); unsigned Src2 = MI->getOperand(2).getReg(); bool isKill2 = MI->getOperand(2).isKill(); - NewMI = addRegReg(BuildMI(get(X86::LEA16r)) + NewMI = addRegReg(BuildMI(MF, get(X86::LEA16r)) .addReg(Dest, true, false, false, isDead), Src, isKill, Src2, isKill2); if (LV && isKill2) @@ -1162,7 +1160,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, case X86::ADD64ri8: assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImmediate()) - NewMI = addRegOffset(BuildMI(get(X86::LEA64r)) + NewMI = addRegOffset(BuildMI(MF, get(X86::LEA64r)) .addReg(Dest, true, false, false, isDead), Src, isKill, MI->getOperand(2).getImm()); break; @@ -1171,7 +1169,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImmediate()) { unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; - NewMI = addRegOffset(BuildMI(get(Opc)) + NewMI = addRegOffset(BuildMI(MF, get(Opc)) .addReg(Dest, true, false, false, isDead), Src, isKill, MI->getOperand(2).getImm()); } @@ -1181,7 +1179,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, if (DisableLEA16) return 0; assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImmediate()) - NewMI = addRegOffset(BuildMI(get(X86::LEA16r)) + NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r)) .addReg(Dest, true, false, false, isDead), Src, isKill, MI->getOperand(2).getImm()); break; @@ -1199,7 +1197,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r : (MIOpc == X86::SHL32ri ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r); - NewMI = addFullAddress(BuildMI(get(Opc)) + NewMI = addFullAddress(BuildMI(MF, get(Opc)) .addReg(Dest, true, false, false, isDead), AM); if (isKill) NewMI->getOperand(3).setIsKill(true); @@ -1262,7 +1260,9 @@ X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { A = C; CisKill = false; } - return BuildMI(get(Opc)).addReg(A, true, false, false, AisDead) + MachineFunction &MF = *MI->getParent()->getParent(); + return BuildMI(MF, get(Opc)) + .addReg(A, true, false, false, AisDead) .addReg(C, false, false, CisKill) .addReg(B, false, false, BisKill).addImm(Size-Amt); } @@ -1750,7 +1750,7 @@ void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment()); - MachineInstrBuilder MIB = BuildMI(get(Opc)); + MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = X86InstrAddOperand(MIB, Addr[i]); MIB.addReg(SrcReg, false, false, isKill); @@ -1809,7 +1809,7 @@ void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment()); - MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = X86InstrAddOperand(MIB, Addr[i]); NewMIs.push_back(MIB); @@ -1854,11 +1854,11 @@ bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, return true; } -static MachineInstr *FuseTwoAddrInst(unsigned Opcode, +static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, SmallVector<MachineOperand,4> &MOs, MachineInstr *MI, const TargetInstrInfo &TII) { // Create the base instruction with the memory operand as the first part. - MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true); + MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true); MachineInstrBuilder MIB(NewMI); unsigned NumAddrOps = MOs.size(); for (unsigned i = 0; i != NumAddrOps; ++i) @@ -1879,10 +1879,11 @@ static MachineInstr *FuseTwoAddrInst(unsigned Opcode, return MIB; } -static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo, +static MachineInstr *FuseInst(MachineFunction &MF, + unsigned Opcode, unsigned OpNo, SmallVector<MachineOperand,4> &MOs, MachineInstr *MI, const TargetInstrInfo &TII) { - MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true); + MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true); MachineInstrBuilder MIB(NewMI); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { @@ -1904,7 +1905,8 @@ static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo, static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, SmallVector<MachineOperand,4> &MOs, MachineInstr *MI) { - MachineInstrBuilder MIB = BuildMI(TII.get(Opcode)); + MachineFunction &MF = *MI->getParent()->getParent(); + MachineInstrBuilder MIB = BuildMI(MF, TII.get(Opcode)); unsigned NumAddrOps = MOs.size(); for (unsigned i = 0; i != NumAddrOps; ++i) @@ -1915,7 +1917,8 @@ static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, } MachineInstr* -X86InstrInfo::foldMemoryOperand(MachineInstr *MI, unsigned i, +X86InstrInfo::foldMemoryOperand(MachineFunction &MF, + MachineInstr *MI, unsigned i, SmallVector<MachineOperand,4> &MOs) const { const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL; bool isTwoAddrFold = false; @@ -1959,9 +1962,9 @@ X86InstrInfo::foldMemoryOperand(MachineInstr *MI, unsigned i, OpcodeTablePtr->find((unsigned*)MI->getOpcode()); if (I != OpcodeTablePtr->end()) { if (isTwoAddrFold) - NewMI = FuseTwoAddrInst(I->second, MOs, MI, *this); + NewMI = FuseTwoAddrInst(MF, I->second, MOs, MI, *this); else - NewMI = FuseInst(I->second, i, MOs, MI, *this); + NewMI = FuseInst(MF, I->second, i, MOs, MI, *this); return NewMI; } } @@ -2017,7 +2020,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF, SmallVector<MachineOperand,4> MOs; MOs.push_back(MachineOperand::CreateFI(FrameIndex)); - return foldMemoryOperand(MI, Ops[0], MOs); + return foldMemoryOperand(MF, MI, Ops[0], MOs); } MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF, @@ -2028,8 +2031,9 @@ MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF, if (NoFusing) return NULL; unsigned Alignment = 0; - for (unsigned i = 0, e = LoadMI->getNumMemOperands(); i != e; ++i) { - const MachineMemOperand &MRO = LoadMI->getMemOperand(i); + for (alist<MachineMemOperand>::iterator i = LoadMI->memoperands_begin(), + e = LoadMI->memoperands_end(); i != e; ++i) { + const MachineMemOperand &MRO = *i; unsigned Align = MRO.getAlignment(); if (Align > Alignment) Alignment = Align; @@ -2072,7 +2076,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF, unsigned NumOps = LoadMI->getDesc().getNumOperands(); for (unsigned i = NumOps - 4; i != NumOps; ++i) MOs.push_back(LoadMI->getOperand(i)); - return foldMemoryOperand(MI, Ops[0], MOs); + return foldMemoryOperand(MF, MI, Ops[0], MOs); } @@ -2185,7 +2189,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, } // Emit the data processing instruction. - MachineInstr *DataMI = new MachineInstr(TID, true); + MachineInstr *DataMI = MF.CreateMachineInstr(TID, true); MachineInstrBuilder MIB(DataMI); if (FoldedStore) diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index b38b618..01b80a9 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -414,9 +414,10 @@ public: virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; private: - MachineInstr* foldMemoryOperand(MachineInstr* MI, - unsigned OpNum, - SmallVector<MachineOperand,4> &MOs) const; + MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, + unsigned OpNum, + SmallVector<MachineOperand,4> &MOs) const; }; } // End llvm namespace diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 691e35f..b652511 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -183,8 +183,8 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { return CalleeSavedRegs64Bit; } else { if (MF) { - MachineFrameInfo *MFI = MF->getFrameInfo(); - MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + const MachineFrameInfo *MFI = MF->getFrameInfo(); + const MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); if (MMI && MMI->callsEHReturn()) return CalleeSavedRegs32EHRet; } @@ -222,8 +222,8 @@ X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { return CalleeSavedRegClasses64Bit; } else { if (MF) { - MachineFrameInfo *MFI = MF->getFrameInfo(); - MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + const MachineFrameInfo *MFI = MF->getFrameInfo(); + const MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); if (MMI && MMI->callsEHReturn()) return CalleeSavedRegClasses32EHRet; } @@ -269,8 +269,8 @@ static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) { // if frame pointer elimination is disabled. // bool X86RegisterInfo::hasFP(const MachineFunction &MF) const { - MachineFrameInfo *MFI = MF.getFrameInfo(); - MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + const MachineFrameInfo *MFI = MF.getFrameInfo(); + const MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); return (NoFramePointerElim || needsStackRealignment(MF) || @@ -280,7 +280,7 @@ bool X86RegisterInfo::hasFP(const MachineFunction &MF) const { } bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const { - MachineFrameInfo *MFI = MF.getFrameInfo();; + const MachineFrameInfo *MFI = MF.getFrameInfo();; // FIXME: Currently we don't support stack realignment for functions with // variable-sized allocas @@ -343,7 +343,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineInstr *New = 0; if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) { - New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr) + New=BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr) .addReg(StackPtr).addImm(Amount); } else { assert(Old->getOpcode() == X86::ADJCALLSTACKUP); @@ -354,7 +354,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, unsigned Opc = (Amount < 128) ? (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri); - New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount); + New = BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount); } } @@ -370,7 +370,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri); MachineInstr *New = - BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt); + BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt); MBB.insert(I, New); } } @@ -749,7 +749,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)) .addExternalSymbol("_alloca"); // Restore EAX - MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX), + MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(X86::MOV32rm),X86::EAX), StackPtr, false, NumBytes-4); MBB.insert(MBBI, MI); } @@ -845,7 +845,7 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF, } else if (MFI->hasVarSizedObjects()) { if (CSSize) { unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r; - MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr), + MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(Opc), StackPtr), FramePtr, false, -CSSize); MBB.insert(MBBI, MI); } else |