diff options
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 20 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.h | 5 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.cpp | 35 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.h | 5 |
4 files changed, 0 insertions, 65 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 0b5b243..aca292a 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1925,23 +1925,3 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, return getOperandLatency(ItinData, DefTID, DefIdx, DefAlign, UseTID, UseIdx, UseAlign); } - -bool ARMBaseInstrInfo:: -hasHighOperandLatency(const InstrItineraryData *ItinData, - const MachineRegisterInfo *MRI, - const MachineInstr *DefMI, unsigned DefIdx, - const MachineInstr *UseMI, unsigned UseIdx) const { - unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; - unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; - if (Subtarget.isCortexA8() && - (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) - // CortexA8 VFP instructions are not pipelined. - return true; - - // Hoist VFP / NEON instructions with 4 or higher latency. - int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); - if (Latency <= 3) - return false; - return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || - UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; -} diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h index b3a8329..36be336 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/lib/Target/ARM/ARMBaseInstrInfo.h @@ -377,11 +377,6 @@ private: unsigned DefIdx, unsigned DefAlign, const TargetInstrDesc &UseTID, unsigned UseIdx, unsigned UseAlign) const; - - bool hasHighOperandLatency(const InstrItineraryData *ItinData, - const MachineRegisterInfo *MRI, - const MachineInstr *DefMI, unsigned DefIdx, - const MachineInstr *UseMI, unsigned UseIdx) const; }; static inline diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 79d9872..40ef3db 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -3152,41 +3152,6 @@ void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { NopInst.setOpcode(X86::NOOP); } -bool X86InstrInfo:: -hasHighOperandLatency(const InstrItineraryData *ItinData, - const MachineRegisterInfo *MRI, - const MachineInstr *DefMI, unsigned DefIdx, - const MachineInstr *UseMI, unsigned UseIdx) const { - switch (DefMI->getOpcode()) { - default: return false; - case X86::DIVSDrm: - case X86::DIVSDrm_Int: - case X86::DIVSDrr: - case X86::DIVSDrr_Int: - case X86::DIVSSrm: - case X86::DIVSSrm_Int: - case X86::DIVSSrr: - case X86::DIVSSrr_Int: - case X86::SQRTPDm: - case X86::SQRTPDm_Int: - case X86::SQRTPDr: - case X86::SQRTPDr_Int: - case X86::SQRTPSm: - case X86::SQRTPSm_Int: - case X86::SQRTPSr: - case X86::SQRTPSr_Int: - case X86::SQRTSDm: - case X86::SQRTSDm_Int: - case X86::SQRTSDr: - case X86::SQRTSDr_Int: - case X86::SQRTSSm: - case X86::SQRTSSm_Int: - case X86::SQRTSSr: - case X86::SQRTSSr_Int: - return true; - } -} - namespace { /// CGBR - Create Global Base Reg pass. This initializes the PIC /// global base register for x86-32. diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index 5060ad8..e43cfac 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -864,11 +864,6 @@ public: unsigned OpNum, const SmallVectorImpl<MachineOperand> &MOs, unsigned Size, unsigned Alignment) const; - - bool hasHighOperandLatency(const InstrItineraryData *ItinData, - const MachineRegisterInfo *MRI, - const MachineInstr *DefMI, unsigned DefIdx, - const MachineInstr *UseMI, unsigned UseIdx) const; private: MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, |