diff options
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 5 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrVFP.td | 2 |
3 files changed, 3 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 73ad6c8..04b497e 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -713,7 +713,7 @@ def PICLDSB : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr", [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; } -let isStore = 1, AddedComplexity = 10 in { +let AddedComplexity = 10 in { def PICSTR : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), Pseudo, "${addr:label}:\n\tstr$p $src, $addr", [(store GPR:$src, addrmodepc:$addr)]>; @@ -878,7 +878,6 @@ def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb), } // isLoad // Store -let isStore = 1 in { def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm, "str", " $src, $addr", [(store GPR:$src, addrmode2:$addr)]>; @@ -893,6 +892,7 @@ def STRB : AI2<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm, [(truncstorei8 GPR:$src, addrmode2:$addr)]>; // Store doubleword +let isStore = 1 in def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm, "str", "d $src, $addr", []>, Requires<[IsARM, HasV5T]>; @@ -933,7 +933,6 @@ def STRB_POST: AI2po<0x1, (outs GPR:$base_wb), "str", "b $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_truncsti8 GPR:$src, GPR:$base, am2offset:$offset))]>; -} // isStore //===----------------------------------------------------------------------===// // Load / store multiple Instructions. diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 83d448b..4611a3e 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -278,7 +278,6 @@ def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr), "ldr $dst, $addr", []>; } // isLoad -let isStore = 1 in { def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr), "str $src, $addr", [(store GPR:$src, t_addrmode_s4:$addr)]>; @@ -295,6 +294,7 @@ def tSTRspi : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr), "str $src, $addr", [(store GPR:$src, t_addrmode_sp:$addr)]>; +let isStore = 1 in { // Special instruction for spill. It cannot clobber condition register // when it's expanded by eliminateCallFramePseudoInstr(). def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr), diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index 1796e77..d0ae52f 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -98,7 +98,6 @@ def FLDS : ASI5<(outs SPR:$dst), (ins addrmode5:$addr), [(set SPR:$dst, (load addrmode5:$addr))]>; } // isLoad -let isStore = 1 in { def FSTD : ADI5<(outs), (ins DPR:$src, addrmode5:$addr), "fstd", " $src, $addr", [(store DPR:$src, addrmode5:$addr)]>; @@ -106,7 +105,6 @@ def FSTD : ADI5<(outs), (ins DPR:$src, addrmode5:$addr), def FSTS : ASI5<(outs), (ins SPR:$src, addrmode5:$addr), "fsts", " $src, $addr", [(store SPR:$src, addrmode5:$addr)]>; -} // isStore //===----------------------------------------------------------------------===// // Load / store multiple Instructions. |