diff options
Diffstat (limited to 'lib/Target')
25 files changed, 1325 insertions, 58 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index 568ca85..96eb764 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -88,9 +88,11 @@ namespace { void emitWordLE(unsigned Binary); void emitDWordLE(uint64_t Binary); + void emitConstantToMemory(unsigned CPI, const Constant *CV); void emitConstPoolInstruction(const MachineInstr &MI); void emitMOVi32immInstruction(const MachineInstr &MI); void emitMOVi2piecesInstruction(const MachineInstr &MI); + void emitLEApcrelInstruction(const MachineInstr &MI); void emitLEApcrelJTInstruction(const MachineInstr &MI); void emitPseudoMoveInstruction(const MachineInstr &MI); void addPCLabel(unsigned LabelID); @@ -139,6 +141,8 @@ namespace { void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); + void emitMiscInstruction(const MachineInstr &MI); + void emitNEONLaneInstruction(const MachineInstr &MI); void emitNEONDupInstruction(const MachineInstr &MI); void emitNEON1RegModImmInstruction(const MachineInstr &MI); @@ -170,7 +174,13 @@ namespace { unsigned NEONThumb2V8PostEncoder(const MachineInstr &MI,unsigned Val) const { return 0; } unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val) - const { return 0; } + const { + if (IsThumb) { + Val &= 0x0FFFFFFF; + Val |= 0xE0000000; + } + return Val; + } unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op) @@ -266,8 +276,20 @@ namespace { return Binary; } - unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const { - return 0; + unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) + const { + const MCInstrDesc &MCID = MI.getDesc(); + const MachineOperand &MO = MI.getOperand(Op); + + unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ? + ARM::reloc_arm_movw : ARM::reloc_arm_movt); + + if (!MO.isImm()) { + emitGlobalAddress(MO.getGlobal(), Reloc, true, false); + return 0; + } + unsigned Imm16 = static_cast<unsigned>(MO.getImm()); + return Imm16; } uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) @@ -289,9 +311,10 @@ namespace { uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { - // {17-13} = reg - // {12} = (U)nsigned (add == '1', sub == '0') - // {11-0} = imm12 + // {12-9} = reg + // {8} = (U)nsigned (add == '1', sub == '0') + // {7-0} = imm8 + uint32_t Binary = 0; const MachineOperand &MO = MI.getOperand(Op); const MachineOperand &MO1 = MI.getOperand(Op + 1); if (!MO.isReg()) { @@ -313,10 +336,8 @@ namespace { isAdd = false; } - uint32_t Binary = Imm12 & 0xfff; - if (isAdd) - Binary |= (1 << 12); - Binary |= (Reg << 13); + // If immediate offset is omitted, default to +0. + Binary |= 1 << 8; return Binary; } unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) @@ -455,6 +476,9 @@ unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, return II->getRegisterInfo().getEncodingValue(MO.getReg()); else if (MO.isImm()) return static_cast<unsigned>(MO.getImm()); + else if (MO.isFPImm()) + return static_cast<unsigned>(MO.getFPImm()->getValueAPF() + .bitcastToAPInt().getHiBits(32).getLimitedValue()); else if (MO.isGlobal()) emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false); else if (MO.isSymbol()) @@ -607,7 +631,9 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { case ARMII::VFPLdStMulFrm: emitVFPLoadStoreMultipleInstruction(MI); break; - + case ARMII::VFPMiscFrm: + emitMiscInstruction(MI); + break; // NEON instructions. case ARMII::NGetLnFrm: case ARMII::NSetLnFrm: @@ -629,6 +655,56 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { MCE.processDebugLoc(MI.getDebugLoc(), false); } +void ARMCodeEmitter::emitConstantToMemory(unsigned CPI, const Constant *C) { + DEBUG({ + errs() << " ** Constant pool #" << CPI << " @ " + << (void*)MCE.getCurrentPCValue() << " "; + if (const Function *F = dyn_cast<Function>(C)) + errs() << F->getName(); + else + errs() << *C; + errs() << '\n'; + }); + + switch (C->getValueID()) { + default: { + llvm_unreachable("Unable to handle this constantpool entry!"); + break; + } + case Value::GlobalVariableVal: { + emitGlobalAddress(static_cast<const GlobalValue*>(C), + ARM::reloc_arm_absolute, isa<Function>(C), false); + emitWordLE(0); + break; + } + case Value::ConstantIntVal: { + const ConstantInt *CI = static_cast<const ConstantInt*>(C); + uint32_t Val = *(uint32_t*)CI->getValue().getRawData(); + emitWordLE(Val); + break; + } + case Value::ConstantFPVal: { + const ConstantFP *CFP = static_cast<const ConstantFP*>(C); + if (CFP->getType()->isFloatTy()) + emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); + else if (CFP->getType()->isDoubleTy()) + emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); + else { + llvm_unreachable("Unable to handle this constantpool entry!"); + } + break; + } + case Value::ConstantArrayVal: { + const ConstantArray *CA = static_cast<const ConstantArray*>(C); + for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i) + emitConstantToMemory(CPI, CA->getOperand(i)); + break; + } + } + + return; +} + void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. @@ -660,35 +736,7 @@ void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { } emitWordLE(0); } else { - const Constant *CV = MCPE.Val.ConstVal; - - DEBUG({ - errs() << " ** Constant pool #" << CPI << " @ " - << (void*)MCE.getCurrentPCValue() << " "; - if (const Function *F = dyn_cast<Function>(CV)) - errs() << F->getName(); - else - errs() << *CV; - errs() << '\n'; - }); - - if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) { - emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false); - emitWordLE(0); - } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) { - uint32_t Val = uint32_t(*CI->getValue().getRawData()); - emitWordLE(Val); - } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) { - if (CFP->getType()->isFloatTy()) - emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); - else if (CFP->getType()->isDoubleTy()) - emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); - else { - llvm_unreachable("Unable to handle this constantpool entry!"); - } - } else { - llvm_unreachable("Unable to handle this constantpool entry!"); - } + emitConstantToMemory(CPI, MCPE.Val.ConstVal); } } @@ -770,6 +818,32 @@ void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { emitWordLE(Binary); } +void ARMCodeEmitter::emitLEApcrelInstruction(const MachineInstr &MI) { + // It's basically add r, pc, (LCPI - $+8) + const MCInstrDesc &MCID = MI.getDesc(); + + unsigned Binary = 0; + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + // Encode S bit if MI modifies CPSR. + Binary |= getAddrModeSBit(MI, MCID); + + // Encode Rd. + Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; + + // Encode Rn which is PC. + Binary |= II->getRegisterInfo().getEncodingValue(ARM::PC) << ARMII::RegRnShift; + + // Encode the displacement which is a so_imm. + // Set bit I(25) to identify this is the immediate form of <shifter_op> + Binary |= 1 << ARMII::I_BitShift; + emitConstPoolAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_so_imm_cp_entry); + + emitWordLE(Binary); +} + void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { // It's basically add r, pc, (LJTI - $+8) @@ -847,6 +921,14 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { switch (Opcode) { default: llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); + case ARM::B: + emitBranchInstruction(MI); + break; + case ARM::BR_JTr: + case ARM::BR_JTm: + case ARM::BR_JTadd: + emitMiscBranchInstruction(MI); + break; case ARM::BX_CALL: case ARM::BMOVPCRX_CALL: { // First emit mov lr, pc @@ -877,6 +959,9 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { case ARM::CONSTPOOL_ENTRY: emitConstPoolInstruction(MI); break; + case ARM::LDMIA_RET: + emitLoadStoreMultipleInstruction(MI); + break; case ARM::PICADD: { // Remember of the address of the PC label for relocation later. addPCLabel(MI.getOperand(2).getImm()); @@ -912,7 +997,10 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { else emitMOVi2piecesInstruction(MI); break; - + case ARM::LEApcrel: + // Materialize constantpool index address. + emitLEApcrelInstruction(MI); + break; case ARM::LEApcrelJT: // Materialize jumptable address. emitLEApcrelJTInstruction(MI); @@ -1013,6 +1101,11 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); + if (MCID.Opcode == ARM::MOVi16 || MCID.Opcode == ARM::MOVTi16) { + emitWordLE(Binary); + return; + } + // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift; @@ -1115,11 +1208,17 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done. if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp || - MI.getOpcode() == ARM::STRi12) { + MI.getOpcode() == ARM::STRi12 || MI.getOpcode() == ARM::LDRBi12 || + MI.getOpcode() == ARM::STRBi12) { emitWordLE(Binary); return; } + if (MI.getOpcode() == ARM::BR_JTm) + Binary = 0x710F000; + else if (MI.getOpcode() == ARM::BR_JTr) + Binary = 0x1A0F000; + // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift; @@ -1275,6 +1374,11 @@ void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); + if (MCID.getOpcode() == ARM::LDMIA_RET) { + IsUpdating = true; + Binary |= 0x8B00000; + } + // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift; @@ -1482,6 +1586,10 @@ void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); + if (MCID.Opcode == ARM::B) { + Binary = 0xEA000000; + } + // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift; @@ -1556,9 +1664,10 @@ unsigned ARMCodeEmitter::encodeVFPRd(const MachineInstr &MI, unsigned Binary = 0; bool isSPVFP = ARM::SPRRegClass.contains(RegD); RegD = II->getRegisterInfo().getEncodingValue(RegD); - if (!isSPVFP) - Binary |= RegD << ARMII::RegRdShift; - else { + if (!isSPVFP) { + Binary |= (RegD & 0x0F) << ARMII::RegRdShift; + Binary |= ((RegD & 0x10) >> 4) << ARMII::D_BitShift; + } else { Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; Binary |= (RegD & 0x01) << ARMII::D_BitShift; } @@ -1571,9 +1680,10 @@ unsigned ARMCodeEmitter::encodeVFPRn(const MachineInstr &MI, unsigned Binary = 0; bool isSPVFP = ARM::SPRRegClass.contains(RegN); RegN = II->getRegisterInfo().getEncodingValue(RegN); - if (!isSPVFP) - Binary |= RegN << ARMII::RegRnShift; - else { + if (!isSPVFP) { + Binary |= (RegN & 0x0F) << ARMII::RegRnShift; + Binary |= ((RegN & 0x10) >> 4) << ARMII::N_BitShift; + } else { Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; Binary |= (RegN & 0x01) << ARMII::N_BitShift; } @@ -1586,9 +1696,10 @@ unsigned ARMCodeEmitter::encodeVFPRm(const MachineInstr &MI, unsigned Binary = 0; bool isSPVFP = ARM::SPRRegClass.contains(RegM); RegM = II->getRegisterInfo().getEncodingValue(RegM); - if (!isSPVFP) - Binary |= RegM; - else { + if (!isSPVFP) { + Binary |= (RegM & 0x0F); + Binary |= ((RegM & 0x10) >> 4) << ARMII::M_BitShift; + } else { Binary |= ((RegM & 0x1E) >> 1); Binary |= (RegM & 0x01) << ARMII::M_BitShift; } @@ -1605,9 +1716,6 @@ void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { Binary |= II->getPredicate(&MI) << ARMII::CondShift; unsigned OpIdx = 0; - assert((Binary & ARMII::D_BitShift) == 0 && - (Binary & ARMII::N_BitShift) == 0 && - (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); // Encode Dd / Sd. Binary |= encodeVFPRd(MI, OpIdx++); @@ -1697,6 +1805,12 @@ void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift; + if (MI.getOpcode() == ARM::VLDRS || MI.getOpcode() == ARM::VLDRD || + MI.getOpcode() == ARM::VSTRS || MI.getOpcode() == ARM::VSTRD){ + emitWordLE(Binary); + return; + } + unsigned OpIdx = 0; // Encode Dd / Sd. @@ -1772,6 +1886,26 @@ ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { emitWordLE(Binary); } +void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) { + unsigned Opcode = MI.getDesc().Opcode; + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + if (Opcode == ARM::FCONSTS) { + unsigned Imm = getMachineOpValue(MI, 1); + Binary &= ~(0x780000 >> 19); + Binary |= (Imm & 0x780000) >> 19; + Binary &= ~(0x3800000 >> 7); + Binary |= (Imm & 0x3800000) >> 7; + Binary = VFPThumb2PostEncoder(MI, Binary); + } + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + emitWordLE(Binary); +} + unsigned ARMCodeEmitter::encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) const { unsigned RegD = MI.getOperand(OpIdx).getReg(); diff --git a/lib/Target/ARM/ARMRelocations.h b/lib/Target/ARM/ARMRelocations.h index 21877fd..9c32b15 100644 --- a/lib/Target/ARM/ARMRelocations.h +++ b/lib/Target/ARM/ARMRelocations.h @@ -35,6 +35,10 @@ namespace llvm { // should be divided by 4. reloc_arm_vfp_cp_entry, + // reloc_arm_so_imm - Same as reloc_arm_cp_entry except contant should be + // encoded as so_imm value. + reloc_arm_so_imm_cp_entry, + // reloc_arm_machine_cp_entry - Relocation of a ARM machine constantpool // entry. reloc_arm_machine_cp_entry, diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index c592421..0a0f30c 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -27,7 +27,7 @@ using namespace llvm; -static cl::opt<bool> +cl::opt<bool> ReserveR9("arm-reserve-r9", cl::Hidden, cl::desc("Reserve R9, making it unavailable as GPR")); diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 1ba78e4..e6dbcb6 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -23,7 +23,7 @@ #include "llvm/Transforms/Scalar.h" using namespace llvm; -static cl::opt<bool> +cl::opt<bool> EnableGlobalMerge("global-merge", cl::Hidden, cl::desc("Enable global merge pass"), cl::init(true)); diff --git a/lib/Target/ARM/Android.mk b/lib/Target/ARM/Android.mk new file mode 100644 index 0000000..25b0d89 --- /dev/null +++ b/lib/Target/ARM/Android.mk @@ -0,0 +1,85 @@ +LOCAL_PATH := $(call my-dir) + +arm_codegen_TBLGEN_TABLES := \ + ARMGenRegisterInfo.inc \ + ARMGenInstrInfo.inc \ + ARMGenCodeEmitter.inc \ + ARMGenMCCodeEmitter.inc \ + ARMGenMCPseudoLowering.inc \ + ARMGenAsmWriter.inc \ + ARMGenAsmMatcher.inc \ + ARMGenDAGISel.inc \ + ARMGenFastISel.inc \ + ARMGenCallingConv.inc \ + ARMGenSubtargetInfo.inc \ + ARMGenDisassemblerTables.inc + +arm_codegen_SRC_FILES := \ + A15SDOptimizer.cpp \ + ARMAsmPrinter.cpp \ + ARMBaseInstrInfo.cpp \ + ARMBaseRegisterInfo.cpp \ + ARMCodeEmitter.cpp \ + ARMConstantIslandPass.cpp \ + ARMConstantPoolValue.cpp \ + ARMExpandPseudoInsts.cpp \ + ARMFastISel.cpp \ + ARMFrameLowering.cpp \ + ARMHazardRecognizer.cpp \ + ARMISelDAGToDAG.cpp \ + ARMISelLowering.cpp \ + ARMInstrInfo.cpp \ + ARMJITInfo.cpp \ + ARMLoadStoreOptimizer.cpp \ + ARMMCInstLower.cpp \ + ARMMachineFunctionInfo.cpp \ + ARMRegisterInfo.cpp \ + ARMSelectionDAGInfo.cpp \ + ARMSubtarget.cpp \ + ARMTargetMachine.cpp \ + ARMTargetObjectFile.cpp \ + ARMTargetTransformInfo.cpp \ + MLxExpansionPass.cpp \ + Thumb1FrameLowering.cpp \ + Thumb1InstrInfo.cpp \ + Thumb1RegisterInfo.cpp \ + Thumb2ITBlockPass.cpp \ + Thumb2InstrInfo.cpp \ + Thumb2RegisterInfo.cpp \ + Thumb2SizeReduction.cpp + +# For the host +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMARMCodeGen +LOCAL_MODULE_TAGS := optional + +LOCAL_SRC_FILES := $(arm_codegen_SRC_FILES) +LOCAL_C_INCLUDES := $(LOCAL_PATH)/MCTargetDesc +TBLGEN_TABLES := $(arm_codegen_TBLGEN_TABLES) + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(LLVM_GEN_INTRINSICS_MK) +include $(BUILD_HOST_STATIC_LIBRARY) + +# For the device only +# ===================================================== +ifeq ($(TARGET_ARCH),arm) +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMARMCodeGen +LOCAL_MODULE_TAGS := optional + +LOCAL_SRC_FILES := $(arm_codegen_SRC_FILES) +LOCAL_C_INCLUDES := $(LOCAL_PATH)/MCTargetDesc +TBLGEN_TABLES := $(arm_codegen_TBLGEN_TABLES) + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(LLVM_GEN_INTRINSICS_MK) +include $(BUILD_STATIC_LIBRARY) +endif diff --git a/lib/Target/ARM/AsmParser/Android.mk b/lib/Target/ARM/AsmParser/Android.mk new file mode 100644 index 0000000..e17a274 --- /dev/null +++ b/lib/Target/ARM/AsmParser/Android.mk @@ -0,0 +1,61 @@ +LOCAL_PATH := $(call my-dir) + +#===---------------------------------------------------------------=== +# libARMAsmParser (common) +#===---------------------------------------------------------------=== + +arm_asm_parser_SRC_FILES := \ + ARMAsmParser.cpp + +arm_asm_parser_TBLGEN_TABLES := \ + ARMGenInstrInfo.inc \ + ARMGenRegisterInfo.inc \ + ARMGenAsmMatcher.inc \ + ARMGenSubtargetInfo.inc + +arm_asm_parser_TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +arm_asm_parser_C_INCLUDES := $(LOCAL_PATH)/.. + + +#===---------------------------------------------------------------=== +# libARMAsmParser (host) +#===---------------------------------------------------------------=== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMARMAsmParser +LOCAL_MODULE_TAGS := optional +LOCAL_SRC_FILES := $(arm_asm_parser_SRC_FILES) +LOCAL_C_INCLUDES += $(arm_asm_parser_C_INCLUDES) +TBLGEN_TABLES := $(arm_asm_parser_TBLGEN_TABLES) +TBLGEN_TD_DIR := $(arm_asm_parser_TBLGEN_TD_DIR) + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +ifneq (,$(filter windows darwin,$(HOST_OS))) +# Override the default optimization level to work around taking forever (~50m) +# to compile ARMAsmParser.cpp on Mac with gcc 4.2, +# or on Linux with mingw32msvc-gcc 4.2, which is used to cross-compile +# the win_sdk. +LOCAL_CFLAGS += -O0 +endif +include $(BUILD_HOST_STATIC_LIBRARY) + + +#===---------------------------------------------------------------=== +# libARMAsmParser (target) +#===---------------------------------------------------------------=== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMARMAsmParser +LOCAL_MODULE_TAGS := optional +LOCAL_SRC_FILES := $(arm_asm_parser_SRC_FILES) +LOCAL_C_INCLUDES += $(arm_asm_parser_C_INCLUDES) +TBLGEN_TABLES := $(arm_asm_parser_TBLGEN_TABLES) +TBLGEN_TD_DIR := $(arm_asm_parser_TBLGEN_TD_DIR) + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_STATIC_LIBRARY) diff --git a/lib/Target/ARM/Disassembler/Android.mk b/lib/Target/ARM/Disassembler/Android.mk new file mode 100644 index 0000000..51e364b --- /dev/null +++ b/lib/Target/ARM/Disassembler/Android.mk @@ -0,0 +1,55 @@ +LOCAL_PATH := $(call my-dir) + +arm_disassembler_TBLGEN_TABLES := \ + ARMGenDisassemblerTables.inc \ + ARMGenInstrInfo.inc \ + ARMGenSubtargetInfo.inc \ + ARMGenRegisterInfo.inc + +arm_disassembler_SRC_FILES := \ + ARMDisassembler.cpp + +# For the device +# ===================================================== +ifeq ($(TARGET_ARCH),arm) +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +TBLGEN_TABLES := $(arm_disassembler_TBLGEN_TABLES) + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(arm_disassembler_SRC_FILES) + +LOCAL_C_INCLUDES += $(LOCAL_PATH)/.. + +LOCAL_MODULE:= libLLVMARMDisassembler + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_STATIC_LIBRARY) +endif + +# For the host +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +TBLGEN_TABLES := $(arm_disassembler_TBLGEN_TABLES) + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(arm_disassembler_SRC_FILES) + +LOCAL_C_INCLUDES += $(LOCAL_PATH)/.. + +LOCAL_MODULE:= libLLVMARMDisassembler + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_HOST_STATIC_LIBRARY) + diff --git a/lib/Target/ARM/InstPrinter/Android.mk b/lib/Target/ARM/InstPrinter/Android.mk new file mode 100644 index 0000000..a047f6f --- /dev/null +++ b/lib/Target/ARM/InstPrinter/Android.mk @@ -0,0 +1,55 @@ +LOCAL_PATH := $(call my-dir) + +arm_asm_printer_TBLGEN_TABLES := \ + ARMGenAsmWriter.inc \ + ARMGenRegisterInfo.inc \ + ARMGenSubtargetInfo.inc \ + ARMGenInstrInfo.inc + +arm_asm_printer_SRC_FILES := \ + ARMInstPrinter.cpp + +# For the host +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +TBLGEN_TABLES := $(arm_asm_printer_TBLGEN_TABLES) + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(arm_asm_printer_SRC_FILES) + +LOCAL_MODULE:= libLLVMARMAsmPrinter + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/.. + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_HOST_STATIC_LIBRARY) + +# For the device only +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +TBLGEN_TABLES := $(arm_asm_printer_TBLGEN_TABLES) + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(arm_asm_printer_SRC_FILES) + +LOCAL_C_INCLUDES+= \ + $(LOCAL_PATH)/.. + +LOCAL_MODULE:= libLLVMARMAsmPrinter + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_STATIC_LIBRARY) + diff --git a/lib/Target/ARM/MCTargetDesc/Android.mk b/lib/Target/ARM/MCTargetDesc/Android.mk new file mode 100644 index 0000000..af22753 --- /dev/null +++ b/lib/Target/ARM/MCTargetDesc/Android.mk @@ -0,0 +1,60 @@ +LOCAL_PATH := $(call my-dir) + +arm_mc_desc_TBLGEN_TABLES := \ + ARMGenRegisterInfo.inc \ + ARMGenInstrInfo.inc \ + ARMGenMCCodeEmitter.inc \ + ARMGenSubtargetInfo.inc + +arm_mc_desc_SRC_FILES := \ + ARMAsmBackend.cpp \ + ARMELFObjectWriter.cpp \ + ARMELFStreamer.cpp \ + ARMMCAsmInfo.cpp \ + ARMMCCodeEmitter.cpp \ + ARMMCExpr.cpp \ + ARMMCTargetDesc.cpp \ + ARMMachObjectWriter.cpp \ + ARMMachORelocationInfo.cpp \ + ARMUnwindOpAsm.cpp + +# For the host +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + + +LOCAL_MODULE:= libLLVMARMDesc +LOCAL_MODULE_TAGS := optional + +LOCAL_SRC_FILES := $(arm_mc_desc_SRC_FILES) +LOCAL_C_INCLUDES := $(LOCAL_PATH)/.. + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. +TBLGEN_TABLES := $(arm_mc_desc_TBLGEN_TABLES) + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(LLVM_GEN_INTRINSICS_MK) +include $(BUILD_HOST_STATIC_LIBRARY) + +# For the device only +# ===================================================== +ifeq ($(TARGET_ARCH),arm) +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMARMDesc +LOCAL_MODULE_TAGS := optional + +LOCAL_SRC_FILES := $(arm_mc_desc_SRC_FILES) +LOCAL_C_INCLUDES := $(LOCAL_PATH)/.. + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. +TBLGEN_TABLES := $(arm_mc_desc_TBLGEN_TABLES) + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(LLVM_GEN_INTRINSICS_MK) +include $(BUILD_STATIC_LIBRARY) +endif diff --git a/lib/Target/ARM/TargetInfo/Android.mk b/lib/Target/ARM/TargetInfo/Android.mk new file mode 100644 index 0000000..d1af6ae --- /dev/null +++ b/lib/Target/ARM/TargetInfo/Android.mk @@ -0,0 +1,55 @@ +LOCAL_PATH := $(call my-dir) + +arm_target_info_TBLGEN_TABLES := \ + ARMGenSubtargetInfo.inc \ + ARMGenRegisterInfo.inc \ + ARMGenInstrInfo.inc + +arm_target_info_SRC_FILES := \ + ARMTargetInfo.cpp + +# For the host +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +TBLGEN_TABLES := $(arm_target_info_TBLGEN_TABLES) + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(arm_target_info_SRC_FILES) + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/.. + +LOCAL_MODULE:= libLLVMARMInfo + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_HOST_STATIC_LIBRARY) + +# For the device +# ===================================================== +ifeq ($(TARGET_ARCH),arm) +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +TBLGEN_TABLES := $(arm_target_info_TBLGEN_TABLES) + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(arm_target_info_SRC_FILES) + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/.. + +LOCAL_MODULE:= libLLVMARMInfo + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_STATIC_LIBRARY) +endif diff --git a/lib/Target/Android.mk b/lib/Target/Android.mk new file mode 100644 index 0000000..60f5b18 --- /dev/null +++ b/lib/Target/Android.mk @@ -0,0 +1,38 @@ +LOCAL_PATH:= $(call my-dir) + +target_SRC_FILES := \ + Mangler.cpp \ + Target.cpp \ + TargetIntrinsicInfo.cpp \ + TargetJITInfo.cpp \ + TargetLibraryInfo.cpp \ + TargetLoweringObjectFile.cpp \ + TargetMachineC.cpp \ + TargetMachine.cpp \ + TargetSubtargetInfo.cpp + +# For the host +# ===================================================== +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := $(target_SRC_FILES) + +LOCAL_MODULE:= libLLVMTarget + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_HOST_BUILD_MK) +include $(BUILD_HOST_STATIC_LIBRARY) + +# For the device +# ===================================================== +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := $(target_SRC_FILES) + +LOCAL_MODULE:= libLLVMTarget + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_DEVICE_BUILD_MK) +include $(BUILD_STATIC_LIBRARY) diff --git a/lib/Target/Mips/Android.mk b/lib/Target/Mips/Android.mk new file mode 100644 index 0000000..954b1d0 --- /dev/null +++ b/lib/Target/Mips/Android.mk @@ -0,0 +1,84 @@ +LOCAL_PATH := $(call my-dir) + +mips_codegen_TBLGEN_TABLES := \ + MipsGenRegisterInfo.inc \ + MipsGenInstrInfo.inc \ + MipsGenCodeEmitter.inc \ + MipsGenMCCodeEmitter.inc \ + MipsGenMCPseudoLowering.inc \ + MipsGenAsmWriter.inc \ + MipsGenDAGISel.inc \ + MipsGenCallingConv.inc \ + MipsGenSubtargetInfo.inc + +mips_codegen_SRC_FILES := \ + Mips16FrameLowering.cpp \ + Mips16HardFloat.cpp \ + Mips16ISelDAGToDAG.cpp \ + Mips16ISelLowering.cpp \ + Mips16InstrInfo.cpp \ + Mips16RegisterInfo.cpp \ + MipsAnalyzeImmediate.cpp \ + MipsAsmPrinter.cpp \ + MipsCodeEmitter.cpp \ + MipsConstantIslandPass.cpp \ + MipsDelaySlotFiller.cpp \ + MipsFrameLowering.cpp \ + MipsInstrInfo.cpp \ + MipsISelDAGToDAG.cpp \ + MipsISelLowering.cpp \ + MipsJITInfo.cpp \ + MipsLongBranch.cpp \ + MipsMachineFunction.cpp \ + MipsMCInstLower.cpp \ + MipsModuleISelDAGToDAG.cpp \ + MipsOptimizeMathLibCalls.cpp \ + MipsOs16.cpp \ + MipsRegisterInfo.cpp \ + MipsSEFrameLowering.cpp \ + MipsSEISelDAGToDAG.cpp \ + MipsSEISelLowering.cpp \ + MipsSEInstrInfo.cpp \ + MipsSERegisterInfo.cpp \ + MipsSelectionDAGInfo.cpp \ + MipsSubtarget.cpp \ + MipsTargetMachine.cpp \ + MipsTargetObjectFile.cpp + +# For the host +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMMipsCodeGen +LOCAL_MODULE_TAGS := optional + +LOCAL_SRC_FILES := $(mips_codegen_SRC_FILES) +LOCAL_C_INCLUDES := $(LOCAL_PATH)/MCTargetDesc + +TBLGEN_TABLES := $(mips_codegen_TBLGEN_TABLES) + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(LLVM_GEN_INTRINSICS_MK) +include $(BUILD_HOST_STATIC_LIBRARY) + +# For the device only +# ===================================================== +ifeq ($(TARGET_ARCH),mips) +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMMipsCodeGen +LOCAL_MODULE_TAGS := optional + +LOCAL_SRC_FILES := $(mips_codegen_SRC_FILES) +LOCAL_C_INCLUDES := $(LOCAL_PATH)/MCTargetDesc + +TBLGEN_TABLES := $(mips_codegen_TBLGEN_TABLES) + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(LLVM_GEN_INTRINSICS_MK) +include $(BUILD_STATIC_LIBRARY) +endif diff --git a/lib/Target/Mips/AsmParser/Android.mk b/lib/Target/Mips/AsmParser/Android.mk new file mode 100644 index 0000000..7d1817d --- /dev/null +++ b/lib/Target/Mips/AsmParser/Android.mk @@ -0,0 +1,54 @@ +LOCAL_PATH := $(call my-dir) + +#===---------------------------------------------------------------=== +# libLLVMMipsAsmParser (common) +#===---------------------------------------------------------------=== + +mips_asm_parser_SRC_FILES := \ + MipsAsmParser.cpp + +mips_asm_parser_C_INCLUDES := $(LOCAL_PATH)/.. + +mips_asm_parser_TBLGEN_TABLES := \ + MipsGenAsmMatcher.inc \ + MipsGenInstrInfo.inc \ + MipsGenRegisterInfo.inc \ + MipsGenSubtargetInfo.inc + +mips_asm_parser_TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + + +#===---------------------------------------------------------------=== +# libLLVMMipsAsmParser (host) +#===---------------------------------------------------------------=== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMMipsAsmParser +LOCAL_MODULE_TAGS := optional +LOCAL_SRC_FILES := $(mips_asm_parser_SRC_FILES) +LOCAL_C_INCLUDES += $(mips_asm_parser_C_INCLUDES) +TBLGEN_TABLES := $(mips_asm_parser_TBLGEN_TABLES) +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_HOST_STATIC_LIBRARY) + + +#===---------------------------------------------------------------=== +# libLLVMMipsAsmParser (target) +#===---------------------------------------------------------------=== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMMipsAsmParser +LOCAL_MODULE_TAGS := optional +LOCAL_SRC_FILES := $(mips_asm_parser_SRC_FILES) +LOCAL_C_INCLUDES += $(mips_asm_parser_C_INCLUDES) +TBLGEN_TABLES := $(mips_asm_parser_TBLGEN_TABLES) +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_STATIC_LIBRARY) diff --git a/lib/Target/Mips/Disassembler/Android.mk b/lib/Target/Mips/Disassembler/Android.mk new file mode 100644 index 0000000..4e38c4b --- /dev/null +++ b/lib/Target/Mips/Disassembler/Android.mk @@ -0,0 +1,48 @@ +LOCAL_PATH := $(call my-dir) + +mips_disassembler_TBLGEN_TABLES := \ + MipsGenDisassemblerTables.inc \ + MipsGenInstrInfo.inc \ + MipsGenRegisterInfo.inc \ + MipsGenSubtargetInfo.inc + +mips_disassembler_SRC_FILES := \ + MipsDisassembler.cpp + +# For the device +# ===================================================== +ifeq ($(TARGET_ARCH),mips) +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMMipsDisassembler +LOCAL_MODULE_TAGS := optional + +LOCAL_SRC_FILES := $(mips_disassembler_SRC_FILES) +LOCAL_C_INCLUDES += $(LOCAL_PATH)/.. + +TBLGEN_TABLES := $(mips_disassembler_TBLGEN_TABLES) +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_STATIC_LIBRARY) +endif + +# For the host +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMMipsDisassembler +LOCAL_MODULE_TAGS := optional + +LOCAL_SRC_FILES := $(mips_disassembler_SRC_FILES) +LOCAL_C_INCLUDES += $(LOCAL_PATH)/.. + +TBLGEN_TABLES := $(mips_disassembler_TBLGEN_TABLES) +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_HOST_STATIC_LIBRARY) diff --git a/lib/Target/Mips/InstPrinter/Android.mk b/lib/Target/Mips/InstPrinter/Android.mk new file mode 100644 index 0000000..fc256cd --- /dev/null +++ b/lib/Target/Mips/InstPrinter/Android.mk @@ -0,0 +1,46 @@ +LOCAL_PATH := $(call my-dir) + +mips_asm_printer_TBLGEN_TABLES := \ + MipsGenAsmWriter.inc \ + MipsGenRegisterInfo.inc \ + MipsGenSubtargetInfo.inc \ + MipsGenInstrInfo.inc + +mips_asm_printer_SRC_FILES := \ + MipsInstPrinter.cpp + +# For the host +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMMipsAsmPrinter +LOCAL_MODULE_TAGS := optional + +TBLGEN_TABLES := $(mips_asm_printer_TBLGEN_TABLES) +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(mips_asm_printer_SRC_FILES) +LOCAL_C_INCLUDES += $(LOCAL_PATH)/.. + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_HOST_STATIC_LIBRARY) + +# For the device only +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMMipsAsmPrinter +LOCAL_MODULE_TAGS := optional + +TBLGEN_TABLES := $(mips_asm_printer_TBLGEN_TABLES) +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(mips_asm_printer_SRC_FILES) +LOCAL_C_INCLUDES += $(LOCAL_PATH)/.. + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_STATIC_LIBRARY) diff --git a/lib/Target/Mips/MCTargetDesc/Android.mk b/lib/Target/Mips/MCTargetDesc/Android.mk new file mode 100644 index 0000000..fcf58c3 --- /dev/null +++ b/lib/Target/Mips/MCTargetDesc/Android.mk @@ -0,0 +1,56 @@ +LOCAL_PATH := $(call my-dir) + +mips_mc_desc_TBLGEN_TABLES := \ + MipsGenRegisterInfo.inc \ + MipsGenInstrInfo.inc \ + MipsGenMCCodeEmitter.inc \ + MipsGenSubtargetInfo.inc + +mips_mc_desc_SRC_FILES := \ + MipsAsmBackend.cpp \ + MipsELFObjectWriter.cpp \ + MipsELFStreamer.cpp \ + MipsMCAsmInfo.cpp \ + MipsMCCodeEmitter.cpp \ + MipsMCTargetDesc.cpp \ + MipsReginfo.cpp + +# For the host +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMMipsDesc +LOCAL_MODULE_TAGS := optional + +LOCAL_SRC_FILES := $(mips_mc_desc_SRC_FILES) +LOCAL_C_INCLUDES := $(LOCAL_PATH)/.. + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. +TBLGEN_TABLES := $(mips_mc_desc_TBLGEN_TABLES) + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(LLVM_GEN_INTRINSICS_MK) +include $(BUILD_HOST_STATIC_LIBRARY) + +# For the device only +# ===================================================== +ifeq ($(TARGET_ARCH),mips) +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMMipsDesc +LOCAL_MODULE_TAGS := optional + +LOCAL_SRC_FILES := $(mips_mc_desc_SRC_FILES) +LOCAL_C_INCLUDES := $(LOCAL_PATH)/.. + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. +TBLGEN_TABLES := $(mips_mc_desc_TBLGEN_TABLES) + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(LLVM_GEN_INTRINSICS_MK) +include $(BUILD_STATIC_LIBRARY) +endif diff --git a/lib/Target/Mips/TargetInfo/Android.mk b/lib/Target/Mips/TargetInfo/Android.mk new file mode 100644 index 0000000..e3f41bc --- /dev/null +++ b/lib/Target/Mips/TargetInfo/Android.mk @@ -0,0 +1,47 @@ +LOCAL_PATH := $(call my-dir) + +mips_target_info_TBLGEN_TABLES := \ + MipsGenInstrInfo.inc \ + MipsGenRegisterInfo.inc \ + MipsGenSubtargetInfo.inc + +mips_target_info_SRC_FILES := \ + MipsTargetInfo.cpp + +# For the host +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMMipsInfo +LOCAL_MODULE_TAGS := optional + +TBLGEN_TABLES := $(mips_target_info_TBLGEN_TABLES) +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(mips_target_info_SRC_FILES) +LOCAL_C_INCLUDES += $(LOCAL_PATH)/.. + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_HOST_STATIC_LIBRARY) + +# For the device +# ===================================================== +ifeq ($(TARGET_ARCH),mips) +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMMipsInfo +LOCAL_MODULE_TAGS := optional + +TBLGEN_TABLES := $(mips_target_info_TBLGEN_TABLES) +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(mips_target_info_SRC_FILES) +LOCAL_C_INCLUDES += $(LOCAL_PATH)/.. + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_STATIC_LIBRARY) +endif diff --git a/lib/Target/X86/Android.mk b/lib/Target/X86/Android.mk new file mode 100644 index 0000000..a9c413d --- /dev/null +++ b/lib/Target/X86/Android.mk @@ -0,0 +1,72 @@ +LOCAL_PATH := $(call my-dir) + +x86_codegen_TBLGEN_TABLES := \ + X86GenAsmWriter.inc \ + X86GenAsmWriter1.inc \ + X86GenRegisterInfo.inc \ + X86GenInstrInfo.inc \ + X86GenDAGISel.inc \ + X86GenFastISel.inc \ + X86GenSubtargetInfo.inc \ + X86GenCallingConv.inc + +x86_codegen_SRC_FILES := \ + X86AsmPrinter.cpp \ + X86COFFMachineModuleInfo.cpp \ + X86CodeEmitter.cpp \ + X86FastISel.cpp \ + X86FixupLEAs.cpp \ + X86FloatingPoint.cpp \ + X86FrameLowering.cpp \ + X86ISelDAGToDAG.cpp \ + X86ISelLowering.cpp \ + X86InstrInfo.cpp \ + X86JITInfo.cpp \ + X86MachineFunctionInfo.cpp \ + X86MCInstLower.cpp \ + X86PadShortFunction.cpp \ + X86RegisterInfo.cpp \ + X86SelectionDAGInfo.cpp \ + X86Subtarget.cpp \ + X86TargetMachine.cpp \ + X86TargetObjectFile.cpp \ + X86TargetTransformInfo.cpp \ + X86VZeroUpper.cpp + +# For the host +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +TBLGEN_TABLES := $(x86_codegen_TBLGEN_TABLES) + +LOCAL_SRC_FILES := $(x86_codegen_SRC_FILES) + +LOCAL_MODULE:= libLLVMX86CodeGen + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(LLVM_GEN_INTRINSICS_MK) +include $(BUILD_HOST_STATIC_LIBRARY) + +# For the device only +# ===================================================== +ifeq ($(TARGET_ARCH),x86) +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +TBLGEN_TABLES := $(x86_codegen_TBLGEN_TABLES) + +LOCAL_SRC_FILES := $(x86_codegen_SRC_FILES) + +LOCAL_MODULE:= libLLVMX86CodeGen + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(LLVM_GEN_INTRINSICS_MK) +include $(BUILD_STATIC_LIBRARY) +endif diff --git a/lib/Target/X86/AsmParser/Android.mk b/lib/Target/X86/AsmParser/Android.mk new file mode 100644 index 0000000..d6de437 --- /dev/null +++ b/lib/Target/X86/AsmParser/Android.mk @@ -0,0 +1,56 @@ +LOCAL_PATH := $(call my-dir) + +# For the device only +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +x86_asm_parser_SRC_FILES := \ + X86AsmParser.cpp + +x86_asm_parser_TBLGEN_TABLES := \ + X86GenAsmMatcher.inc \ + X86GenInstrInfo.inc \ + X86GenRegisterInfo.inc \ + X86GenSubtargetInfo.inc + +x86_asm_parser_TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +x86_asm_parser_C_INCLUDES += \ + $(LOCAL_PATH)/.. + + +#===---------------------------------------------------------------=== +# libX86AsmParser (host) +#===---------------------------------------------------------------=== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMX86AsmParser +LOCAL_MODULE_TAGS := optional +LOCAL_SRC_FILES := $(x86_asm_parser_SRC_FILES) +LOCAL_C_INCLUDES += $(x86_asm_parser_C_INCLUDES) +TBLGEN_TABLES := $(x86_asm_parser_TBLGEN_TABLES) +TBLGEN_TD_DIR := $(x86_asm_parser_TBLGEN_TD_DIR) + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_HOST_STATIC_LIBRARY) + + +#===---------------------------------------------------------------=== +# libX86AsmParser (target) +#===---------------------------------------------------------------=== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMX86AsmParser +LOCAL_MODULE_TAGS := optional +LOCAL_SRC_FILES := $(x86_asm_parser_SRC_FILES) +LOCAL_C_INCLUDES += $(x86_asm_parser_C_INCLUDES) +TBLGEN_TABLES := $(x86_asm_parser_TBLGEN_TABLES) +TBLGEN_TD_DIR := $(x86_asm_parser_TBLGEN_TD_DIR) + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_STATIC_LIBRARY) diff --git a/lib/Target/X86/Disassembler/Android.mk b/lib/Target/X86/Disassembler/Android.mk new file mode 100644 index 0000000..1cee663 --- /dev/null +++ b/lib/Target/X86/Disassembler/Android.mk @@ -0,0 +1,55 @@ +LOCAL_PATH := $(call my-dir) + +x86_disassembler_TBLGEN_TABLES := \ + X86GenDisassemblerTables.inc \ + X86GenInstrInfo.inc \ + X86GenRegisterInfo.inc + +x86_disassembler_SRC_FILES := \ + X86Disassembler.cpp \ + X86DisassemblerDecoder.c + +# For the device +# ===================================================== +ifeq ($(TARGET_ARCH),x86) +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +TBLGEN_TABLES := $(x86_disassembler_TBLGEN_TABLES) + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(x86_disassembler_SRC_FILES) + +LOCAL_C_INCLUDES += $(LOCAL_PATH)/.. + +LOCAL_MODULE:= libLLVMX86Disassembler + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_STATIC_LIBRARY) +endif + +# For the host +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +TBLGEN_TABLES := $(x86_disassembler_TBLGEN_TABLES) + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(x86_disassembler_SRC_FILES) + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/.. + +LOCAL_MODULE:= libLLVMX86Disassembler + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_HOST_STATIC_LIBRARY) diff --git a/lib/Target/X86/InstPrinter/Android.mk b/lib/Target/X86/InstPrinter/Android.mk new file mode 100644 index 0000000..0fd7058 --- /dev/null +++ b/lib/Target/X86/InstPrinter/Android.mk @@ -0,0 +1,57 @@ +LOCAL_PATH := $(call my-dir) + +x86_instprinter_TBLGEN_TABLES := \ + X86GenAsmWriter.inc \ + X86GenAsmWriter1.inc \ + X86GenInstrInfo.inc \ + X86GenRegisterInfo.inc \ + X86GenSubtargetInfo.inc + +x86_instprinter_SRC_FILES := \ + X86ATTInstPrinter.cpp \ + X86IntelInstPrinter.cpp \ + X86InstComments.cpp + +# For the device +# ===================================================== +ifeq ($(TARGET_ARCH),x86) +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +TBLGEN_TABLES := $(x86_instprinter_TBLGEN_TABLES) + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(x86_instprinter_SRC_FILES) + +LOCAL_C_INCLUDES += $(LOCAL_PATH)/.. + +LOCAL_MODULE:= libLLVMX86AsmPrinter + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_STATIC_LIBRARY) +endif + +# For the host +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +TBLGEN_TABLES := $(x86_instprinter_TBLGEN_TABLES) + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(x86_instprinter_SRC_FILES) + +LOCAL_C_INCLUDES += $(LOCAL_PATH)/.. + +LOCAL_MODULE := libLLVMX86AsmPrinter + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_HOST_STATIC_LIBRARY) diff --git a/lib/Target/X86/MCTargetDesc/Android.mk b/lib/Target/X86/MCTargetDesc/Android.mk new file mode 100644 index 0000000..31ba842 --- /dev/null +++ b/lib/Target/X86/MCTargetDesc/Android.mk @@ -0,0 +1,56 @@ +LOCAL_PATH := $(call my-dir) + +x86_mc_desc_TBLGEN_TABLES := \ + X86GenRegisterInfo.inc \ + X86GenInstrInfo.inc \ + X86GenSubtargetInfo.inc + +x86_mc_desc_SRC_FILES := \ + X86AsmBackend.cpp \ + X86ELFObjectWriter.cpp \ + X86ELFRelocationInfo.cpp \ + X86MCTargetDesc.cpp \ + X86MCAsmInfo.cpp \ + X86MCCodeEmitter.cpp \ + X86MachORelocationInfo.cpp \ + X86MachObjectWriter.cpp \ + X86WinCOFFObjectWriter.cpp + +# For the host +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +LOCAL_MODULE:= libLLVMX86Desc +LOCAL_MODULE_TAGS := optional + +LOCAL_SRC_FILES := $(x86_mc_desc_SRC_FILES) +LOCAL_C_INCLUDES := $(LOCAL_PATH)/.. +TBLGEN_TABLES := $(x86_mc_desc_TBLGEN_TABLES) +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(LLVM_GEN_INTRINSICS_MK) +include $(BUILD_HOST_STATIC_LIBRARY) + +# For the device only +# ===================================================== +ifeq ($(TARGET_ARCH),x86) +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + + +LOCAL_MODULE:= libLLVMX86Desc +LOCAL_MODULE_TAGS := optional + +LOCAL_SRC_FILES := $(x86_mc_desc_SRC_FILES) +LOCAL_C_INCLUDES := $(LOCAL_PATH)/.. +TBLGEN_TABLES := $(x86_mc_desc_TBLGEN_TABLES) +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(LLVM_GEN_INTRINSICS_MK) +include $(BUILD_STATIC_LIBRARY) +endif diff --git a/lib/Target/X86/TargetInfo/Android.mk b/lib/Target/X86/TargetInfo/Android.mk new file mode 100644 index 0000000..c72b383 --- /dev/null +++ b/lib/Target/X86/TargetInfo/Android.mk @@ -0,0 +1,55 @@ +LOCAL_PATH := $(call my-dir) + +x86_target_info_TBLGEN_TABLES := \ + X86GenRegisterInfo.inc \ + X86GenSubtargetInfo.inc \ + X86GenInstrInfo.inc + +x86_target_info_SRC_FILES := \ + X86TargetInfo.cpp + +# For the host +# ===================================================== +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +TBLGEN_TABLES := $(x86_target_info_TBLGEN_TABLES) + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(x86_target_info_SRC_FILES) + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/.. + +LOCAL_MODULE:= libLLVMX86Info + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_HOST_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_HOST_STATIC_LIBRARY) + +# For the device +# ===================================================== +ifeq ($(TARGET_ARCH),x86) +include $(CLEAR_VARS) +include $(CLEAR_TBLGEN_VARS) + +TBLGEN_TABLES := $(x86_target_info_TBLGEN_TABLES) + +TBLGEN_TD_DIR := $(LOCAL_PATH)/.. + +LOCAL_SRC_FILES := $(x86_target_info_SRC_FILES) + +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/.. + +LOCAL_MODULE:= libLLVMX86Info + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_DEVICE_BUILD_MK) +include $(LLVM_TBLGEN_RULES_MK) +include $(BUILD_STATIC_LIBRARY) +endif diff --git a/lib/Target/X86/Utils/Android.mk b/lib/Target/X86/Utils/Android.mk new file mode 100644 index 0000000..d9dd670 --- /dev/null +++ b/lib/Target/X86/Utils/Android.mk @@ -0,0 +1,34 @@ +LOCAL_PATH := $(call my-dir) + +x86_utils_SRC_FILES := \ + X86ShuffleDecode.cpp + +# For the device +# ===================================================== +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := $(x86_utils_SRC_FILES) + +LOCAL_C_INCLUDES += $(LOCAL_PATH)/.. + +LOCAL_MODULE:= libLLVMX86Utils + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_DEVICE_BUILD_MK) +include $(BUILD_STATIC_LIBRARY) + +# For the host +# ===================================================== +include $(CLEAR_VARS) + +LOCAL_SRC_FILES := $(x86_utils_SRC_FILES) + +LOCAL_C_INCLUDES += $(LOCAL_PATH)/.. + +LOCAL_MODULE:= libLLVMX86Utils + +LOCAL_MODULE_TAGS := optional + +include $(LLVM_HOST_BUILD_MK) +include $(BUILD_HOST_STATIC_LIBRARY) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 00b4976..9ffe29f 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -19028,8 +19028,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, if (Res.second == 0) { // Map st(0) -> st(7) -> ST0 if (Constraint.size() == 7 && Constraint[0] == '{' && - tolower(Constraint[1]) == 's' && - tolower(Constraint[2]) == 't' && + std::tolower(Constraint[1]) == 's' && + std::tolower(Constraint[2]) == 't' && Constraint[3] == '(' && (Constraint[4] >= '0' && Constraint[4] <= '7') && Constraint[5] == ')' && |