diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/PostRASchedulerList.cpp | 22 | ||||
| -rw-r--r-- | lib/Target/ARM/ARM.td | 6 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMSubtarget.cpp | 5 |
3 files changed, 23 insertions, 10 deletions
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index 1a744be..eddc489 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -48,11 +48,17 @@ using namespace llvm; STATISTIC(NumNoops, "Number of noops inserted"); STATISTIC(NumStalls, "Number of pipeline stalls"); +// Post-RA scheduling is enabled with +// TargetSubtarget.enablePostRAScheduler(). This flag can be used to +// override the target. +static cl::opt<bool> +EnablePostRAScheduler("post-RA-scheduler", + cl::desc("Enable scheduling after register allocation"), + cl::init(false)); static cl::opt<bool> EnableAntiDepBreaking("break-anti-dependencies", cl::desc("Break post-RA scheduling anti-dependencies"), cl::init(true), cl::Hidden); - static cl::opt<bool> EnablePostRAHazardAvoidance("avoid-hazards", cl::desc("Enable exact hazard avoidance"), @@ -215,10 +221,16 @@ static bool isSchedulingBoundary(const MachineInstr *MI, } bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { - // Check that post-RA scheduling is enabled for this function - const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>(); - if (!ST.enablePostRAScheduler()) - return true; + // Check for explicit enable/disable of post-ra scheduling. + if (EnablePostRAScheduler.getPosition() > 0) { + if (!EnablePostRAScheduler) + return true; + } else { + // Check that post-RA scheduling is enabled for this function + const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>(); + if (!ST.enablePostRAScheduler()) + return true; + } DEBUG(errs() << "PostRAScheduler\n"); diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 4174899..8069e2b 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -43,9 +43,6 @@ def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2", def FeatureNEONFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", "true", "Use NEON for single-precision FP">; -def FeaturePostRASched : SubtargetFeature<"postrasched", "PostRAScheduler", - "true", - "Use Post-Register-Allocation Scheduler">; //===----------------------------------------------------------------------===// // ARM Processors supported. @@ -108,8 +105,7 @@ def : ProcNoItin<"arm1156t2f-s", [ArchV6T2, FeatureThumb2, FeatureVFP2]>; // V7 Processors. def : Processor<"cortex-a8", CortexA8Itineraries, - [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP, - FeaturePostRASched]>; + [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP]>; def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>; //===----------------------------------------------------------------------===// diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index b46bd0c..704cf7a 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -93,6 +93,11 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS, if (isTargetDarwin()) IsR9Reserved = ReserveR9 | (ARMArchVersion < V6); + + // Set CPU specific features. + if (CPUString == "cortex-a8") { + PostRAScheduler = true; + } } /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol. |