aboutsummaryrefslogtreecommitdiffstats
path: root/lib
diff options
context:
space:
mode:
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp4
-rw-r--r--lib/Target/PowerPC/PPCCallingConv.td39
-rw-r--r--lib/Target/PowerPC/PPCRegisterInfo.cpp52
-rw-r--r--lib/Target/PowerPC/PPCRegisterInfo.td2
4 files changed, 62 insertions, 35 deletions
diff --git a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index cbe1321..7a654ea 100644
--- a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -752,6 +752,10 @@ MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
IntVal = 9;
return false;
+ } else if (Name.equals_lower("vrsave")) {
+ RegNo = PPC::VRSAVE;
+ IntVal = 256;
+ return false;
} else if (Name.substr(0, 1).equals_lower("r") &&
!Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
diff --git a/lib/Target/PowerPC/PPCCallingConv.td b/lib/Target/PowerPC/PPCCallingConv.td
index c8a29a3..a584188 100644
--- a/lib/Target/PowerPC/PPCCallingConv.td
+++ b/lib/Target/PowerPC/PPCCallingConv.td
@@ -105,40 +105,45 @@ def CC_PPC32_SVR4_ByVal : CallingConv<[
CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
]>;
+def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
+ V28, V29, V30, V31)>;
+
def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
R21, R22, R23, R24, R25, R26, R27, R28,
R29, R30, R31, F14, F15, F16, F17, F18,
F19, F20, F21, F22, F23, F24, F25, F26,
- F27, F28, F29, F30, F31, CR2, CR3, CR4,
- V20, V21, V22, V23, V24, V25, V26, V27,
- V28, V29, V30, V31)>;
+ F27, F28, F29, F30, F31, CR2, CR3, CR4
+ )>;
+
+def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
-def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20, VRSAVE,
+def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
R21, R22, R23, R24, R25, R26, R27, R28,
R29, R30, R31, F14, F15, F16, F17, F18,
F19, F20, F21, F22, F23, F24, F25, F26,
- F27, F28, F29, F30, F31, CR2, CR3, CR4,
- V20, V21, V22, V23, V24, V25, V26, V27,
- V28, V29, V30, V31)>;
+ F27, F28, F29, F30, F31, CR2, CR3, CR4
+ )>;
+
+def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
X21, X22, X23, X24, X25, X26, X27, X28,
X29, X30, X31, F14, F15, F16, F17, F18,
F19, F20, F21, F22, F23, F24, F25, F26,
- F27, F28, F29, F30, F31, CR2, CR3, CR4,
- V20, V21, V22, V23, V24, V25, V26, V27,
- V28, V29, V30, V31)>;
+ F27, F28, F29, F30, F31, CR2, CR3, CR4
+ )>;
-def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, VRSAVE,
+def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
+
+def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
X21, X22, X23, X24, X25, X26, X27, X28,
X29, X30, X31, F14, F15, F16, F17, F18,
F19, F20, F21, F22, F23, F24, F25, F26,
- F27, F28, F29, F30, F31, CR2, CR3, CR4,
- V20, V21, V22, V23, V24, V25, V26, V27,
- V28, V29, V30, V31)>;
+ F27, F28, F29, F30, F31, CR2, CR3, CR4
+ )>;
+
-def CSR_NoRegs : CalleeSavedRegs<(add VRSAVE)>;
-def CSR_NoRegs_Darwin : CalleeSavedRegs<(add)>;
+def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>;
-def CSR_NoRegs_Altivec : CalleeSavedRegs<(add (sequence "V%u", 0, 31), VRSAVE)>;
+def CSR_NoRegs : CalleeSavedRegs<(add)>;
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 96b5bb6..06788fe 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -91,32 +91,41 @@ PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
const uint16_t*
PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
if (Subtarget.isDarwinABI())
- return Subtarget.isPPC64() ? CSR_Darwin64_SaveList :
- CSR_Darwin32_SaveList;
-
- return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList;
+ return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
+ CSR_Darwin64_Altivec_SaveList :
+ CSR_Darwin64_SaveList) :
+ (Subtarget.hasAltivec() ?
+ CSR_Darwin32_Altivec_SaveList :
+ CSR_Darwin32_SaveList);
+
+ return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
+ CSR_SVR464_Altivec_SaveList :
+ CSR_SVR464_SaveList) :
+ (Subtarget.hasAltivec() ?
+ CSR_SVR432_Altivec_SaveList :
+ CSR_SVR432_SaveList);
}
const uint32_t*
PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
if (Subtarget.isDarwinABI())
- return Subtarget.isPPC64() ? CSR_Darwin64_RegMask :
- CSR_Darwin32_RegMask;
-
- return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask;
+ return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
+ CSR_Darwin64_Altivec_RegMask :
+ CSR_Darwin64_RegMask) :
+ (Subtarget.hasAltivec() ?
+ CSR_Darwin32_Altivec_RegMask :
+ CSR_Darwin32_RegMask);
+
+ return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
+ CSR_SVR464_Altivec_RegMask :
+ CSR_SVR464_RegMask) :
+ (Subtarget.hasAltivec() ?
+ CSR_SVR432_Altivec_RegMask :
+ CSR_SVR432_RegMask);
}
const uint32_t*
PPCRegisterInfo::getNoPreservedMask() const {
- // The naming here is inverted: The CSR_NoRegs_Altivec has the
- // Altivec registers masked so that they're not saved and restored around
- // instructions with this preserved mask.
-
- if (!Subtarget.hasAltivec())
- return CSR_NoRegs_Altivec_RegMask;
-
- if (Subtarget.isDarwin())
- return CSR_NoRegs_Darwin_RegMask;
return CSR_NoRegs_RegMask;
}
@@ -145,6 +154,9 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
Reserved.set(PPC::LR8);
Reserved.set(PPC::RM);
+ if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
+ Reserved.set(PPC::VRSAVE);
+
// The SVR4 ABI reserves r2 and r13
if (Subtarget.isSVR4ABI()) {
Reserved.set(PPC::R2); // System-reserved register
@@ -170,6 +182,12 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
if (PPCFI->needsFP(MF))
Reserved.set(PPC::R31);
+ // Reserve Altivec registers when Altivec is unavailable.
+ if (!Subtarget.hasAltivec())
+ for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
+ IE = PPC::VRRCRegClass.end(); I != IE; ++I)
+ Reserved.set(*I);
+
return Reserved;
}
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index b1b4f06..003e7c3 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -150,7 +150,7 @@ def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
// VRsave register
-def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[109]>;
+def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
// Carry bit. In the architecture this is really bit 0 of the XER register
// (which really is SPR register 1); this is the only bit interesting to a
generated by cgit v1.1 at 2025-11-12 08:18:47 +0000