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-rw-r--r--test/CodeGen/ARM/vmov.ll44
1 files changed, 22 insertions, 22 deletions
diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll
index 7900af4..b7a23b7 100644
--- a/test/CodeGen/ARM/vmov.ll
+++ b/test/CodeGen/ARM/vmov.ll
@@ -174,7 +174,7 @@ define void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) noun
entry:
;CHECK-LABEL: vdupn128:
;CHECK: vmov.i8 d{{.*}}, #0x80
- %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
+ %0 = getelementptr inbounds %struct.int8x8_t, %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, <8 x i8>* %0, align 8
ret void
}
@@ -183,7 +183,7 @@ define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) no
entry:
;CHECK-LABEL: vdupnneg75:
;CHECK: vmov.i8 d{{.*}}, #0xb5
- %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
+ %0 = getelementptr inbounds %struct.int8x8_t, %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, <8 x i8>* %0, align 8
ret void
}
@@ -191,7 +191,7 @@ entry:
define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
;CHECK-LABEL: vmovls8:
;CHECK: vmovl.s8
- %tmp1 = load <8 x i8>* %A
+ %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
ret <8 x i16> %tmp2
}
@@ -199,7 +199,7 @@ define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
;CHECK-LABEL: vmovls16:
;CHECK: vmovl.s16
- %tmp1 = load <4 x i16>* %A
+ %tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
ret <4 x i32> %tmp2
}
@@ -207,7 +207,7 @@ define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
;CHECK-LABEL: vmovls32:
;CHECK: vmovl.s32
- %tmp1 = load <2 x i32>* %A
+ %tmp1 = load <2 x i32>, <2 x i32>* %A
%tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
ret <2 x i64> %tmp2
}
@@ -215,7 +215,7 @@ define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
;CHECK-LABEL: vmovlu8:
;CHECK: vmovl.u8
- %tmp1 = load <8 x i8>* %A
+ %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
ret <8 x i16> %tmp2
}
@@ -223,7 +223,7 @@ define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
;CHECK-LABEL: vmovlu16:
;CHECK: vmovl.u16
- %tmp1 = load <4 x i16>* %A
+ %tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
ret <4 x i32> %tmp2
}
@@ -231,7 +231,7 @@ define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
;CHECK-LABEL: vmovlu32:
;CHECK: vmovl.u32
- %tmp1 = load <2 x i32>* %A
+ %tmp1 = load <2 x i32>, <2 x i32>* %A
%tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
ret <2 x i64> %tmp2
}
@@ -239,7 +239,7 @@ define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
;CHECK-LABEL: vmovni16:
;CHECK: vmovn.i16
- %tmp1 = load <8 x i16>* %A
+ %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = trunc <8 x i16> %tmp1 to <8 x i8>
ret <8 x i8> %tmp2
}
@@ -247,7 +247,7 @@ define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
;CHECK-LABEL: vmovni32:
;CHECK: vmovn.i32
- %tmp1 = load <4 x i32>* %A
+ %tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
ret <4 x i16> %tmp2
}
@@ -255,7 +255,7 @@ define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
;CHECK-LABEL: vmovni64:
;CHECK: vmovn.i64
- %tmp1 = load <2 x i64>* %A
+ %tmp1 = load <2 x i64>, <2 x i64>* %A
%tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>
ret <2 x i32> %tmp2
}
@@ -263,7 +263,7 @@ define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
;CHECK-LABEL: vqmovns16:
;CHECK: vqmovn.s16
- %tmp1 = load <8 x i16>* %A
+ %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
ret <8 x i8> %tmp2
}
@@ -271,7 +271,7 @@ define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
;CHECK-LABEL: vqmovns32:
;CHECK: vqmovn.s32
- %tmp1 = load <4 x i32>* %A
+ %tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
ret <4 x i16> %tmp2
}
@@ -279,7 +279,7 @@ define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
;CHECK-LABEL: vqmovns64:
;CHECK: vqmovn.s64
- %tmp1 = load <2 x i64>* %A
+ %tmp1 = load <2 x i64>, <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
ret <2 x i32> %tmp2
}
@@ -287,7 +287,7 @@ define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
;CHECK-LABEL: vqmovnu16:
;CHECK: vqmovn.u16
- %tmp1 = load <8 x i16>* %A
+ %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
ret <8 x i8> %tmp2
}
@@ -295,7 +295,7 @@ define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
;CHECK-LABEL: vqmovnu32:
;CHECK: vqmovn.u32
- %tmp1 = load <4 x i32>* %A
+ %tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
ret <4 x i16> %tmp2
}
@@ -303,7 +303,7 @@ define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
;CHECK-LABEL: vqmovnu64:
;CHECK: vqmovn.u64
- %tmp1 = load <2 x i64>* %A
+ %tmp1 = load <2 x i64>, <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
ret <2 x i32> %tmp2
}
@@ -311,7 +311,7 @@ define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
;CHECK-LABEL: vqmovuns16:
;CHECK: vqmovun.s16
- %tmp1 = load <8 x i16>* %A
+ %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
ret <8 x i8> %tmp2
}
@@ -319,7 +319,7 @@ define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
;CHECK-LABEL: vqmovuns32:
;CHECK: vqmovun.s32
- %tmp1 = load <4 x i32>* %A
+ %tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
ret <4 x i16> %tmp2
}
@@ -327,7 +327,7 @@ define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
;CHECK-LABEL: vqmovuns64:
;CHECK: vqmovun.s64
- %tmp1 = load <2 x i64>* %A
+ %tmp1 = load <2 x i64>, <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
ret <2 x i32> %tmp2
}
@@ -348,7 +348,7 @@ declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone
; Radar 8598391.
define void @noTruncStore(<4 x i32>* %a, <4 x i16>* %b) nounwind {
;CHECK: vmovn
- %tmp1 = load <4 x i32>* %a, align 16
+ %tmp1 = load <4 x i32>, <4 x i32>* %a, align 16
%tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
store <4 x i16> %tmp2, <4 x i16>* %b, align 8
ret void
@@ -376,7 +376,7 @@ define void @v_mov_v4f32_undef(<4 x float> * nocapture %p) nounwind {
entry:
;CHECK-LABEL: v_mov_v4f32_undef:
;CHECK: vmov.f32 q{{.*}}, #1.000000e+00
- %a = load <4 x float> *%p
+ %a = load <4 x float> , <4 x float> *%p
%b = fadd <4 x float> %a, <float undef, float 1.0, float 1.0, float 1.0>
store <4 x float> %b, <4 x float> *%p
ret void
generated by cgit v1.1 at 2024-06-09 22:27:38 +0000