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-rw-r--r--test/CodeGen/Mips/llvm-ir/mul.ll109
1 files changed, 72 insertions, 37 deletions
diff --git a/test/CodeGen/Mips/llvm-ir/mul.ll b/test/CodeGen/Mips/llvm-ir/mul.ll
index 1674124..a758280 100644
--- a/test/CodeGen/Mips/llvm-ir/mul.ll
+++ b/test/CodeGen/Mips/llvm-ir/mul.ll
@@ -1,19 +1,27 @@
-; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=M2
-; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R1
-; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R2
-; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=32R6
-; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=M4
-; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=64R1-R2
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=64R1-R2
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=M2 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=32R1-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=32R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=M4 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=64R1-R5 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=64R6
define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -24,9 +32,9 @@ entry:
; M2: sll $[[T0]], $[[T0]], 31
; M2: sra $2, $[[T0]], 31
- ; 32R1-R2: mul $[[T0:[0-9]+]], $4, $5
- ; 32R1-R2: sll $[[T0]], $[[T0]], 31
- ; 32R1-R2: sra $2, $[[T0]], 31
+ ; 32R1-R5: mul $[[T0:[0-9]+]], $4, $5
+ ; 32R1-R5: sll $[[T0]], $[[T0]], 31
+ ; 32R1-R5: sra $2, $[[T0]], 31
; 32R6: mul $[[T0:[0-9]+]], $4, $5
; 32R6: sll $[[T0]], $[[T0]], 31
@@ -37,9 +45,9 @@ entry:
; M4: sll $[[T0]], $[[T0]], 31
; M4: sra $2, $[[T0]], 31
- ; 64R1-R2: mul $[[T0:[0-9]+]], $4, $5
- ; 64R1-R2: sll $[[T0]], $[[T0]], 31
- ; 64R1-R2: sra $2, $[[T0]], 31
+ ; 64R1-R5: mul $[[T0:[0-9]+]], $4, $5
+ ; 64R1-R5: sll $[[T0]], $[[T0]], 31
+ ; 64R1-R5: sra $2, $[[T0]], 31
; 64R6: mul $[[T0:[0-9]+]], $4, $5
; 64R6: sll $[[T0]], $[[T0]], 31
@@ -62,8 +70,8 @@ entry:
; 32R1: sll $[[T0]], $[[T0]], 24
; 32R1: sra $2, $[[T0]], 24
- ; 32R2: mul $[[T0:[0-9]+]], $4, $5
- ; 32R2: seb $2, $[[T0]]
+ ; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5
+ ; 32R2-R5: seb $2, $[[T0]]
; 32R6: mul $[[T0:[0-9]+]], $4, $5
; 32R6: seb $2, $[[T0]]
@@ -99,8 +107,8 @@ entry:
; 32R1: sll $[[T0]], $[[T0]], 16
; 32R1: sra $2, $[[T0]], 16
- ; 32R2: mul $[[T0:[0-9]+]], $4, $5
- ; 32R2: seh $2, $[[T0]]
+ ; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5
+ ; 32R2-R5: seh $2, $[[T0]]
; 32R6: mul $[[T0:[0-9]+]], $4, $5
; 32R6: seh $2, $[[T0]]
@@ -130,10 +138,10 @@ entry:
; M2: mult $4, $5
; M2: mflo $2
- ; 32R1-R2: mul $2, $4, $5
+ ; 32R1-R5: mul $2, $4, $5
; 32R6: mul $2, $4, $5
- ; 64R1-R2: mul $2, $4, $5
+ ; 64R1-R5: mul $2, $4, $5
; 64R6: mul $2, $4, $5
%r = mul i32 %a, %b
ret i32 %r
@@ -153,13 +161,13 @@ entry:
; M2: addu $[[T2:[0-9]+]], $4, $[[T1]]
; M2: addu $2, $[[T2]], $[[T0]]
- ; 32R1-R2: multu $5, $7
- ; 32R1-R2: mflo $3
- ; 32R1-R2: mfhi $[[T0:[0-9]+]]
- ; 32R1-R2: mul $[[T1:[0-9]+]], $4, $7
- ; 32R1-R2: mul $[[T2:[0-9]+]], $5, $6
- ; 32R1-R2: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]]
- ; 32R1-R2: addu $2, $[[T0]], $[[T1]]
+ ; 32R1-R5: multu $5, $7
+ ; 32R1-R5: mflo $3
+ ; 32R1-R5: mfhi $[[T0:[0-9]+]]
+ ; 32R1-R5: mul $[[T1:[0-9]+]], $4, $7
+ ; 32R1-R5: mul $[[T2:[0-9]+]], $5, $6
+ ; 32R1-R5: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]]
+ ; 32R1-R5: addu $2, $[[T0]], $[[T1]]
; 32R6: mul $[[T0:[0-9]+]], $5, $6
; 32R6: muhu $[[T1:[0-9]+]], $5, $7
@@ -171,11 +179,38 @@ entry:
; M4: dmult $4, $5
; M4: mflo $2
- ; 64R1-R2: dmult $4, $5
- ; 64R1-R2: mflo $2
+ ; 64R1-R5: dmult $4, $5
+ ; 64R1-R5: mflo $2
; 64R6: dmul $2, $4, $5
%r = mul i64 %a, %b
ret i64 %r
}
+
+define signext i128 @mul_i128(i128 signext %a, i128 signext %b) {
+entry:
+; ALL-LABEL: mul_i128:
+
+ ; GP32: lw $25, %call16(__multi3)($gp)
+
+ ; GP64-NOT-R6: dmult $4, $7
+ ; GP64-NOT-R6: mflo $[[T0:[0-9]+]]
+ ; GP64-NOT-R6: dmult $5, $6
+ ; GP64-NOT-R6: mflo $[[T1:[0-9]+]]
+ ; GP64-NOT-R6: dmultu $5, $7
+ ; GP64-NOT-R6: mflo $3
+ ; GP64-NOT-R6: mfhi $[[T2:[0-9]+]]
+ ; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]]
+
+ ; 64R6: dmul $[[T0:[0-9]+]], $5, $6
+ ; 64R6: dmuhu $[[T1:[0-9]+]], $5, $7
+ ; 64R6: daddu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+ ; 64R6: dmul $[[T3:[0-9]+]], $4, $7
+ ; 64R6: daddu $2, $[[T2]], $[[T3]]
+ ; 64R6: dmul $3, $5, $7
+
+ %r = mul i128 %a, %b
+ ret i128 %r
+}
generated by cgit v1.1 at 2025-01-21 21:35:29 +0000