diff options
Diffstat (limited to 'test/CodeGen/PowerPC')
54 files changed, 949 insertions, 182 deletions
diff --git a/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll b/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll index 002a064..5992ad4 100644 --- a/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll +++ b/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll @@ -6,7 +6,7 @@ entry: %tmp = icmp sgt i64 %tmp1, 2 ; <i1> [#uses=1] br i1 %tmp, label %UnifiedReturnBlock, label %cond_true cond_true: ; preds = %entry - %tmp.upgrd.1 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp.upgrd.1 = tail call i32 (...) @bar( ) ; <i32> [#uses=0] ret void UnifiedReturnBlock: ; preds = %entry ret void diff --git a/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll b/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll index 3d462b4..ab5f37d 100644 --- a/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll +++ b/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll @@ -10,7 +10,7 @@ entry: %tmp = icmp eq i32 %tmp2, 0 ; <i1> [#uses=1] br i1 %tmp, label %UnifiedReturnBlock, label %cond_true cond_true: ; preds = %entry - tail call i32 (...)* @bar( ) ; <i32>:0 [#uses=0] + tail call i32 (...) @bar( ) ; <i32>:0 [#uses=0] ret void UnifiedReturnBlock: ; preds = %entry ret void diff --git a/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll b/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll index 6e8b5b4..5a6fbf0 100644 --- a/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll +++ b/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll @@ -7,7 +7,7 @@ target triple = "powerpc-apple-darwin8" define i32 @main() { entry: - %tmp = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([18 x i8], [18 x i8]* @str, i32 0, i32 0) ) ; <i32> [#uses=0] + %tmp = tail call i32 (i8*, ...) @printf( i8* getelementptr ([18 x i8], [18 x i8]* @str, i32 0, i32 0) ) ; <i32> [#uses=0] ret i32 0 } diff --git a/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll b/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll index bba3707..b3b7323 100644 --- a/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll +++ b/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll @@ -22,8 +22,8 @@ entry: br i1 %toBool, label %cond_true, label %cond_false cond_true: ; preds = %entry - %tmp3 = call i32 (...)* @bar( ) ; <i32> [#uses=0] - %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0] + %tmp3 = call i32 (...) @bar( ) ; <i32> [#uses=0] + %tmp4 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0] %tmp7 = load i32, i32* %q_addr ; <i32> [#uses=1] %tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1] %tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1] @@ -31,8 +31,8 @@ cond_true: ; preds = %entry br i1 %toBool10, label %cond_true11, label %cond_false15 cond_false: ; preds = %entry - %tmp5 = call i32 (...)* @foo( ) ; <i32> [#uses=0] - %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0] + %tmp5 = call i32 (...) @foo( ) ; <i32> [#uses=0] + %tmp6 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0] %tmp27 = load i32, i32* %q_addr ; <i32> [#uses=1] %tmp28 = icmp ne i32 %tmp27, 0 ; <i1> [#uses=1] %tmp289 = zext i1 %tmp28 to i8 ; <i8> [#uses=1] @@ -40,17 +40,17 @@ cond_false: ; preds = %entry br i1 %toBool210, label %cond_true11, label %cond_false15 cond_true11: ; preds = %cond_next - %tmp13 = call i32 (...)* @foo( ) ; <i32> [#uses=0] - %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0] + %tmp13 = call i32 (...) @foo( ) ; <i32> [#uses=0] + %tmp14 = call i32 (...) @quux( i32 3, i32 4 ) ; <i32> [#uses=0] br label %cond_next18 cond_false15: ; preds = %cond_next - %tmp16 = call i32 (...)* @bar( ) ; <i32> [#uses=0] - %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0] + %tmp16 = call i32 (...) @bar( ) ; <i32> [#uses=0] + %tmp17 = call i32 (...) @quux( i32 3, i32 4 ) ; <i32> [#uses=0] br label %cond_next18 cond_next18: ; preds = %cond_false15, %cond_true11 - %tmp19 = call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp19 = call i32 (...) @bar( ) ; <i32> [#uses=0] br label %return return: ; preds = %cond_next18 diff --git a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll index ee1e233..aae914e 100644 --- a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll +++ b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll @@ -9,7 +9,7 @@ entry: %ttype = alloca i32, align 4 ; <i32*> [#uses=1] %regs = alloca [1024 x %struct.__db_region], align 16 ; <[1024 x %struct.__db_region]*> [#uses=0] %tmp = load i32, i32* %ttype, align 4 ; <i32> [#uses=1] - %tmp1 = call i32 (...)* @bork( i32 %tmp ) ; <i32> [#uses=0] + %tmp1 = call i32 (...) @bork( i32 %tmp ) ; <i32> [#uses=0] ret void ; CHECK: @foo diff --git a/test/CodeGen/PowerPC/2007-09-08-unaligned.ll b/test/CodeGen/PowerPC/2007-09-08-unaligned.ll index 341b632..ccbadb4 100644 --- a/test/CodeGen/PowerPC/2007-09-08-unaligned.ll +++ b/test/CodeGen/PowerPC/2007-09-08-unaligned.ll @@ -42,7 +42,7 @@ entry: %tmp4 = getelementptr <{ i8, double }>, <{ i8, double }>* @v, i32 0, i32 1 ; <double*> [#uses=1] %tmp5 = load double, double* %tmp4, align 1 ; <double> [#uses=1] %tmp6 = getelementptr [8 x i8], [8 x i8]* @.str, i32 0, i32 0 ; <i8*> [#uses=1] - %tmp7 = call i32 (i8*, ...)* @printf( i8* %tmp6, double %tmp23, double %tmp5 ) ; <i32> [#uses=0] + %tmp7 = call i32 (i8*, ...) @printf( i8* %tmp6, double %tmp23, double %tmp5 ) ; <i32> [#uses=0] br label %return return: ; preds = %entry diff --git a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll index 09f331f..13b9be3 100644 --- a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll +++ b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll @@ -17,11 +17,11 @@ define %struct.NSManagedObjectContext* @"+[ListGenerator(Private) managedObjectContextWithModelURL:storeURL:]"(%struct.objc_object* %self, %struct._message_ref_t* %_cmd, %struct.NSURL* %modelURL, %struct.NSURL* %storeURL) { entry: %storeCoordinator = alloca %struct.NSPersistentStoreCoordinator* ; <%struct.NSPersistentStoreCoordinator**> [#uses=0] - %tmp29 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2" ) ; <%struct.objc_object*> [#uses=0] + %tmp29 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...) null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2" ) ; <%struct.objc_object*> [#uses=0] %tmp34 = load %struct.NSString*, %struct.NSString** @NSXMLStoreType, align 8 ; <%struct.NSString*> [#uses=1] %tmp37 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*, %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_5", i32 0, i32 0), align 8 ; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1] - %tmp42 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 1 ) ; <%struct.objc_object*> [#uses=1] - %tmp45 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp37( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_5", %struct.objc_object* %tmp42, %struct.NSString* null ) ; <%struct.objc_object*> [#uses=1] - %tmp48 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", %struct.NSString* %tmp34, i8* null, %struct.NSURL* null, %struct.objc_object* %tmp45, %struct.NSError** null ) ; <%struct.objc_object*> [#uses=0] + %tmp42 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...) null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 1 ) ; <%struct.objc_object*> [#uses=1] + %tmp45 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...) %tmp37( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_5", %struct.objc_object* %tmp42, %struct.NSString* null ) ; <%struct.objc_object*> [#uses=1] + %tmp48 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...) null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", %struct.NSString* %tmp34, i8* null, %struct.NSURL* null, %struct.objc_object* %tmp45, %struct.NSError** null ) ; <%struct.objc_object*> [#uses=0] unreachable } diff --git a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll index b27eec4..ff5f835 100644 --- a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll +++ b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll @@ -15,11 +15,11 @@ define %struct.NSManagedObjectContext* @"+[ListGenerator(Private) managedObjectContextWithModelURL:storeURL:]"(%struct.objc_object* %self, %struct._message_ref_t* %_cmd, %struct.NSURL* %modelURL, %struct.NSURL* %storeURL) { entry: %tmp27 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*, %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2", i32 0, i32 0), align 8 ; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1] - %tmp29 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp27( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2" ) ; <%struct.objc_object*> [#uses=0] + %tmp29 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...) %tmp27( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2" ) ; <%struct.objc_object*> [#uses=0] %tmp33 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*, %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", i32 0, i32 0), align 8 ; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1] %tmp34 = load %struct.NSString*, %struct.NSString** @NSXMLStoreType, align 8 ; <%struct.NSString*> [#uses=1] %tmp40 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*, %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 0, i32 0), align 8 ; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1] - %tmp42 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp40( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 1 ) ; <%struct.objc_object*> [#uses=0] - %tmp48 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp33( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", %struct.NSString* %tmp34, i8* null, %struct.NSURL* null, %struct.objc_object* null, %struct.NSError** null ) ; <%struct.objc_object*> [#uses=0] + %tmp42 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...) %tmp40( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 1 ) ; <%struct.objc_object*> [#uses=0] + %tmp48 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...) %tmp33( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", %struct.NSString* %tmp34, i8* null, %struct.NSURL* null, %struct.objc_object* null, %struct.NSError** null ) ; <%struct.objc_object*> [#uses=0] unreachable } diff --git a/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll b/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll index 9158084..45d4399 100644 --- a/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll +++ b/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll @@ -39,7 +39,7 @@ bb41: ; preds = %bb31 ret i32 0 bb68: ; preds = %bb31 - tail call void (i8*, ...)* @IOLog( i8* getelementptr ([68 x i8], [68 x i8]* @.str34, i32 0, i32 0), i64 %tmp34, i64 0, i32 131072 ) nounwind + tail call void (i8*, ...) @IOLog( i8* getelementptr ([68 x i8], [68 x i8]* @.str34, i32 0, i32 0), i64 %tmp34, i64 0, i32 131072 ) nounwind %tmp2021.i = trunc i64 %Pos.0.reg2mem.0 to i32 ; <i32> [#uses=1] %tmp202122.i = inttoptr i32 %tmp2021.i to i8* ; <i8*> [#uses=1] tail call void @IODelay( i32 500 ) nounwind @@ -55,7 +55,7 @@ bb65.i: ; preds = %bb68 br i1 %tmp67.i, label %_Z24unlock_then_erase_sectory.exit, label %bb70.i bb70.i: ; preds = %bb65.i - tail call void (i8*, ...)* @IOLog( i8* getelementptr ([64 x i8], [64 x i8]* @.str19, i32 0, i32 0), i32 %tmp5455.i ) nounwind + tail call void (i8*, ...) @IOLog( i8* getelementptr ([64 x i8], [64 x i8]* @.str19, i32 0, i32 0), i32 %tmp5455.i ) nounwind ret i32 0 _Z24unlock_then_erase_sectory.exit: ; preds = %bb65.i @@ -66,11 +66,11 @@ _Z24unlock_then_erase_sectory.exit: ; preds = %bb65.i br i1 %tmp100, label %bb31, label %bb103 bb103: ; preds = %_Z24unlock_then_erase_sectory.exit, %bb - tail call void (i8*, ...)* @IOLog( i8* getelementptr ([37 x i8], [37 x i8]* @.str35, i32 0, i32 0) ) nounwind + tail call void (i8*, ...) @IOLog( i8* getelementptr ([37 x i8], [37 x i8]* @.str35, i32 0, i32 0) ) nounwind ret i32 0 bb107: ; preds = %entry - tail call void (i8*, ...)* @IOLog( i8* getelementptr ([48 x i8], [48 x i8]* @.str36, i32 0, i32 0) ) nounwind + tail call void (i8*, ...) @IOLog( i8* getelementptr ([48 x i8], [48 x i8]* @.str36, i32 0, i32 0) ) nounwind %tmp114115 = bitcast i8* %buffer to i16* ; <i16*> [#uses=1] %tmp256 = lshr i64 %bufferSize, 1 ; <i64> [#uses=1] %tmp256257 = trunc i64 %tmp256 to i32 ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll b/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll index 9de1c7f..ee3d0f4 100644 --- a/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll +++ b/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll @@ -4,7 +4,7 @@ define void @llvm_static_func(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, i32 %a10, i32 %a11, i32 %a12, i32 %a13, i32 %a14, i32 %a15) nounwind { entry: - tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i64 0), i32 %a8 ) nounwind ; <i32>:0 [#uses=0] + tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @"\01LC", i32 0, i64 0), i32 %a8 ) nounwind ; <i32>:0 [#uses=0] ret void } diff --git a/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll index d98080b..b107600 100644 --- a/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll +++ b/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll @@ -169,19 +169,19 @@ bb2315: ; preds = %bb2295 bb2317: ; preds = %bb2315 %115 = load i64, i64* %2, align 16 ; <i64> [#uses=1] - %116 = call i32 (...)* @_u16a_cm( i64 %115, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=1] + %116 = call i32 (...) @_u16a_cm( i64 %115, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=1] %117 = sext i32 %116 to i64 ; <i64> [#uses=1] store i64 %117, i64* %2, align 16 %118 = load i64, i64* %3, align 8 ; <i64> [#uses=1] - %119 = call i32 (...)* @_u16a_cm( i64 %118, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=1] + %119 = call i32 (...) @_u16a_cm( i64 %118, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=1] %120 = sext i32 %119 to i64 ; <i64> [#uses=1] store i64 %120, i64* %3, align 8 %121 = load i64, i64* %4, align 16 ; <i64> [#uses=1] - %122 = call i32 (...)* @_u16a_cm( i64 %121, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=1] + %122 = call i32 (...) @_u16a_cm( i64 %121, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=1] %123 = sext i32 %122 to i64 ; <i64> [#uses=1] store i64 %123, i64* %4, align 16 %124 = load i64, i64* %5, align 8 ; <i64> [#uses=1] - %125 = call i32 (...)* @_u16a_cm( i64 %124, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=0] + %125 = call i32 (...) @_u16a_cm( i64 %124, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=0] unreachable bb2318: ; preds = %bb2315 @@ -190,29 +190,29 @@ bb2318: ; preds = %bb2315 %128 = load i64, i64* %127, align 8 ; <i64> [#uses=1] %129 = trunc i64 %128 to i32 ; <i32> [#uses=4] %130 = load i64, i64* %2, align 16 ; <i64> [#uses=1] - %131 = call i32 (...)* @_u16_ff( i64 %130, i32 %129 ) nounwind ; <i32> [#uses=1] + %131 = call i32 (...) @_u16_ff( i64 %130, i32 %129 ) nounwind ; <i32> [#uses=1] %132 = sext i32 %131 to i64 ; <i64> [#uses=1] store i64 %132, i64* %2, align 16 %133 = load i64, i64* %3, align 8 ; <i64> [#uses=1] - %134 = call i32 (...)* @_u16_ff( i64 %133, i32 %129 ) nounwind ; <i32> [#uses=1] + %134 = call i32 (...) @_u16_ff( i64 %133, i32 %129 ) nounwind ; <i32> [#uses=1] %135 = sext i32 %134 to i64 ; <i64> [#uses=1] store i64 %135, i64* %3, align 8 %136 = load i64, i64* %4, align 16 ; <i64> [#uses=1] - %137 = call i32 (...)* @_u16_ff( i64 %136, i32 %129 ) nounwind ; <i32> [#uses=1] + %137 = call i32 (...) @_u16_ff( i64 %136, i32 %129 ) nounwind ; <i32> [#uses=1] %138 = sext i32 %137 to i64 ; <i64> [#uses=1] store i64 %138, i64* %4, align 16 %139 = load i64, i64* %5, align 8 ; <i64> [#uses=1] - %140 = call i32 (...)* @_u16_ff( i64 %139, i32 %129 ) nounwind ; <i32> [#uses=0] + %140 = call i32 (...) @_u16_ff( i64 %139, i32 %129 ) nounwind ; <i32> [#uses=0] unreachable bb2319: ; preds = %bb2326 %141 = getelementptr %struct.CGLSI, %struct.CGLSI* %src, i32 %indvar5021, i32 2 ; <i8**> [#uses=1] %142 = load i8*, i8** %141, align 4 ; <i8*> [#uses=4] %143 = getelementptr i8, i8* %142, i32 0 ; <i8*> [#uses=1] - %144 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %143 ) nounwind ; <i32> [#uses=1] + %144 = call i32 (...) @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %143 ) nounwind ; <i32> [#uses=1] %145 = sext i32 %144 to i64 ; <i64> [#uses=2] %146 = getelementptr i8, i8* %142, i32 0 ; <i8*> [#uses=1] - %147 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %146 ) nounwind ; <i32> [#uses=1] + %147 = call i32 (...) @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %146 ) nounwind ; <i32> [#uses=1] %148 = sext i32 %147 to i64 ; <i64> [#uses=2] %149 = shl i64 %145, 48 ; <i64> [#uses=0] %150 = shl i64 %148, 32 ; <i64> [#uses=1] @@ -220,10 +220,10 @@ bb2319: ; preds = %bb2326 store i64 %145, i64* %2, align 16 store i64 %148, i64* %3, align 8 %152 = getelementptr i8, i8* %142, i32 0 ; <i8*> [#uses=1] - %153 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %152 ) nounwind ; <i32> [#uses=1] + %153 = call i32 (...) @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %152 ) nounwind ; <i32> [#uses=1] %154 = sext i32 %153 to i64 ; <i64> [#uses=0] %155 = getelementptr i8, i8* %142, i32 0 ; <i8*> [#uses=1] - %156 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %155 ) nounwind ; <i32> [#uses=0] + %156 = call i32 (...) @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %155 ) nounwind ; <i32> [#uses=0] unreachable bb2325: ; preds = %bb2326, %bb2295 diff --git a/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll b/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll index d4972a9..0599b74 100644 --- a/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll +++ b/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll @@ -12,7 +12,7 @@ entry: ; CHECK: mtctr r12 ; CHECK: bctrl %0 = load void (...)*, void (...)** @p, align 4 ; <void (...)*> [#uses=1] - call void (...)* %0() nounwind + call void (...) %0() nounwind br label %return return: ; preds = %entry diff --git a/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll b/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll index a488e68..e592091 100644 --- a/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll +++ b/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll @@ -66,7 +66,7 @@ for.end12: ; preds = %for.end.7, %for.end %sub14 = sub nsw i64 %call13, %call1 %conv = sitofp i64 %sub14 to double %div = fdiv double %conv, 1.000000e+06 - %call15 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str152, i64 0, i64 0), double %div) nounwind + %call15 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str152, i64 0, i64 0), double %div) nounwind tail call void @check(i32 1) ret i32 0 diff --git a/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll b/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll index 84c9989..9347682 100644 --- a/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll +++ b/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll @@ -204,7 +204,7 @@ for.end23: ; preds = %for.end17 %sub = sub nsw i64 %call24, %call1 %conv25 = sitofp i64 %sub to double %div = fdiv double %conv25, 1.000000e+06 - %call26 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @.str235, i64 0, i64 0), double %div) nounwind + %call26 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @.str235, i64 0, i64 0), double %div) nounwind %add29 = fadd float %add, 1.000000e+00 %add31 = fadd float %add29, %conv18 %add32 = fadd float %add31, 1.000000e+00 diff --git a/test/CodeGen/PowerPC/and-branch.ll b/test/CodeGen/PowerPC/and-branch.ll index 0484f88..1543205 100644 --- a/test/CodeGen/PowerPC/and-branch.ll +++ b/test/CodeGen/PowerPC/and-branch.ll @@ -7,7 +7,7 @@ entry: %tmp4 = and i1 %tmp3, %tmp ; <i1> [#uses=1] br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock cond_true: ; preds = %entry - %tmp5 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp5 = tail call i32 (...) @bar( ) ; <i32> [#uses=0] ret void UnifiedReturnBlock: ; preds = %entry ret void diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll index 9130921..b4b95a2 100644 --- a/test/CodeGen/PowerPC/atomic-2.ll +++ b/test/CodeGen/PowerPC/atomic-2.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=ppc64 | FileCheck %s -; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-P7U -; RUN: llc < %s -march=ppc64 -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-P7U +; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s +; RUN: llc < %s -march=ppc64 -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-P8U define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind { ; CHECK-LABEL: exchange_and_add: @@ -12,17 +12,17 @@ define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind { define i8 @exchange_and_add8(i8* %mem, i8 %val) nounwind { ; CHECK-LABEL: exchange_and_add8: -; CHECK-P7U: lbarx +; CHECK-P8U: lbarx %tmp = atomicrmw add i8* %mem, i8 %val monotonic -; CHECK-P7U: stbcx. +; CHECK-P8U: stbcx. ret i8 %tmp } define i16 @exchange_and_add16(i16* %mem, i16 %val) nounwind { ; CHECK-LABEL: exchange_and_add16: -; CHECK-P7U: lharx +; CHECK-P8U: lharx %tmp = atomicrmw add i16* %mem, i16 %val monotonic -; CHECK-P7U: sthcx. +; CHECK-P8U: sthcx. ret i16 %tmp } @@ -38,21 +38,21 @@ define i64 @exchange_and_cmp(i64* %mem) nounwind { define i8 @exchange_and_cmp8(i8* %mem) nounwind { ; CHECK-LABEL: exchange_and_cmp8: -; CHECK-P7U: lbarx +; CHECK-P8U: lbarx %tmppair = cmpxchg i8* %mem, i8 0, i8 1 monotonic monotonic %tmp = extractvalue { i8, i1 } %tmppair, 0 -; CHECK-P7U: stbcx. -; CHECK-P7U: stbcx. +; CHECK-P8U: stbcx. +; CHECK-P8U: stbcx. ret i8 %tmp } define i16 @exchange_and_cmp16(i16* %mem) nounwind { ; CHECK-LABEL: exchange_and_cmp16: -; CHECK-P7U: lharx +; CHECK-P8U: lharx %tmppair = cmpxchg i16* %mem, i16 0, i16 1 monotonic monotonic %tmp = extractvalue { i16, i1 } %tmppair, 0 -; CHECK-P7U: sthcx. -; CHECK-P7U: sthcx. +; CHECK-P8U: sthcx. +; CHECK-P8U: sthcx. ret i16 %tmp } @@ -66,17 +66,17 @@ define i64 @exchange(i64* %mem, i64 %val) nounwind { define i8 @exchange8(i8* %mem, i8 %val) nounwind { ; CHECK-LABEL: exchange8: -; CHECK-P7U: lbarx +; CHECK-P8U: lbarx %tmp = atomicrmw xchg i8* %mem, i8 1 monotonic -; CHECK-P7U: stbcx. +; CHECK-P8U: stbcx. ret i8 %tmp } define i16 @exchange16(i16* %mem, i16 %val) nounwind { ; CHECK-LABEL: exchange16: -; CHECK-P7U: lharx +; CHECK-P8U: lharx %tmp = atomicrmw xchg i16* %mem, i16 1 monotonic -; CHECK-P7U: sthcx. +; CHECK-P8U: sthcx. ret i16 %tmp } diff --git a/test/CodeGen/PowerPC/branch-opt.ll b/test/CodeGen/PowerPC/branch-opt.ll index dda1538..d6928dd 100644 --- a/test/CodeGen/PowerPC/branch-opt.ll +++ b/test/CodeGen/PowerPC/branch-opt.ll @@ -11,7 +11,7 @@ entry: br i1 %tmp1.upgrd.1, label %cond_false, label %bb5 bb: ; preds = %bb5, %bb %indvar77 = phi i32 [ %indvar.next78, %bb ], [ 0, %bb5 ] ; <i32> [#uses=1] - %tmp2 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp2 = tail call i32 (...) @bar( ) ; <i32> [#uses=0] %indvar.next78 = add i32 %indvar77, 1 ; <i32> [#uses=2] %exitcond79 = icmp eq i32 %indvar.next78, %X ; <i1> [#uses=1] br i1 %exitcond79, label %cond_next48, label %bb @@ -24,7 +24,7 @@ cond_false: ; preds = %entry br i1 %tmp10.upgrd.2, label %cond_false20, label %bb16 bb12: ; preds = %bb16, %bb12 %indvar72 = phi i32 [ %indvar.next73, %bb12 ], [ 0, %bb16 ] ; <i32> [#uses=1] - %tmp13 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp13 = tail call i32 (...) @bar( ) ; <i32> [#uses=0] %indvar.next73 = add i32 %indvar72, 1 ; <i32> [#uses=2] %exitcond74 = icmp eq i32 %indvar.next73, %Y ; <i1> [#uses=1] br i1 %exitcond74, label %cond_next48, label %bb12 @@ -37,7 +37,7 @@ cond_false20: ; preds = %cond_false br i1 %tmp23.upgrd.3, label %cond_false33, label %bb29 bb25: ; preds = %bb29, %bb25 %indvar67 = phi i32 [ %indvar.next68, %bb25 ], [ 0, %bb29 ] ; <i32> [#uses=1] - %tmp26 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp26 = tail call i32 (...) @bar( ) ; <i32> [#uses=0] %indvar.next68 = add i32 %indvar67, 1 ; <i32> [#uses=2] %exitcond69 = icmp eq i32 %indvar.next68, %Z ; <i1> [#uses=1] br i1 %exitcond69, label %cond_next48, label %bb25 @@ -49,7 +49,7 @@ cond_false33: ; preds = %cond_false20 %tmp36.upgrd.4 = icmp eq i32 %tmp36, 0 ; <i1> [#uses=1] br i1 %tmp36.upgrd.4, label %cond_next48, label %bb42 bb38: ; preds = %bb42 - %tmp39 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp39 = tail call i32 (...) @bar( ) ; <i32> [#uses=0] %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1] br label %bb42 bb42: ; preds = %bb38, %cond_false33 @@ -62,7 +62,7 @@ cond_next48: ; preds = %bb42, %cond_false33, %bb29, %bb25, %bb16, %bb12, %bb5, %tmp50 = icmp eq i32 %W_addr.1, 0 ; <i1> [#uses=1] br i1 %tmp50, label %UnifiedReturnBlock, label %cond_true51 cond_true51: ; preds = %cond_next48 - %tmp52 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp52 = tail call i32 (...) @bar( ) ; <i32> [#uses=0] ret void UnifiedReturnBlock: ; preds = %cond_next48 ret void diff --git a/test/CodeGen/PowerPC/cr1eq-no-extra-moves.ll b/test/CodeGen/PowerPC/cr1eq-no-extra-moves.ll index 477cf2f..2b3ab9b 100644 --- a/test/CodeGen/PowerPC/cr1eq-no-extra-moves.ll +++ b/test/CodeGen/PowerPC/cr1eq-no-extra-moves.ll @@ -7,14 +7,14 @@ target triple = "powerpc-unknown-linux" define void @test(i32 %count) nounwind { entry: ; CHECK: crxor 6, 6, 6 - %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i32 1) nounwind + %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i32 1) nounwind %cmp2 = icmp sgt i32 %count, 0 br i1 %cmp2, label %for.body, label %for.end for.body: ; preds = %entry, %for.body %i.03 = phi i32 [ %inc, %for.body ], [ 0, %entry ] ; CHECK: crxor 6, 6, 6 - %call1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i32 1) nounwind + %call1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i32 1) nounwind %inc = add nsw i32 %i.03, 1 %exitcond = icmp eq i32 %inc, %count br i1 %exitcond, label %for.end, label %for.body diff --git a/test/CodeGen/PowerPC/cr1eq.ll b/test/CodeGen/PowerPC/cr1eq.ll index 5ffc1a2..43cd454 100644 --- a/test/CodeGen/PowerPC/cr1eq.ll +++ b/test/CodeGen/PowerPC/cr1eq.ll @@ -9,9 +9,9 @@ target triple = "powerpc-unknown-freebsd" define void @foo() nounwind { entry: ; CHECK: crxor 6, 6, 6 - %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 1) + %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 1) ; CHECK: creqv 6, 6, 6 - %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str1, i32 0, i32 0), double 1.100000e+00) + %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str1, i32 0, i32 0), double 1.100000e+00) ret void } diff --git a/test/CodeGen/PowerPC/cr_spilling.ll b/test/CodeGen/PowerPC/cr_spilling.ll index fdbcf4b..8ac4e72 100644 --- a/test/CodeGen/PowerPC/cr_spilling.ll +++ b/test/CodeGen/PowerPC/cr_spilling.ll @@ -10,7 +10,7 @@ entry: br i1 false, label %cond_true94, label %cond_next99 cond_true94: ; preds = %entry - %tmp98 = call i32 (i8*, ...)* @printf(i8* getelementptr ([3 x i8], [3 x i8]* @.str242, i32 0, i32 0), i8* null) ; <i32> [#uses=0] + %tmp98 = call i32 (i8*, ...) @printf(i8* getelementptr ([3 x i8], [3 x i8]* @.str242, i32 0, i32 0), i8* null) ; <i32> [#uses=0] %tmp20971 = icmp sgt i32 %tmp86, 0 ; <i1> [#uses=1] br i1 %tmp20971, label %bb101, label %bb212 diff --git a/test/CodeGen/PowerPC/ctrloop-sums.ll b/test/CodeGen/PowerPC/ctrloop-sums.ll index 4d8488c..056ee34 100644 --- a/test/CodeGen/PowerPC/ctrloop-sums.ll +++ b/test/CodeGen/PowerPC/ctrloop-sums.ll @@ -119,7 +119,7 @@ for.body3.lr.ph.us.i: ; preds = %for.inc17, %for.inc br label %for.body3.us.i SumArray.exit: ; preds = %for.inc6.us.i - %call20 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([23 x i8], [23 x i8]* @.str, i64 0, i64 0), i32 100, i32 100, i32 %add.us.i) nounwind + %call20 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([23 x i8], [23 x i8]* @.str, i64 0, i64 0), i32 100, i32 100, i32 %add.us.i) nounwind ret i32 0 ; CHECK: @main diff --git a/test/CodeGen/PowerPC/dbg.ll b/test/CodeGen/PowerPC/dbg.ll index a64d58f..f09fc4f 100644 --- a/test/CodeGen/PowerPC/dbg.ll +++ b/test/CodeGen/PowerPC/dbg.ll @@ -17,7 +17,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!22} -!0 = !MDCompileUnit(language: DW_LANG_C99, producer: "clang version 3.1", isOptimized: true, emissionKind: 0, file: !21, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports: !"") +!0 = !MDCompileUnit(language: DW_LANG_C99, producer: "clang version 3.1", isOptimized: true, emissionKind: 0, file: !21, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports: !1) !1 = !{} !3 = !{!5} !5 = !MDSubprogram(name: "main", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !21, scope: null, type: !7, function: i32 (i32, i8**)* @main, variables: !13) diff --git a/test/CodeGen/PowerPC/div-e-32.ll b/test/CodeGen/PowerPC/div-e-32.ll new file mode 100644 index 0000000..588756b --- /dev/null +++ b/test/CodeGen/PowerPC/div-e-32.ll @@ -0,0 +1,31 @@ +; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s + +; Function Attrs: nounwind +define signext i32 @test1() #0 { +entry: + %0 = call i32 @llvm.ppc.divwe(i32 32, i32 16) + ret i32 %0 +; CHECK: divwe 3, 4, 3 +} + +; Function Attrs: nounwind readnone +declare i32 @llvm.ppc.divwe(i32, i32) #1 + +; Function Attrs: nounwind +define signext i32 @test2() #0 { +entry: + %0 = call i32 @llvm.ppc.divweu(i32 32, i32 16) + ret i32 %0 +; CHECK: divweu 3, 4, 3 +} + +; Function Attrs: nounwind readnone +declare i32 @llvm.ppc.divweu(i32, i32) #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } + +!llvm.ident = !{!0} + +!0 = !{!"clang version 3.7.0 (trunk 231831) (llvm/trunk 231828:231843M)"} diff --git a/test/CodeGen/PowerPC/div-e-all.ll b/test/CodeGen/PowerPC/div-e-all.ll new file mode 100644 index 0000000..912deeb --- /dev/null +++ b/test/CodeGen/PowerPC/div-e-all.ll @@ -0,0 +1,54 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s + +; Function Attrs: nounwind +define signext i32 @test1() #0 { +entry: + %0 = call i32 @llvm.ppc.divwe(i32 32, i32 16) + ret i32 %0 +; CHECK: divwe 3, 4, 3 +} + +; Function Attrs: nounwind readnone +declare i32 @llvm.ppc.divwe(i32, i32) #1 + +; Function Attrs: nounwind +define signext i32 @test2() #0 { +entry: + %0 = call i32 @llvm.ppc.divweu(i32 32, i32 16) + ret i32 %0 +; CHECK: divweu 3, 4, 3 +} + +; Function Attrs: nounwind readnone +declare i32 @llvm.ppc.divweu(i32, i32) #1 + +; Function Attrs: nounwind +define i64 @test3() #0 { +entry: + %0 = call i64 @llvm.ppc.divde(i64 32, i64 16) + ret i64 %0 +; CHECK: divde 3, 4, 3 +} + +; Function Attrs: nounwind readnone +declare i64 @llvm.ppc.divde(i64, i64) #1 + +; Function Attrs: nounwind +define i64 @test4() #0 { +entry: + %0 = call i64 @llvm.ppc.divdeu(i64 32, i64 16) + ret i64 %0 +; CHECK: divdeu 3, 4, 3 +} + +; Function Attrs: nounwind readnone +declare i64 @llvm.ppc.divdeu(i64, i64) #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } + +!llvm.ident = !{!0} + +!0 = !{!"clang version 3.7.0 (trunk 231831) (llvm/trunk 231828:231843M)"} diff --git a/test/CodeGen/PowerPC/f32-to-i64.ll b/test/CodeGen/PowerPC/f32-to-i64.ll new file mode 100644 index 0000000..c138188 --- /dev/null +++ b/test/CodeGen/PowerPC/f32-to-i64.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "E-m:e-p:32:32-i64:64-n32" +target triple = "powerpc-unknown-unknown" + +; Function Attrs: nounwind +define i64 @testullf(float %arg) #0 { +entry: + %arg.addr = alloca float, align 4 + store float %arg, float* %arg.addr, align 4 + %0 = load float, float* %arg.addr, align 4 + %conv = fptoui float %0 to i64 + ret i64 %conv + +; CHECK-LABEL: @testullf +; CHECK: fctiduz [[REG1:[0-9]+]], 1 +; CHECK: stfd [[REG1]], [[OFF:[0-9]+]](1) +; CHECK-DAG: lwz 3, [[OFF]](1) +; CHECK-DAG: lwz 4, {{[0-9]+}}(1) +; CHECK: blr +} + +attributes #0 = { nounwind "target-cpu"="a2" } + diff --git a/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll b/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll index ab439cd..8a873da 100644 --- a/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll +++ b/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll @@ -1,15 +1,12 @@ -;; There are some known limitations in the VSX support during FastIsel -;; (see fast-isel-load-store.ll header). Nevertheless, we are adding some -;; regressions here for bugs we fix in the meantime ; RUN: llc < %s -O0 -fast-isel -mattr=+vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64VSX ;; The semantics of VSX stores for when R0 is used is different depending on ;; whether it is used as base or offset. If used as base, the effective -;; address computation will use zero regardless the content of R0. If used as -;; offset, the content will be used in the effective address. We observed that +;; address computation will use zero regardless of the content of R0. If used as +;; an offset the content will be used in the effective address. We observed that ;; for some constructors, the initialization values were being stored without -;; any offset register being specified which was causing R0 to be used as offset -;; in regions where it contained the value in the link register. This regression +;; an offset register being specified which was causing R0 to be used as offset +;; in regions where it contained the value in the link register. This test ;; verifies that R0 is used as base in these situations. %SomeStruct = type { double } @@ -28,6 +25,4 @@ entry: %0 = load double, double* %V.addr, align 8 store double %0, double* %Val, align 8 ret void - } - - + } diff --git a/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll b/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll new file mode 100644 index 0000000..1d9b648 --- /dev/null +++ b/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll @@ -0,0 +1,426 @@ +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s + +; Function Attrs: nounwind +define zeroext i8 @_Z6testcff(float %arg) { +entry: + %arg.addr = alloca float, align 4 + store float %arg, float* %arg.addr, align 4 + %0 = load float, float* %arg.addr, align 4 + %conv = fptoui float %0 to i8 + ret i8 %conv +; CHECK-LABEL: @_Z6testcff +; CHECK: xscvdpsxws [[CONVREG01:[0-9]+]], 1 +; CHECK: mfvsrwz 3, [[CONVREG01]] +} + +; Function Attrs: nounwind +define float @_Z6testfcc(i8 zeroext %arg) { +entry: + %arg.addr = alloca i8, align 1 + store i8 %arg, i8* %arg.addr, align 1 + %0 = load i8, i8* %arg.addr, align 1 + %conv = uitofp i8 %0 to float + ret float %conv +; CHECK-LABEL: @_Z6testfcc +; CHECK: mtvsrwz [[MOVEREG01:[0-9]+]], 3 +; FIXME: Once we have XSCVUXDSP implemented, this will change +; CHECK: fcfidus 1, [[MOVEREG01]] +} + +; Function Attrs: nounwind +define zeroext i8 @_Z6testcdd(double %arg) { +entry: + %arg.addr = alloca double, align 8 + store double %arg, double* %arg.addr, align 8 + %0 = load double, double* %arg.addr, align 8 + %conv = fptoui double %0 to i8 + ret i8 %conv +; CHECK-LABEL: @_Z6testcdd +; CHECK: xscvdpsxws [[CONVREG02:[0-9]+]], 1 +; CHECK: mfvsrwz 3, [[CONVREG02]] +} + +; Function Attrs: nounwind +define double @_Z6testdcc(i8 zeroext %arg) { +entry: + %arg.addr = alloca i8, align 1 + store i8 %arg, i8* %arg.addr, align 1 + %0 = load i8, i8* %arg.addr, align 1 + %conv = uitofp i8 %0 to double + ret double %conv +; CHECK-LABEL: @_Z6testdcc +; CHECK: mtvsrwz [[MOVEREG02:[0-9]+]], 3 +; CHECK: xscvuxddp 1, [[MOVEREG02]] +} + +; Function Attrs: nounwind +define zeroext i8 @_Z7testucff(float %arg) { +entry: + %arg.addr = alloca float, align 4 + store float %arg, float* %arg.addr, align 4 + %0 = load float, float* %arg.addr, align 4 + %conv = fptoui float %0 to i8 + ret i8 %conv +; CHECK-LABEL: @_Z7testucff +; CHECK: xscvdpsxws [[CONVREG03:[0-9]+]], 1 +; CHECK: mfvsrwz 3, [[CONVREG03]] +} + +; Function Attrs: nounwind +define float @_Z7testfuch(i8 zeroext %arg) { +entry: + %arg.addr = alloca i8, align 1 + store i8 %arg, i8* %arg.addr, align 1 + %0 = load i8, i8* %arg.addr, align 1 + %conv = uitofp i8 %0 to float + ret float %conv +; CHECK-LABEL: @_Z7testfuch +; CHECK: mtvsrwz [[MOVEREG03:[0-9]+]], 3 +; FIXME: Once we have XSCVUXDSP implemented, this will change +; CHECK: fcfidus 1, [[MOVEREG03]] +} + +; Function Attrs: nounwind +define zeroext i8 @_Z7testucdd(double %arg) { +entry: + %arg.addr = alloca double, align 8 + store double %arg, double* %arg.addr, align 8 + %0 = load double, double* %arg.addr, align 8 + %conv = fptoui double %0 to i8 + ret i8 %conv +; CHECK-LABEL: @_Z7testucdd +; CHECK: xscvdpsxws [[CONVREG04:[0-9]+]], 1 +; CHECK: mfvsrwz 3, [[CONVREG04]] +} + +; Function Attrs: nounwind +define double @_Z7testduch(i8 zeroext %arg) { +entry: + %arg.addr = alloca i8, align 1 + store i8 %arg, i8* %arg.addr, align 1 + %0 = load i8, i8* %arg.addr, align 1 + %conv = uitofp i8 %0 to double + ret double %conv +; CHECK-LABEL: @_Z7testduch +; CHECK: mtvsrwz [[MOVEREG04:[0-9]+]], 3 +; CHECK: xscvuxddp 1, [[MOVEREG04]] +} + +; Function Attrs: nounwind +define signext i16 @_Z6testsff(float %arg) { +entry: + %arg.addr = alloca float, align 4 + store float %arg, float* %arg.addr, align 4 + %0 = load float, float* %arg.addr, align 4 + %conv = fptosi float %0 to i16 + ret i16 %conv +; CHECK-LABEL: @_Z6testsff +; CHECK: xscvdpsxws [[CONVREG05:[0-9]+]], 1 +; CHECK: mfvsrwz 3, [[CONVREG05]] +} + +; Function Attrs: nounwind +define float @_Z6testfss(i16 signext %arg) { +entry: + %arg.addr = alloca i16, align 2 + store i16 %arg, i16* %arg.addr, align 2 + %0 = load i16, i16* %arg.addr, align 2 + %conv = sitofp i16 %0 to float + ret float %conv +; CHECK-LABEL: @_Z6testfss +; CHECK: mtvsrwa [[MOVEREG05:[0-9]+]], 3 +; FIXME: Once we have XSCVSXDSP implemented, this will change +; CHECK: fcfids 1, [[MOVEREG05]] +} + +; Function Attrs: nounwind +define signext i16 @_Z6testsdd(double %arg) { +entry: + %arg.addr = alloca double, align 8 + store double %arg, double* %arg.addr, align 8 + %0 = load double, double* %arg.addr, align 8 + %conv = fptosi double %0 to i16 + ret i16 %conv +; CHECK-LABEL: @_Z6testsdd +; CHECK: xscvdpsxws [[CONVREG06:[0-9]+]], 1 +; CHECK: mfvsrwz 3, [[CONVREG06]] +} + +; Function Attrs: nounwind +define double @_Z6testdss(i16 signext %arg) { +entry: + %arg.addr = alloca i16, align 2 + store i16 %arg, i16* %arg.addr, align 2 + %0 = load i16, i16* %arg.addr, align 2 + %conv = sitofp i16 %0 to double + ret double %conv +; CHECK-LABEL: @_Z6testdss +; CHECK: mtvsrwa [[MOVEREG06:[0-9]+]], 3 +; CHECK: xscvsxddp 1, [[MOVEREG06]] +} + +; Function Attrs: nounwind +define zeroext i16 @_Z7testusff(float %arg) { +entry: + %arg.addr = alloca float, align 4 + store float %arg, float* %arg.addr, align 4 + %0 = load float, float* %arg.addr, align 4 + %conv = fptoui float %0 to i16 + ret i16 %conv +; CHECK-LABEL: @_Z7testusff +; CHECK: xscvdpsxws [[CONVREG07:[0-9]+]], 1 +; CHECK: mfvsrwz 3, [[CONVREG07]] +} + +; Function Attrs: nounwind +define float @_Z7testfust(i16 zeroext %arg) { +entry: + %arg.addr = alloca i16, align 2 + store i16 %arg, i16* %arg.addr, align 2 + %0 = load i16, i16* %arg.addr, align 2 + %conv = uitofp i16 %0 to float + ret float %conv +; CHECK-LABEL: @_Z7testfust +; CHECK: mtvsrwz [[MOVEREG07:[0-9]+]], 3 +; FIXME: Once we have XSCVUXDSP implemented, this will change +; CHECK: fcfidus 1, [[MOVEREG07]] +} + +; Function Attrs: nounwind +define zeroext i16 @_Z7testusdd(double %arg) { +entry: + %arg.addr = alloca double, align 8 + store double %arg, double* %arg.addr, align 8 + %0 = load double, double* %arg.addr, align 8 + %conv = fptoui double %0 to i16 + ret i16 %conv +; CHECK-LABEL: @_Z7testusdd +; CHECK: xscvdpsxws [[CONVREG08:[0-9]+]], 1 +; CHECK: mfvsrwz 3, [[CONVREG08]] +} + +; Function Attrs: nounwind +define double @_Z7testdust(i16 zeroext %arg) { +entry: + %arg.addr = alloca i16, align 2 + store i16 %arg, i16* %arg.addr, align 2 + %0 = load i16, i16* %arg.addr, align 2 + %conv = uitofp i16 %0 to double + ret double %conv +; CHECK-LABEL: @_Z7testdust +; CHECK: mtvsrwz [[MOVEREG08:[0-9]+]], 3 +; CHECK: xscvuxddp 1, [[MOVEREG08]] +} + +; Function Attrs: nounwind +define signext i32 @_Z6testiff(float %arg) { +entry: + %arg.addr = alloca float, align 4 + store float %arg, float* %arg.addr, align 4 + %0 = load float, float* %arg.addr, align 4 + %conv = fptosi float %0 to i32 + ret i32 %conv +; CHECK-LABEL: @_Z6testiff +; CHECK: xscvdpsxws [[CONVREG09:[0-9]+]], 1 +; CHECK: mfvsrwz 3, [[CONVREG09]] +} + +; Function Attrs: nounwind +define float @_Z6testfii(i32 signext %arg) { +entry: + %arg.addr = alloca i32, align 4 + store i32 %arg, i32* %arg.addr, align 4 + %0 = load i32, i32* %arg.addr, align 4 + %conv = sitofp i32 %0 to float + ret float %conv +; CHECK-LABEL: @_Z6testfii +; CHECK: mtvsrwa [[MOVEREG09:[0-9]+]], 3 +; FIXME: Once we have XSCVSXDSP implemented, this will change +; CHECK: fcfids 1, [[MOVEREG09]] +} + +; Function Attrs: nounwind +define signext i32 @_Z6testidd(double %arg) { +entry: + %arg.addr = alloca double, align 8 + store double %arg, double* %arg.addr, align 8 + %0 = load double, double* %arg.addr, align 8 + %conv = fptosi double %0 to i32 + ret i32 %conv +; CHECK-LABEL: @_Z6testidd +; CHECK: xscvdpsxws [[CONVREG10:[0-9]+]], 1 +; CHECK: mfvsrwz 3, [[CONVREG10]] +} + +; Function Attrs: nounwind +define double @_Z6testdii(i32 signext %arg) { +entry: + %arg.addr = alloca i32, align 4 + store i32 %arg, i32* %arg.addr, align 4 + %0 = load i32, i32* %arg.addr, align 4 + %conv = sitofp i32 %0 to double + ret double %conv +; CHECK-LABEL: @_Z6testdii +; CHECK: mtvsrwa [[MOVEREG10:[0-9]+]], 3 +; CHECK: xscvsxddp 1, [[MOVEREG10]] +} + +; Function Attrs: nounwind +define zeroext i32 @_Z7testuiff(float %arg) { +entry: + %arg.addr = alloca float, align 4 + store float %arg, float* %arg.addr, align 4 + %0 = load float, float* %arg.addr, align 4 + %conv = fptoui float %0 to i32 + ret i32 %conv +; CHECK-LABEL: @_Z7testuiff +; CHECK: xscvdpuxws [[CONVREG11:[0-9]+]], 1 +; CHECK: mfvsrwz 3, [[CONVREG11]] +} + +; Function Attrs: nounwind +define float @_Z7testfuij(i32 zeroext %arg) { +entry: + %arg.addr = alloca i32, align 4 + store i32 %arg, i32* %arg.addr, align 4 + %0 = load i32, i32* %arg.addr, align 4 + %conv = uitofp i32 %0 to float + ret float %conv +; CHECK-LABEL: @_Z7testfuij +; CHECK: mtvsrwz [[MOVEREG11:[0-9]+]], 3 +; FIXME: Once we have XSCVUXDSP implemented, this will change +; CHECK: fcfidus 1, [[MOVEREG11]] +} + +; Function Attrs: nounwind +define zeroext i32 @_Z7testuidd(double %arg) { +entry: + %arg.addr = alloca double, align 8 + store double %arg, double* %arg.addr, align 8 + %0 = load double, double* %arg.addr, align 8 + %conv = fptoui double %0 to i32 + ret i32 %conv +; CHECK-LABEL: @_Z7testuidd +; CHECK: xscvdpuxws [[CONVREG12:[0-9]+]], 1 +; CHECK: mfvsrwz 3, [[CONVREG12]] +} + +; Function Attrs: nounwind +define double @_Z7testduij(i32 zeroext %arg) { +entry: + %arg.addr = alloca i32, align 4 + store i32 %arg, i32* %arg.addr, align 4 + %0 = load i32, i32* %arg.addr, align 4 + %conv = uitofp i32 %0 to double + ret double %conv +; CHECK-LABEL: @_Z7testduij +; CHECK: mtvsrwz [[MOVEREG12:[0-9]+]], 3 +; CHECK: xscvuxddp 1, [[MOVEREG12]] +} + +; Function Attrs: nounwind +define i64 @_Z7testllff(float %arg) { +entry: + %arg.addr = alloca float, align 4 + store float %arg, float* %arg.addr, align 4 + %0 = load float, float* %arg.addr, align 4 + %conv = fptosi float %0 to i64 + ret i64 %conv +; CHECK-LABEL: @_Z7testllff +; CHECK: xscvdpsxds [[CONVREG13:[0-9]+]], 1 +; CHECK: mfvsrd 3, [[CONVREG13]] +} + +; Function Attrs: nounwind +define float @_Z7testfllx(i64 %arg) { +entry: + %arg.addr = alloca i64, align 8 + store i64 %arg, i64* %arg.addr, align 8 + %0 = load i64, i64* %arg.addr, align 8 + %conv = sitofp i64 %0 to float + ret float %conv +; CHECK-LABEL:@_Z7testfllx +; CHECK: mtvsrd [[MOVEREG13:[0-9]+]], 3 +; FIXME: Once we have XSCVSXDSP implemented, this will change +; CHECK: fcfids 1, [[MOVEREG13]] +} + +; Function Attrs: nounwind +define i64 @_Z7testlldd(double %arg) { +entry: + %arg.addr = alloca double, align 8 + store double %arg, double* %arg.addr, align 8 + %0 = load double, double* %arg.addr, align 8 + %conv = fptosi double %0 to i64 + ret i64 %conv +; CHECK-LABEL: @_Z7testlldd +; CHECK: xscvdpsxds [[CONVREG14:[0-9]+]], 1 +; CHECK: mfvsrd 3, [[CONVREG14]] +} + +; Function Attrs: nounwind +define double @_Z7testdllx(i64 %arg) { +entry: + %arg.addr = alloca i64, align 8 + store i64 %arg, i64* %arg.addr, align 8 + %0 = load i64, i64* %arg.addr, align 8 + %conv = sitofp i64 %0 to double + ret double %conv +; CHECK-LABEL: @_Z7testdllx +; CHECK: mtvsrd [[MOVEREG14:[0-9]+]], 3 +; CHECK: xscvsxddp 1, [[MOVEREG14]] +} + +; Function Attrs: nounwind +define i64 @_Z8testullff(float %arg) { +entry: + %arg.addr = alloca float, align 4 + store float %arg, float* %arg.addr, align 4 + %0 = load float, float* %arg.addr, align 4 + %conv = fptoui float %0 to i64 + ret i64 %conv +; CHECK-LABEL: @_Z8testullff +; CHECK: xscvdpuxds [[CONVREG15:[0-9]+]], 1 +; CHECK: mfvsrd 3, [[CONVREG15]] +} + +; Function Attrs: nounwind +define float @_Z8testfully(i64 %arg) { +entry: + %arg.addr = alloca i64, align 8 + store i64 %arg, i64* %arg.addr, align 8 + %0 = load i64, i64* %arg.addr, align 8 + %conv = uitofp i64 %0 to float + ret float %conv +; CHECK-LABEL: @_Z8testfully +; CHECK: mtvsrd [[MOVEREG15:[0-9]+]], 3 +; FIXME: Once we have XSCVUXDSP implemented, this will change +; CHECK: fcfidus 1, [[MOVEREG15]] +} + +; Function Attrs: nounwind +define i64 @_Z8testulldd(double %arg) { +entry: + %arg.addr = alloca double, align 8 + store double %arg, double* %arg.addr, align 8 + %0 = load double, double* %arg.addr, align 8 + %conv = fptoui double %0 to i64 + ret i64 %conv +; CHECK-LABEL: @_Z8testulldd +; CHECK: xscvdpuxds [[CONVREG16:[0-9]+]], 1 +; CHECK: mfvsrd 3, [[CONVREG16]] +} + +; Function Attrs: nounwind +define double @_Z8testdully(i64 %arg) { +entry: + %arg.addr = alloca i64, align 8 + store i64 %arg, i64* %arg.addr, align 8 + %0 = load i64, i64* %arg.addr, align 8 + %conv = uitofp i64 %0 to double + ret double %conv +; CHECK-LABEL: @_Z8testdully +; CHECK: mtvsrd [[MOVEREG16:[0-9]+]], 3 +; CHECK: xscvuxddp 1, [[MOVEREG16]] +} diff --git a/test/CodeGen/PowerPC/loop-data-prefetch-inner.ll b/test/CodeGen/PowerPC/loop-data-prefetch-inner.ll new file mode 100644 index 0000000..adcc7b9 --- /dev/null +++ b/test/CodeGen/PowerPC/loop-data-prefetch-inner.ll @@ -0,0 +1,66 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-bgq-linux" + +; Function Attrs: nounwind +define void @foo(double* %x, double* nocapture readonly %y) #0 { +entry: + %scevgep = getelementptr double, double* %x, i64 1599 + %scevgep20 = getelementptr double, double* %y, i64 1599 + br label %vector.memcheck + +vector.memcheck: ; preds = %for.end, %entry + %j.015 = phi i32 [ 0, %entry ], [ %inc7, %for.end ] + %bound0 = icmp uge double* %scevgep20, %x + %bound1 = icmp uge double* %scevgep, %y + %memcheck.conflict = and i1 %bound0, %bound1 + br i1 %memcheck.conflict, label %middle.block, label %vector.body + +vector.body: ; preds = %vector.memcheck, %vector.body + %index = phi i64 [ %index.next, %vector.body ], [ 0, %vector.memcheck ] + %0 = getelementptr inbounds double, double* %y, i64 %index + %1 = bitcast double* %0 to <4 x double>* + %wide.load = load <4 x double>, <4 x double>* %1, align 8 + %2 = fadd <4 x double> %wide.load, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %3 = getelementptr inbounds double, double* %x, i64 %index + %4 = bitcast double* %3 to <4 x double>* + store <4 x double> %2, <4 x double>* %4, align 8 + %index.next = add i64 %index, 4 + %5 = icmp eq i64 %index.next, 1600 + br i1 %5, label %middle.block, label %vector.body + +middle.block: ; preds = %vector.body, %vector.memcheck + %resume.val = phi i1 [ false, %vector.memcheck ], [ true, %vector.body ] + %trunc.resume.val = phi i64 [ 0, %vector.memcheck ], [ 1600, %vector.body ] + br i1 %resume.val, label %for.end, label %for.body3 + +for.body3: ; preds = %middle.block, %for.body3 + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3 ], [ %trunc.resume.val, %middle.block ] + %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv + %6 = load double, double* %arrayidx, align 8 + %add = fadd double %6, 1.000000e+00 + %arrayidx5 = getelementptr inbounds double, double* %x, i64 %indvars.iv + store double %add, double* %arrayidx5, align 8 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1600 + br i1 %exitcond, label %for.end, label %for.body3 + +for.end: ; preds = %middle.block, %for.body3 + tail call void @bar(double* %x) #2 + %inc7 = add nuw nsw i32 %j.015, 1 + %exitcond16 = icmp eq i32 %inc7, 100 + br i1 %exitcond16, label %for.end8, label %vector.memcheck + +for.end8: ; preds = %for.end + ret void + +; CHECK-LABEL: @foo +; CHECK: dcbt +} + +declare void @bar(double*) #1 + +attributes #0 = { nounwind "target-cpu"="a2q" } +attributes #1 = { "target-cpu"="a2q" } +attributes #2 = { nounwind } + diff --git a/test/CodeGen/PowerPC/loop-prep-all.ll b/test/CodeGen/PowerPC/loop-prep-all.ll new file mode 100644 index 0000000..895daff --- /dev/null +++ b/test/CodeGen/PowerPC/loop-prep-all.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-bgq-linux < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BGQ +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @foo(double* nocapture %x, double* nocapture readonly %y) #0 { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv + %0 = load double, double* %arrayidx, align 8 + %add = fadd double %0, 1.000000e+00 + %arrayidx2 = getelementptr inbounds double, double* %x, i64 %indvars.iv + store double %add, double* %arrayidx2, align 8 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond19 = icmp eq i64 %indvars.iv.next, 1600 + br i1 %exitcond19, label %for.body7, label %for.body + +; CHECK-LABEL: @foo + +; CHECK-BGQ-DAG: dcbt 4, 5 +; CHECK-DAG: lfdu [[REG1:[0-9]+]], 8({{[0-9]+}}) +; CHECK-DAG: fadd [[REG2:[0-9]+]], [[REG1]], 0 +; CHECK-DAG: stfdu [[REG2]], 8({{[0-9]+}}) +; CHECK: bdnz + +; CHECK: blr + +for.cond.cleanup6: ; preds = %for.body7 + ret void + +for.body7: ; preds = %for.body, %for.body7 + %i3.017 = phi i32 [ %inc9, %for.body7 ], [ 0, %for.body ] + tail call void bitcast (void (...)* @bar to void ()*)() #2 + %inc9 = add nuw nsw i32 %i3.017, 1 + %exitcond = icmp eq i32 %inc9, 1024 + br i1 %exitcond, label %for.cond.cleanup6, label %for.body7 +} + +declare void @bar(...) #1 + +attributes #0 = { nounwind "target-cpu"="a2q" } +attributes #1 = { "target-cpu"="a2q" } +attributes #2 = { nounwind } + diff --git a/test/CodeGen/PowerPC/mcm-obj-2.ll b/test/CodeGen/PowerPC/mcm-obj-2.ll index f31d852..36c5856 100644 --- a/test/CodeGen/PowerPC/mcm-obj-2.ll +++ b/test/CodeGen/PowerPC/mcm-obj-2.ll @@ -20,7 +20,7 @@ entry: ; accessing function-scoped variable si. ; ; CHECK: Relocations [ -; CHECK: Section (2) .rela.text { +; CHECK: Section {{.*}} .rela.text { ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]] ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM2]] ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]] diff --git a/test/CodeGen/PowerPC/mcm-obj.ll b/test/CodeGen/PowerPC/mcm-obj.ll index 770ef35..46295cf 100644 --- a/test/CodeGen/PowerPC/mcm-obj.ll +++ b/test/CodeGen/PowerPC/mcm-obj.ll @@ -22,12 +22,12 @@ entry: ; accessing external variable ei. ; ; MEDIUM: Relocations [ -; MEDIUM: Section (2) .rela.text { +; MEDIUM: Section {{.*}} .rela.text { ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]] ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]] ; ; LARGE: Relocations [ -; LARGE: Section (2) .rela.text { +; LARGE: Section {{.*}} .rela.text { ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]] ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]] diff --git a/test/CodeGen/PowerPC/memset-nc-le.ll b/test/CodeGen/PowerPC/memset-nc-le.ll new file mode 100644 index 0000000..af8e9c3 --- /dev/null +++ b/test/CodeGen/PowerPC/memset-nc-le.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le" + +; Function Attrs: nounwind +define void @test_vsx() unnamed_addr #0 align 2 { +entry: + %0 = load i32, i32* undef, align 4 + %1 = trunc i32 %0 to i8 + call void @llvm.memset.p0i8.i64(i8* null, i8 %1, i64 32, i32 1, i1 false) + ret void + +; CHECK-LABEL: @test_vsx +; CHECK: stxvd2x +; CHECK: stxvd2x +; CHECK: blr +} + +; Function Attrs: nounwind +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #1 + +attributes #0 = { nounwind "target-cpu"="pwr8" } +attributes #1 = { nounwind } + diff --git a/test/CodeGen/PowerPC/memset-nc.ll b/test/CodeGen/PowerPC/memset-nc.ll new file mode 100644 index 0000000..414a987 --- /dev/null +++ b/test/CodeGen/PowerPC/memset-nc.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s | FileCheck %s +; RUN: llc -O0 < %s | FileCheck %s -check-prefix=CHECK-O0 +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-bgq-linux" + +; Function Attrs: nounwind +define void @test_qpx() unnamed_addr #0 align 2 { +entry: + %0 = load i32, i32* undef, align 4 + %1 = trunc i32 %0 to i8 + call void @llvm.memset.p0i8.i64(i8* null, i8 %1, i64 64, i32 32, i1 false) + ret void + +; CHECK-LABEL: @test_qpx +; CHECK: qvstfdx +; CHECK: qvstfdx +; CHECK: blr + +; CHECK-O0-LABEL: @test_qpx +; CHECK-O0-NOT: qvstfdx +; CHECK-O0: blr +} + +; Function Attrs: nounwind +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #1 + +; Function Attrs: nounwind +define void @test_vsx() unnamed_addr #2 align 2 { +entry: + %0 = load i32, i32* undef, align 4 + %1 = trunc i32 %0 to i8 + call void @llvm.memset.p0i8.i64(i8* null, i8 %1, i64 32, i32 1, i1 false) + ret void + +; CHECK-LABEL: @test_vsx +; CHECK: stxvw4x +; CHECK: stxvw4x +; CHECK: blr + +; CHECK-O0-LABEL: @test_vsx +; CHECK-O0-NOT: stxvw4x +; CHECK-O0: blr +} + +attributes #0 = { nounwind "target-cpu"="a2q" } +attributes #1 = { nounwind } +attributes #2 = { nounwind "target-cpu"="pwr7" } + diff --git a/test/CodeGen/PowerPC/optnone-crbits-i1-ret.ll b/test/CodeGen/PowerPC/optnone-crbits-i1-ret.ll new file mode 100644 index 0000000..745a038 --- /dev/null +++ b/test/CodeGen/PowerPC/optnone-crbits-i1-ret.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-bgq-linux" + +declare zeroext i1 @ri1() +declare void @se1() +declare void @se2() + +define void @test() #0 { +entry: + %b = call zeroext i1 @ri1() + br label %next + +; CHECK-LABEL: @test +; CHECK: bl ri1 +; CHECK-NEXT: nop +; CHECK: andi. 3, 3, 1 + +next: + br i1 %b, label %case1, label %case2 + +case1: + call void @se1() + br label %end + +case2: + call void @se2() + br label %end + +end: + ret void + +; CHECK: blr +} + +attributes #0 = { noinline optnone } + diff --git a/test/CodeGen/PowerPC/pip-inner.ll b/test/CodeGen/PowerPC/pip-inner.ll new file mode 100644 index 0000000..930f0d3 --- /dev/null +++ b/test/CodeGen/PowerPC/pip-inner.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @foo(double* %x, double* nocapture readonly %y) #0 { +entry: + br label %for.cond1.preheader + +for.cond1.preheader: ; preds = %for.end, %entry + %i.015 = phi i32 [ 0, %entry ], [ %inc7, %for.end ] + br label %for.body3 + +for.body3: ; preds = %for.body3, %for.cond1.preheader + %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.body3 ] + %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv + %0 = load double, double* %arrayidx, align 8 + %add = fadd double %0, 1.000000e+00 + %arrayidx5 = getelementptr inbounds double, double* %x, i64 %indvars.iv + store double %add, double* %arrayidx5, align 8 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 16000 + br i1 %exitcond, label %for.end, label %for.body3 + +for.end: ; preds = %for.body3 + tail call void @bar(double* %x) #2 + %inc7 = add nuw nsw i32 %i.015, 1 + %exitcond16 = icmp eq i32 %inc7, 1000 + br i1 %exitcond16, label %for.end8, label %for.cond1.preheader + +for.end8: ; preds = %for.end + ret void + +; CHECK-LABEL: @foo + +; CHECK: lfdu [[REG1:[0-9]+]], 8({{[0-9]+}}) +; CHECK: fadd [[REG2:[0-9]+]], [[REG1]], {{[0-9]+}} +; CHECK: stfdu [[REG2]], 8({{[0-9]+}}) +; CHECK: bdnz + +; CHECK: bl bar +; CHECK-NEXT: nop + +; CHECK: blr +} + +declare void @bar(double*) #1 + +attributes #0 = { nounwind "target-cpu"="a2" } +attributes #1 = { "target-cpu"="a2" } +attributes #2 = { nounwind } + diff --git a/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll b/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll index 6e0aec2..ad8ed38 100644 --- a/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll +++ b/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll @@ -5,7 +5,7 @@ target triple = "powerpc-unknown-linux-gnu" declare void @printf(i8*, ...) define void @main() { - call void (i8*, ...)* @printf(i8* undef, i1 false) + call void (i8*, ...) @printf(i8* undef, i1 false) ret void } diff --git a/test/CodeGen/PowerPC/ppc32-pic-large.ll b/test/CodeGen/PowerPC/ppc32-pic-large.ll index 4c85ab9..6a06945 100644 --- a/test/CodeGen/PowerPC/ppc32-pic-large.ll +++ b/test/CodeGen/PowerPC/ppc32-pic-large.ll @@ -6,7 +6,7 @@ declare i32 @call_foo(i32, ...) define i32 @foo() { entry: %0 = load i32, i32* @bar, align 4 - %call = call i32 (i32, ...)* @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64) + %call = call i32 (i32, ...) @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64) ret i32 %0 } diff --git a/test/CodeGen/PowerPC/ppc32-pic.ll b/test/CodeGen/PowerPC/ppc32-pic.ll index 74f9394..63f521c 100644 --- a/test/CodeGen/PowerPC/ppc32-pic.ll +++ b/test/CodeGen/PowerPC/ppc32-pic.ll @@ -6,7 +6,7 @@ declare i32 @call_foo(i32, ...) define i32 @foo() { entry: %0 = load i32, i32* @bar, align 4 - %call = call i32 (i32, ...)* @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64) + %call = call i32 (i32, ...) @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64) ret i32 0 } diff --git a/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll b/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll index 479c7a7..dfa6ec0 100644 --- a/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll +++ b/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll @@ -8,7 +8,7 @@ define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i6 i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24, i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32) { entry: - %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 32, + %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 32, i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8, i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16, i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24, diff --git a/test/CodeGen/PowerPC/ppc64-anyregcc.ll b/test/CodeGen/PowerPC/ppc64-anyregcc.ll index ab2feb6..66f6a2c 100644 --- a/test/CodeGen/PowerPC/ppc64-anyregcc.ll +++ b/test/CodeGen/PowerPC/ppc64-anyregcc.ll @@ -82,7 +82,7 @@ target triple = "powerpc64-unknown-linux-gnu" ; CHECK-NEXT: .long 3 define i64 @test() nounwind ssp uwtable { entry: - call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 0, i32 24, i8* null, i32 2, i32 1, i32 2, i64 3) + call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 24, i8* null, i32 2, i32 1, i32 2, i64 3) ret i64 0 } @@ -104,7 +104,7 @@ entry: define i64 @property_access1(i8* %obj) nounwind ssp uwtable { entry: %f = inttoptr i64 281474417671919 to i8* - %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 1, i32 24, i8* %f, i32 1, i8* %obj) + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 24, i8* %f, i32 1, i8* %obj) ret i64 %ret } @@ -127,7 +127,7 @@ define i64 @property_access2() nounwind ssp uwtable { entry: %obj = alloca i64, align 8 %f = inttoptr i64 281474417671919 to i8* - %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 24, i8* %f, i32 1, i64* %obj) + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 24, i8* %f, i32 1, i64* %obj) ret i64 %ret } @@ -150,7 +150,7 @@ define i64 @property_access3() nounwind ssp uwtable { entry: %obj = alloca i64, align 8 %f = inttoptr i64 281474417671919 to i8* - %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 24, i8* %f, i32 0, i64* %obj) + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 24, i8* %f, i32 0, i64* %obj) ret i64 %ret } @@ -232,7 +232,7 @@ entry: define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { entry: %f = inttoptr i64 281474417671919 to i8* - %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 4, i32 24, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 24, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) ret i64 %ret } @@ -314,7 +314,7 @@ entry: define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { entry: %f = inttoptr i64 281474417671919 to i8* - %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 24, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 24, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) ret i64 %ret } @@ -342,7 +342,7 @@ entry: ; CHECK-NEXT: .long 0 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { entry: - %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2) + %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2) tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17 },~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind ret i64 %result @@ -384,7 +384,7 @@ define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { entry: tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17 },~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind - %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 13, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4) + %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4) ret i64 %result } diff --git a/test/CodeGen/PowerPC/ppc64-patchpoint.ll b/test/CodeGen/PowerPC/ppc64-patchpoint.ll index 48ffb6a..67b2626 100644 --- a/test/CodeGen/PowerPC/ppc64-patchpoint.ll +++ b/test/CodeGen/PowerPC/ppc64-patchpoint.ll @@ -28,9 +28,9 @@ entry: ; CHECK: blr %resolveCall2 = inttoptr i64 244837814094590 to i8* - %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 24, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4) + %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 24, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4) %resolveCall3 = inttoptr i64 244837814094591 to i8* - tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 3, i32 24, i8* %resolveCall3, i32 2, i64 %p1, i64 %result) + tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 24, i8* %resolveCall3, i32 2, i64 %p1, i64 %result) ret i64 %result } @@ -51,7 +51,7 @@ entry: store i64 11, i64* %metadata store i64 12, i64* %metadata store i64 13, i64* %metadata - call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata) + call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata) ret void } @@ -64,14 +64,14 @@ entry: %tmp80 = add i64 %tmp79, -16 %tmp81 = inttoptr i64 %tmp80 to i64* %tmp82 = load i64, i64* %tmp81, align 8 - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 14, i32 8, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82) - tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 15, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 8, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82) + tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 15, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82) %tmp83 = load i64, i64* %tmp33, align 8 %tmp84 = add i64 %tmp83, -24 %tmp85 = inttoptr i64 %tmp84 to i64* %tmp86 = load i64, i64* %tmp85, align 8 - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 17, i32 8, i64 %arg, i64 %tmp10, i64 %tmp86) - tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 18, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 17, i32 8, i64 %arg, i64 %tmp10, i64 %tmp86) + tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 18, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86) ret i64 10 } @@ -87,7 +87,7 @@ entry: ; CHECK-NEXT: nop ; CHECK-NOT: nop ; CHECK: blr - %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* null, i32 2, i64 %p1, i64 %p2) + %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* null, i32 2, i64 %p1, i64 %p2) ret void } diff --git a/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll b/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll index 368ddc5..19d65b9 100644 --- a/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll +++ b/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll @@ -16,7 +16,7 @@ entry: ; CHECK: mtlr [[REG1]] ; CHECK: blr - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 0, i32 32) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 0, i32 32) ret void } diff --git a/test/CodeGen/PowerPC/ppc64-stackmap.ll b/test/CodeGen/PowerPC/ppc64-stackmap.ll index bc974a0..917fa74 100644 --- a/test/CodeGen/PowerPC/ppc64-stackmap.ll +++ b/test/CodeGen/PowerPC/ppc64-stackmap.ll @@ -112,7 +112,7 @@ target triple = "powerpc64-unknown-linux-gnu" define void @constantargs() { entry: %0 = inttoptr i64 244837814094590 to i8* - tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 1, i32 24, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296) + tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 24, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296) ret void } @@ -134,7 +134,7 @@ entry: ; Runtime void->void call. call void inttoptr (i64 244837814094590 to void ()*)() ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars. - call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b) + call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b) ret void } @@ -160,7 +160,7 @@ entry: cold: ; OSR patchpoint with 12-byte nop-slide and 2 live vars. %thunk = inttoptr i64 244837814094590 to i8* - call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 4, i32 24, i8* %thunk, i32 0, i64 %a, i64 %b) + call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 24, i8* %thunk, i32 0, i64 %a, i64 %b) unreachable ret: ret void @@ -176,7 +176,7 @@ ret: define i64 @propertyRead(i64* %obj) { entry: %resolveRead = inttoptr i64 244837814094590 to i8* - %result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 24, i8* %resolveRead, i32 1, i64* %obj) + %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 24, i8* %resolveRead, i32 1, i64* %obj) %add = add i64 %result, 3 ret i64 %add } @@ -196,7 +196,7 @@ entry: define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) { entry: %resolveWrite = inttoptr i64 244837814094590 to i8* - call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 6, i32 24, i8* %resolveWrite, i32 2, i64* %obj, i64 %a) + call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 24, i8* %resolveWrite, i32 2, i64* %obj, i64 %a) ret void } @@ -218,7 +218,7 @@ entry: define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) { entry: %resolveCall = inttoptr i64 244837814094590 to i8* - call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 7, i32 24, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2) + call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 24, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2) ret void } @@ -240,7 +240,7 @@ entry: define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) { entry: %resolveCall = inttoptr i64 244837814094590 to i8* - %result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 8, i32 24, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2) + %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 24, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2) %add = add i64 %result, 3 ret i64 %add } @@ -260,7 +260,7 @@ entry: ; CHECK-NEXT: .short 31 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) { entry: - call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 11, i32 24, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) + call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 24, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) ret void } @@ -279,7 +279,7 @@ entry: ; CHECK-NEXT: .short 31 define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) { entry: - call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) + call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) ret void } @@ -297,7 +297,7 @@ entry: ; CHECK-NEXT: .long 33 define void @liveConstant() { - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 15, i32 8, i32 33) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 15, i32 8, i32 33) ret void } @@ -314,7 +314,7 @@ define void @liveConstant() { ; CHECK-NEXT: .long {{[0-9]+}} define void @clobberLR(i32 %a) { tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 16, i32 8, i32 %a) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 8, i32 %a) ret void } diff --git a/test/CodeGen/PowerPC/ppcf128-3.ll b/test/CodeGen/PowerPC/ppcf128-3.ll index 5043b62..fe3b418 100644 --- a/test/CodeGen/PowerPC/ppcf128-3.ll +++ b/test/CodeGen/PowerPC/ppcf128-3.ll @@ -4,28 +4,28 @@ define i32 @stp_sequence_set_short_data(%struct.stp_sequence* %sequence, i32 %count, i16* %data) { entry: %tmp1112 = sitofp i16 0 to ppc_fp128 ; <ppc_fp128> [#uses=1] - %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] + %tmp13 = call i32 (...) @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] ret i32 0 } define i32 @stp_sequence_set_short_data2(%struct.stp_sequence* %sequence, i32 %count, i16* %data) { entry: %tmp1112 = sitofp i8 0 to ppc_fp128 ; <ppc_fp128> [#uses=1] - %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] + %tmp13 = call i32 (...) @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] ret i32 0 } define i32 @stp_sequence_set_short_data3(%struct.stp_sequence* %sequence, i32 %count, i16* %data) { entry: %tmp1112 = uitofp i16 0 to ppc_fp128 ; <ppc_fp128> [#uses=1] - %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] + %tmp13 = call i32 (...) @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] ret i32 0 } define i32 @stp_sequence_set_short_data4(%struct.stp_sequence* %sequence, i32 %count, i16* %data) { entry: %tmp1112 = uitofp i8 0 to ppc_fp128 ; <ppc_fp128> [#uses=1] - %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] + %tmp13 = call i32 (...) @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] ret i32 0 } diff --git a/test/CodeGen/PowerPC/remat-imm.ll b/test/CodeGen/PowerPC/remat-imm.ll index 486495e..ffae8a9 100644 --- a/test/CodeGen/PowerPC/remat-imm.ll +++ b/test/CodeGen/PowerPC/remat-imm.ll @@ -9,7 +9,7 @@ define i32 @main() nounwind { entry: ; CHECK: li 4, 128 ; CHECK-NOT: mr 4, {{.*}} - %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), i32 128, i32 128) nounwind + %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), i32 128, i32 128) nounwind ret i32 0 } diff --git a/test/CodeGen/PowerPC/resolvefi-basereg.ll b/test/CodeGen/PowerPC/resolvefi-basereg.ll index 2b22f95..a613c33 100644 --- a/test/CodeGen/PowerPC/resolvefi-basereg.ll +++ b/test/CodeGen/PowerPC/resolvefi-basereg.ll @@ -340,7 +340,7 @@ if.end: ; preds = %if.then, %entry call void @llvm.memcpy.p0i8.p0i8.i64(i8* %65, i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i32 16, i1 false) %66 = bitcast %struct.S1998* %agg.tmp115 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* %66, i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i32 16, i1 false) - call void (i32, ...)* @check1998va(i32 signext 1, double 1.000000e+00, %struct.S1998* byval align 16 %agg.tmp113, i64 2, %struct.S1998* byval align 16 %agg.tmp114, %struct.S1998* byval align 16 %agg.tmp115) + call void (i32, ...) @check1998va(i32 signext 1, double 1.000000e+00, %struct.S1998* byval align 16 %agg.tmp113, i64 2, %struct.S1998* byval align 16 %agg.tmp114, %struct.S1998* byval align 16 %agg.tmp115) %67 = bitcast %struct.S1998* %agg.tmp116 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* %67, i8* bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i32 16, i1 false) %68 = bitcast %struct.S1998* %agg.tmp117 to i8* @@ -349,7 +349,7 @@ if.end: ; preds = %if.then, %entry call void @llvm.memcpy.p0i8.p0i8.i64(i8* %69, i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i32 16, i1 false) %70 = bitcast %struct.S1998* %agg.tmp119 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* %70, i8* bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i32 16, i1 false) - call void (i32, ...)* @check1998va(i32 signext 2, %struct.S1998* byval align 16 %agg.tmp116, %struct.S1998* byval align 16 %agg.tmp117, ppc_fp128 0xM40000000000000000000000000000000, %struct.S1998* byval align 16 %agg.tmp118, %struct.S1998* byval align 16 %agg.tmp119) + call void (i32, ...) @check1998va(i32 signext 2, %struct.S1998* byval align 16 %agg.tmp116, %struct.S1998* byval align 16 %agg.tmp117, ppc_fp128 0xM40000000000000000000000000000000, %struct.S1998* byval align 16 %agg.tmp118, %struct.S1998* byval align 16 %agg.tmp119) ret void } diff --git a/test/CodeGen/PowerPC/s000-alias-misched.ll b/test/CodeGen/PowerPC/s000-alias-misched.ll index 3a0c897..2e34c65 100644 --- a/test/CodeGen/PowerPC/s000-alias-misched.ll +++ b/test/CodeGen/PowerPC/s000-alias-misched.ll @@ -87,7 +87,7 @@ for.end10: ; preds = %for.end %sub = sub nsw i64 %call11, %call1 %conv = sitofp i64 %sub to double %div = fdiv double %conv, 1.000000e+06 - %call12 = tail call signext i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str137, i64 0, i64 0), double %div) nounwind + %call12 = tail call signext i32 (i8*, ...) @printf(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str137, i64 0, i64 0), double %div) nounwind tail call void @check(i32 signext 1) ret i32 0 } diff --git a/test/CodeGen/PowerPC/stack-protector.ll b/test/CodeGen/PowerPC/stack-protector.ll index 48bfbe6..8d255bd 100644 --- a/test/CodeGen/PowerPC/stack-protector.ll +++ b/test/CodeGen/PowerPC/stack-protector.ll @@ -14,7 +14,7 @@ entry: %0 = load i8*, i8** %a_addr, align 4 ; <i8*> [#uses=1] %1 = call i8* @strcpy(i8* %buf1, i8* %0) nounwind ; <i8*> [#uses=0] %buf2 = bitcast [8 x i8]* %buf to i8* ; <i8*> [#uses=1] - %2 = call i32 (i8*, ...)* @printf(i8* getelementptr ([11 x i8], [11 x i8]* @"\01LC", i32 0, i32 0), i8* %buf2) nounwind ; <i32> [#uses=0] + %2 = call i32 (i8*, ...) @printf(i8* getelementptr ([11 x i8], [11 x i8]* @"\01LC", i32 0, i32 0), i8* %buf2) nounwind ; <i32> [#uses=0] br label %return return: ; preds = %entry diff --git a/test/CodeGen/PowerPC/trampoline.ll b/test/CodeGen/PowerPC/trampoline.ll index bc7bee8..e1a26da 100644 --- a/test/CodeGen/PowerPC/trampoline.ll +++ b/test/CodeGen/PowerPC/trampoline.ll @@ -106,7 +106,7 @@ entry: %27 = load %struct.objc_selector*, %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_1", align 4 ; <%struct.objc_selector*> [#uses=1] %__block_holder_tmp_1.03 = bitcast %struct.__block_1* %__block_holder_tmp_1.0 to void (%struct.CGImage*)* ; <void (%struct.CGImage*)*> [#uses=1] %28 = load %struct.objc_object*, %struct.objc_object** %self.1, align 4 ; <%struct.objc_object*> [#uses=1] - %29 = call %struct.objc_object* (%struct.objc_object*, %struct.objc_selector*, ...)* inttoptr (i64 4294901504 to %struct.objc_object* (%struct.objc_object*, %struct.objc_selector*, ...)*)(%struct.objc_object* %28, %struct.objc_selector* %27, void (%struct.CGImage*)* %__block_holder_tmp_1.03) nounwind ; <%struct.objc_object*> [#uses=0] + %29 = call %struct.objc_object* (%struct.objc_object*, %struct.objc_selector*, ...) inttoptr (i64 4294901504 to %struct.objc_object* (%struct.objc_object*, %struct.objc_selector*, ...)*)(%struct.objc_object* %28, %struct.objc_selector* %27, void (%struct.CGImage*)* %__block_holder_tmp_1.03) nounwind ; <%struct.objc_object*> [#uses=0] br label %return return: ; preds = %entry @@ -155,7 +155,7 @@ entry: %15 = load %struct.objc_selector*, %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_0", align 4 ; <%struct.objc_selector*> [#uses=1] %16 = load %struct.objc_super*, %struct.objc_super** %objc_super.5, align 4 ; <%struct.objc_super*> [#uses=1] %17 = load %struct.NSZone*, %struct.NSZone** %zone, align 4 ; <%struct.NSZone*> [#uses=1] - %18 = call %struct.objc_object* (%struct.objc_super*, %struct.objc_selector*, ...)* @objc_msgSendSuper(%struct.objc_super* %16, %struct.objc_selector* %15, %struct.NSZone* %17) nounwind ; <%struct.objc_object*> [#uses=1] + %18 = call %struct.objc_object* (%struct.objc_super*, %struct.objc_selector*, ...) @objc_msgSendSuper(%struct.objc_super* %16, %struct.objc_selector* %15, %struct.NSZone* %17) nounwind ; <%struct.objc_object*> [#uses=1] %19 = bitcast %struct.objc_object* %18 to %struct.NSBitmapImageRep* ; <%struct.NSBitmapImageRep*> [#uses=1] %20 = load %struct.NSBitmapImageRep**, %struct.NSBitmapImageRep*** %new, align 4 ; <%struct.NSBitmapImageRep**> [#uses=1] store %struct.NSBitmapImageRep* %19, %struct.NSBitmapImageRep** %20, align 4 diff --git a/test/CodeGen/PowerPC/varargs-struct-float.ll b/test/CodeGen/PowerPC/varargs-struct-float.ll index dbdda05..7bb5a34 100644 --- a/test/CodeGen/PowerPC/varargs-struct-float.ll +++ b/test/CodeGen/PowerPC/varargs-struct-float.ll @@ -12,7 +12,7 @@ entry: store float %s.coerce, float* %coerce.dive, align 1 %coerce.dive1 = getelementptr %struct.Sf1, %struct.Sf1* %s, i32 0, i32 0 %0 = load float, float* %coerce.dive1, align 1 - call void (i32, ...)* @testvaSf1(i32 1, float inreg %0) + call void (i32, ...) @testvaSf1(i32 1, float inreg %0) ret void } diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll index 45df814..858b85d 100644 --- a/test/CodeGen/PowerPC/vec_constants.ll +++ b/test/CodeGen/PowerPC/vec_constants.ll @@ -1,7 +1,5 @@ -; RUN: llc -O0 -mcpu=pwr7 < %s | FileCheck %s - -target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" -target triple = "powerpc64-unknown-linux-gnu" +; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind { %tmp = load <4 x i32>, <4 x i32>* %P1 ; <<4 x i32>> [#uses=1] diff --git a/test/CodeGen/PowerPC/vperm-lowering.ll b/test/CodeGen/PowerPC/vperm-lowering.ll index d55d26c..c78ffdd 100644 --- a/test/CodeGen/PowerPC/vperm-lowering.ll +++ b/test/CodeGen/PowerPC/vperm-lowering.ll @@ -9,58 +9,23 @@ define <16 x i8> @foo() nounwind ssp { } ; CHECK: .LCPI0_0: -; CHECK: .byte 31 -; CHECK: .byte 26 -; CHECK: .byte 21 -; CHECK: .byte 16 -; CHECK: .byte 11 -; CHECK: .byte 6 -; CHECK: .byte 1 -; CHECK: .byte 28 -; CHECK: .byte 23 -; CHECK: .byte 18 -; CHECK: .byte 13 -; CHECK: .byte 8 -; CHECK: .byte 3 -; CHECK: .byte 30 -; CHECK: .byte 25 -; CHECK: .byte 20 -; CHECK: .LCPI0_1: ; CHECK: .byte 0 -; CHECK: .byte 1 -; CHECK: .byte 2 -; CHECK: .byte 3 -; CHECK: .byte 4 ; CHECK: .byte 5 -; CHECK: .byte 6 -; CHECK: .byte 7 -; CHECK: .byte 8 -; CHECK: .byte 9 ; CHECK: .byte 10 -; CHECK: .byte 11 -; CHECK: .byte 12 -; CHECK: .byte 13 -; CHECK: .byte 14 ; CHECK: .byte 15 -; CHECK: .LCPI0_2: -; CHECK: .byte 16 -; CHECK: .byte 17 -; CHECK: .byte 18 -; CHECK: .byte 19 ; CHECK: .byte 20 -; CHECK: .byte 21 -; CHECK: .byte 22 -; CHECK: .byte 23 -; CHECK: .byte 24 ; CHECK: .byte 25 -; CHECK: .byte 26 -; CHECK: .byte 27 -; CHECK: .byte 28 -; CHECK: .byte 29 ; CHECK: .byte 30 -; CHECK: .byte 31 +; CHECK: .byte 3 +; CHECK: .byte 8 +; CHECK: .byte 13 +; CHECK: .byte 18 +; CHECK: .byte 23 +; CHECK: .byte 28 +; CHECK: .byte 1 +; CHECK: .byte 6 +; CHECK: .byte 11 ; CHECK: foo: -; CHECK: addis [[REG1:[0-9]+]], 2, .LCPI0_2@toc@ha -; CHECK: addi [[REG2:[0-9]+]], [[REG1]], .LCPI0_2@toc@l +; CHECK: addis [[REG1:[0-9]+]], 2, .LCPI0_0@toc@ha +; CHECK: addi [[REG2:[0-9]+]], [[REG1]], .LCPI0_0@toc@l ; CHECK: lvx [[REG3:[0-9]+]], 0, [[REG2]] -; CHECK: vperm {{[0-9]+}}, [[REG3]], {{[0-9]+}}, {{[0-9]+}} diff --git a/test/CodeGen/PowerPC/vsx-fma-m.ll b/test/CodeGen/PowerPC/vsx-fma-m.ll index 64185a4..d859273 100644 --- a/test/CodeGen/PowerPC/vsx-fma-m.ll +++ b/test/CodeGen/PowerPC/vsx-fma-m.ll @@ -98,9 +98,9 @@ entry: ; re-ordering the instructions. ; CHECK-DAG: xsmaddadp [[F1]], 2, 3 -; CHECK-DAG: xsmaddmdp 2, 3, 4 +; CHECK-DAG: xsmaddmdp 3, 2, 4 ; CHECK-DAG: stxsdx [[F1]], 0, 8 -; CHECK-DAG: stxsdx 2, 8, [[C1]] +; CHECK-DAG: stxsdx 3, 8, [[C1]] ; CHECK-DAG: stxsdx 1, 8, [[C2]] ; CHECK-DAG: stxsdx 4, 8, [[C3]] ; CHECK: blr @@ -269,10 +269,10 @@ entry: ; re-ordering the instructions. ; CHECK-DAG: xvmaddadp [[V1]], 35, 36 -; CHECK-DAG: xvmaddmdp 35, 36, 37 +; CHECK-DAG: xvmaddmdp 36, 35, 37 ; CHECK-DAG: xvmaddadp 34, 35, 38 ; CHECK-DAG: stxvd2x 32, 0, 3 -; CHECK-DAG: stxvd2x 35, 3, [[C1]] +; CHECK-DAG: stxvd2x 36, 3, [[C1]] ; CHECK-DAG: stxvd2x 34, 3, [[C2]] ; CHECK-DAG: stxvd2x 37, 3, [[C3]] ; CHECK: blr diff --git a/test/CodeGen/PowerPC/vsx-spill-norwstore.ll b/test/CodeGen/PowerPC/vsx-spill-norwstore.ll index c135a00..77b6cb2 100644 --- a/test/CodeGen/PowerPC/vsx-spill-norwstore.ll +++ b/test/CodeGen/PowerPC/vsx-spill-norwstore.ll @@ -23,7 +23,7 @@ check.exit69.i: ; preds = %entry br i1 undef, label %if.then.i63.i, label %check.exit64.i if.then.i63.i: ; preds = %check.exit69.i - tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str10, i64 0, i64 0), i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str1, i64 0, i64 0)) #0 + tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str10, i64 0, i64 0), i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str1, i64 0, i64 0)) #0 br label %check.exit64.i check.exit64.i: ; preds = %if.then.i63.i, %check.exit69.i |