diff options
Diffstat (limited to 'test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll')
| -rw-r--r-- | test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll | 333 |
1 files changed, 174 insertions, 159 deletions
diff --git a/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll b/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll index eb50942..0b60d0d 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll @@ -3,8 +3,8 @@ declare i32 @llvm.AMDGPU.bfe.i32(i32, i32, i32) nounwind readnone -; FUNC-LABEL: @bfe_i32_arg_arg_arg -; SI: V_BFE_I32 +; FUNC-LABEL: {{^}}bfe_i32_arg_arg_arg: +; SI: v_bfe_i32 ; EG: BFE_INT ; EG: encoding: [{{[x0-9a-f]+,[x0-9a-f]+,[x0-9a-f]+,[x0-9a-f]+,[x0-9a-f]+}},0xac define void @bfe_i32_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind { @@ -13,8 +13,8 @@ define void @bfe_i32_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i ret void } -; FUNC-LABEL: @bfe_i32_arg_arg_imm -; SI: V_BFE_I32 +; FUNC-LABEL: {{^}}bfe_i32_arg_arg_imm: +; SI: v_bfe_i32 ; EG: BFE_INT define void @bfe_i32_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 %src1, i32 123) nounwind readnone @@ -22,8 +22,8 @@ define void @bfe_i32_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) n ret void } -; FUNC-LABEL: @bfe_i32_arg_imm_arg -; SI: V_BFE_I32 +; FUNC-LABEL: {{^}}bfe_i32_arg_imm_arg: +; SI: v_bfe_i32 ; EG: BFE_INT define void @bfe_i32_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 123, i32 %src2) nounwind readnone @@ -31,8 +31,8 @@ define void @bfe_i32_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) n ret void } -; FUNC-LABEL: @bfe_i32_imm_arg_arg -; SI: V_BFE_I32 +; FUNC-LABEL: {{^}}bfe_i32_imm_arg_arg: +; SI: v_bfe_i32 ; EG: BFE_INT define void @bfe_i32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 123, i32 %src1, i32 %src2) nounwind readnone @@ -40,8 +40,8 @@ define void @bfe_i32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) n ret void } -; FUNC-LABEL: @v_bfe_print_arg -; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 2, 8 +; FUNC-LABEL: {{^}}v_bfe_print_arg: +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 2, 8 define void @v_bfe_print_arg(i32 addrspace(1)* %out, i32 addrspace(1)* %src0) nounwind { %load = load i32 addrspace(1)* %src0, align 4 %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 2, i32 8) nounwind readnone @@ -49,9 +49,9 @@ define void @v_bfe_print_arg(i32 addrspace(1)* %out, i32 addrspace(1)* %src0) no ret void } -; FUNC-LABEL: @bfe_i32_arg_0_width_reg_offset -; SI-NOT: BFE -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_arg_0_width_reg_offset: +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_arg_0_width_reg_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 %src1, i32 0) nounwind readnone @@ -59,9 +59,9 @@ define void @bfe_i32_arg_0_width_reg_offset(i32 addrspace(1)* %out, i32 %src0, i ret void } -; FUNC-LABEL: @bfe_i32_arg_0_width_imm_offset -; SI-NOT: BFE -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_arg_0_width_imm_offset: +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 8, i32 0) nounwind readnone @@ -69,10 +69,10 @@ define void @bfe_i32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i ret void } -; FUNC-LABEL: @bfe_i32_test_6 -; SI: V_LSHLREV_B32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} -; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_test_6: +; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} +; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} +; SI: s_endpgm define void @bfe_i32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -81,12 +81,12 @@ define void @bfe_i32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw ret void } -; FUNC-LABEL: @bfe_i32_test_7 -; SI-NOT: SHL -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_test_7: +; SI-NOT: shl +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm define void @bfe_i32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -96,10 +96,10 @@ define void @bfe_i32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FIXME: The shifts should be 1 BFE -; FUNC-LABEL: @bfe_i32_test_8 -; SI: BUFFER_LOAD_DWORD -; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1 -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_test_8: +; SI: buffer_load_dword +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1 +; SI: s_endpgm define void @bfe_i32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -108,11 +108,11 @@ define void @bfe_i32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw ret void } -; FUNC-LABEL: @bfe_i32_test_9 -; SI-NOT: BFE -; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_test_9: +; SI-NOT: {{[^@]}}bfe +; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_i32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 31, i32 1) @@ -120,11 +120,11 @@ define void @bfe_i32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw ret void } -; FUNC-LABEL: @bfe_i32_test_10 -; SI-NOT: BFE -; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_test_10: +; SI-NOT: {{[^@]}}bfe +; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_i32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 1, i32 31) @@ -132,11 +132,11 @@ define void @bfe_i32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun ret void } -; FUNC-LABEL: @bfe_i32_test_11 -; SI-NOT: BFE -; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 8, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_test_11: +; SI-NOT: {{[^@]}}bfe +; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 8, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_i32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 8, i32 24) @@ -144,11 +144,11 @@ define void @bfe_i32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun ret void } -; FUNC-LABEL: @bfe_i32_test_12 -; SI-NOT: BFE -; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 24, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_test_12: +; SI-NOT: {{[^@]}}bfe +; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 24, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_i32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 24, i32 8) @@ -156,10 +156,10 @@ define void @bfe_i32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun ret void } -; FUNC-LABEL: @bfe_i32_test_13 -; SI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 31, {{v[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_test_13: +; SI: v_ashrrev_i32_e32 {{v[0-9]+}}, 31, {{v[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_i32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = ashr i32 %x, 31 @@ -167,10 +167,10 @@ define void @bfe_i32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @bfe_i32_test_14 -; SI-NOT: LSHR -; SI-NOT: BFE -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_test_14: +; SI-NOT: lshr +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_i32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = lshr i32 %x, 31 @@ -178,11 +178,11 @@ define void @bfe_i32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_0 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_0: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_0(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 0, i32 0, i32 0) nounwind readnone @@ -190,11 +190,11 @@ define void @bfe_i32_constant_fold_test_0(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_1 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_1: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_1(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 12334, i32 0, i32 0) nounwind readnone @@ -202,11 +202,11 @@ define void @bfe_i32_constant_fold_test_1(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_2 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_2: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_2(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 0, i32 0, i32 1) nounwind readnone @@ -214,11 +214,11 @@ define void @bfe_i32_constant_fold_test_2(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_3 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_3: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_3(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 1, i32 0, i32 1) nounwind readnone @@ -226,11 +226,11 @@ define void @bfe_i32_constant_fold_test_3(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_4 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_4: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_4(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 4294967295, i32 0, i32 1) nounwind readnone @@ -238,11 +238,11 @@ define void @bfe_i32_constant_fold_test_4(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_5 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_5: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_5(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 128, i32 7, i32 1) nounwind readnone @@ -250,11 +250,11 @@ define void @bfe_i32_constant_fold_test_5(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_6 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0xffffff80 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_6: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0xffffff80 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_6(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 128, i32 0, i32 8) nounwind readnone @@ -262,11 +262,11 @@ define void @bfe_i32_constant_fold_test_6(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_7 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x7f -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_7: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_7(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 127, i32 0, i32 8) nounwind readnone @@ -274,11 +274,11 @@ define void @bfe_i32_constant_fold_test_7(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_8 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_8: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 127, i32 6, i32 8) nounwind readnone @@ -286,11 +286,11 @@ define void @bfe_i32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_9 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_9: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 65536, i32 16, i32 8) nounwind readnone @@ -298,11 +298,11 @@ define void @bfe_i32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_10 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_10: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_10(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 65535, i32 16, i32 16) nounwind readnone @@ -310,11 +310,11 @@ define void @bfe_i32_constant_fold_test_10(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_11 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -6 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_11: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -6 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_11(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 4, i32 4) nounwind readnone @@ -322,11 +322,11 @@ define void @bfe_i32_constant_fold_test_11(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_12 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_12: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_12(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 31, i32 1) nounwind readnone @@ -334,11 +334,11 @@ define void @bfe_i32_constant_fold_test_12(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_13 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_13: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_13(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 131070, i32 16, i32 16) nounwind readnone @@ -346,11 +346,11 @@ define void @bfe_i32_constant_fold_test_13(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_14 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 40 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_14: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 40 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_14(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 2, i32 30) nounwind readnone @@ -358,11 +358,11 @@ define void @bfe_i32_constant_fold_test_14(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_15 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 10 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_15: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 10 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_15(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 4, i32 28) nounwind readnone @@ -370,11 +370,11 @@ define void @bfe_i32_constant_fold_test_15(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_16 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_16: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_16(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 4294967295, i32 1, i32 7) nounwind readnone @@ -382,11 +382,11 @@ define void @bfe_i32_constant_fold_test_16(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_17 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x7f -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_17: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_17(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 255, i32 1, i32 31) nounwind readnone @@ -394,11 +394,11 @@ define void @bfe_i32_constant_fold_test_17(i32 addrspace(1)* %out) nounwind { ret void } -; FUNC-LABEL: @bfe_i32_constant_fold_test_18 -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_18: +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 255, i32 31, i32 1) nounwind readnone @@ -408,14 +408,14 @@ define void @bfe_i32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind { ; XXX - This should really be a single BFE, but the sext_inreg of the ; extended type i24 is never custom lowered. -; FUNC-LABEL: @bfe_sext_in_reg_i24 -; SI: BUFFER_LOAD_DWORD [[LOAD:v[0-9]+]], -; SI: V_LSHLREV_B32_e32 {{v[0-9]+}}, 8, {{v[0-9]+}} -; SI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 8, {{v[0-9]+}} -; XSI: V_BFE_I32 [[BFE:v[0-9]+]], [[LOAD]], 0, 8 +; FUNC-LABEL: {{^}}bfe_sext_in_reg_i24: +; SI: buffer_load_dword [[LOAD:v[0-9]+]], +; SI: v_lshlrev_b32_e32 {{v[0-9]+}}, 8, {{v[0-9]+}} +; SI: v_ashrrev_i32_e32 {{v[0-9]+}}, 8, {{v[0-9]+}} +; XSI: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 0, 8 ; XSI-NOT: SHL ; XSI-NOT: SHR -; XSI: BUFFER_STORE_DWORD [[BFE]], +; XSI: buffer_store_dword [[BFE]], define void @bfe_sext_in_reg_i24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 0, i32 24) @@ -424,3 +424,18 @@ define void @bfe_sext_in_reg_i24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) store i32 %ashr, i32 addrspace(1)* %out, align 4 ret void } + +; FUNC-LABEL: @simplify_demanded_bfe_sdiv +; SI: buffer_load_dword [[LOAD:v[0-9]+]] +; SI: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 1, 16 +; SI: v_lshrrev_b32_e32 [[TMP0:v[0-9]+]], 31, [[BFE]] +; SI: v_add_i32_e32 [[TMP1:v[0-9]+]], [[TMP0]], [[BFE]] +; SI: v_ashrrev_i32_e32 [[TMP2:v[0-9]+]], 1, [[TMP1]] +; SI: buffer_store_dword [[TMP2]] +define void @simplify_demanded_bfe_sdiv(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { + %src = load i32 addrspace(1)* %in, align 4 + %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %src, i32 1, i32 16) nounwind readnone + %div = sdiv i32 %bfe, 2 + store i32 %div, i32 addrspace(1)* %out, align 4 + ret void +} |