diff options
Diffstat (limited to 'test/MC/ARM/arm-ldrd.s')
| -rw-r--r-- | test/MC/ARM/arm-ldrd.s | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/test/MC/ARM/arm-ldrd.s b/test/MC/ARM/arm-ldrd.s new file mode 100644 index 0000000..c26ee25 --- /dev/null +++ b/test/MC/ARM/arm-ldrd.s @@ -0,0 +1,57 @@ +// RUN: not llvm-mc -arch arm -mattr=+v5te %s 2>&1 | FileCheck %s +// +// rdar://14479793 + +ldrd r1, r2, [pc, #0] +ldrd r1, r2, [r3, #4] +ldrd r1, r2, [r3], #4 +ldrd r1, r2, [r3, #4]! +ldrd r1, r2, [r3, -r4]! +ldrd r1, r2, [r3, r4] +ldrd r1, r2, [r3], r4 +// CHECK: error: Rt must be even-numbered +// CHECK: error: Rt must be even-numbered +// CHECK: error: Rt must be even-numbered +// CHECK: error: Rt must be even-numbered +// CHECK: error: Rt must be even-numbered +// CHECK: error: Rt must be even-numbered +// CHECK: error: Rt must be even-numbered + +ldrd r0, r3, [pc, #0] +ldrd r0, r3, [r4, #4] +ldrd r0, r3, [r4], #4 +ldrd r0, r3, [r4, #4]! +ldrd r0, r3, [r4, -r5]! +ldrd r0, r3, [r4, r5] +ldrd r0, r3, [r4], r5 +// CHECK: error: destination operands must be sequential +// CHECK: error: destination operands must be sequential +// CHECK: error: destination operands must be sequential +// CHECK: error: destination operands must be sequential +// CHECK: error: destination operands must be sequential +// CHECK: error: destination operands must be sequential +// CHECK: error: destination operands must be sequential + +ldrd lr, pc, [pc, #0] +ldrd lr, pc, [r3, #4] +ldrd lr, pc, [r3], #4 +ldrd lr, pc, [r3, #4]! +ldrd lr, pc, [r3, -r4]! +ldrd lr, pc, [r3, r4] +ldrd lr, pc, [r3], r4 +// CHECK: error: Rt can't be R14 +// CHECK: error: Rt can't be R14 +// CHECK: error: Rt can't be R14 +// CHECK: error: Rt can't be R14 +// CHECK: error: Rt can't be R14 +// CHECK: error: Rt can't be R14 +// CHECK: error: Rt can't be R14 + +ldrd r0, r1, [r0], #4 +ldrd r0, r1, [r1], #4 +ldrd r0, r1, [r0, #4]! +ldrd r0, r1, [r1, #4]! +// CHECK: error: base register needs to be different from destination registers +// CHECK: error: base register needs to be different from destination registers +// CHECK: error: base register needs to be different from destination registers +// CHECK: error: base register needs to be different from destination registers |