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-rw-r--r--test/MC/ARM/2010-11-30-reloc-movt.s1
-rw-r--r--test/MC/ARM/arm-elf-symver.s6
-rw-r--r--test/MC/ARM/basic-arm-instructions-v8.1a.s64
-rw-r--r--test/MC/ARM/eh-compact-pr0.s27
-rw-r--r--test/MC/ARM/eh-directive-handlerdata.s30
-rw-r--r--test/MC/ARM/eh-directive-personality.s50
-rw-r--r--test/MC/ARM/eh-directive-personalityindex.s97
-rw-r--r--test/MC/ARM/eh-directive-section-multiple-func.s33
-rw-r--r--test/MC/ARM/eh-directive-section.s49
-rw-r--r--test/MC/ARM/eh-link.s90
-rw-r--r--test/MC/ARM/elf-movt.s8
-rw-r--r--test/MC/ARM/elf-reloc-01.ll2
-rw-r--r--test/MC/ARM/elf-reloc-02.ll10
-rw-r--r--test/MC/ARM/elf-reloc-03.ll4
-rw-r--r--test/MC/ARM/elf-reloc-condcall.s2
-rw-r--r--test/MC/ARM/elf-thumbfunc-reloc.ll4
-rw-r--r--test/MC/ARM/elf-thumbfunc-reloc.s2
-rw-r--r--test/MC/ARM/thumb1-relax-adr.s9
-rw-r--r--test/MC/ARM/thumb1-relax-bcc.s12
-rw-r--r--test/MC/ARM/thumb1-relax-br.s19
-rw-r--r--test/MC/ARM/thumb1-relax-ldrlit.s9
-rw-r--r--test/MC/ARM/thumb2-bxj-v8.s11
-rw-r--r--test/MC/ARM/thumb2-bxj.s2
23 files changed, 393 insertions, 148 deletions
diff --git a/test/MC/ARM/2010-11-30-reloc-movt.s b/test/MC/ARM/2010-11-30-reloc-movt.s
index 9de88f0..dc6960b 100644
--- a/test/MC/ARM/2010-11-30-reloc-movt.s
+++ b/test/MC/ARM/2010-11-30-reloc-movt.s
@@ -34,6 +34,7 @@ barf: @ @barf
// CHECK-NEXT: 0000: 00482DE9 000000E3 000040E3 FEFFFFEB
// CHECK-NEXT: 0010: 0088BDE8
// CHECK-NEXT: )
+// CHECK: Name: .rel.text
// CHECK: Relocations [
// CHECK-NEXT: 0x4 R_ARM_MOVW_ABS_NC a
// CHECK-NEXT: 0x8 R_ARM_MOVT_ABS
diff --git a/test/MC/ARM/arm-elf-symver.s b/test/MC/ARM/arm-elf-symver.s
index 5fb1f6a..26d7655 100644
--- a/test/MC/ARM/arm-elf-symver.s
+++ b/test/MC/ARM/arm-elf-symver.s
@@ -23,7 +23,7 @@ defined3:
global1:
@ CHECK: Relocations [
-@ CHECK-NEXT: Section (2) .rel.text {
+@ CHECK-NEXT: Section {{.*}} .rel.text {
@ CHECK-NEXT: 0x0 R_ARM_ABS32 .text 0x0
@ CHECK-NEXT: 0x4 R_ARM_ABS32 bar2@zed 0x0
@ CHECK-NEXT: 0x8 R_ARM_ABS32 .text 0x0
@@ -93,7 +93,7 @@ global1:
@ CHECK-NEXT: Binding: Local (0x0)
@ CHECK-NEXT: Type: Section (0x3)
@ CHECK-NEXT: Other: 0
-@ CHECK-NEXT: Section: .data (0x3)
+@ CHECK-NEXT: Section: .data
@ CHECK-NEXT: }
@ CHECK-NEXT: Symbol {
@ CHECK-NEXT: Name: .bss (0)
@@ -102,7 +102,7 @@ global1:
@ CHECK-NEXT: Binding: Local (0x0)
@ CHECK-NEXT: Type: Section (0x3)
@ CHECK-NEXT: Other: 0
-@ CHECK-NEXT: Section: .bss (0x4)
+@ CHECK-NEXT: Section: .bss
@ CHECK-NEXT: }
@ CHECK-NEXT: Symbol {
@ CHECK-NEXT: Name: g1@@zed
diff --git a/test/MC/ARM/basic-arm-instructions-v8.1a.s b/test/MC/ARM/basic-arm-instructions-v8.1a.s
index f46057b6..005f27b 100644
--- a/test/MC/ARM/basic-arm-instructions-v8.1a.s
+++ b/test/MC/ARM/basic-arm-instructions-v8.1a.s
@@ -43,28 +43,28 @@
vqrdmlah.s16 d0, d1, d2
//CHECK-V81aARM: vqrdmlah.s16 d0, d1, d2 @ encoding: [0x12,0x0b,0x11,0xf3]
//CHECK-V81aTHUMB: vqrdmlah.s16 d0, d1, d2 @ encoding: [0x11,0xff,0x12,0x0b]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s16 d0, d1, d2
//CHECK-V8: ^
vqrdmlah.s32 d0, d1, d2
//CHECK-V81aARM: vqrdmlah.s32 d0, d1, d2 @ encoding: [0x12,0x0b,0x21,0xf3]
//CHECK-V81aTHUMB: vqrdmlah.s32 d0, d1, d2 @ encoding: [0x21,0xff,0x12,0x0b]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s32 d0, d1, d2
//CHECK-V8: ^
vqrdmlah.s16 q0, q1, q2
//CHECK-V81aARM: vqrdmlah.s16 q0, q1, q2 @ encoding: [0x54,0x0b,0x12,0xf3]
//CHECK-V81aTHUMB: vqrdmlah.s16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0b]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s16 q0, q1, q2
//CHECK-V8: ^
vqrdmlah.s32 q2, q3, q0
//CHECK-V81aARM: vqrdmlah.s32 q2, q3, q0 @ encoding: [0x50,0x4b,0x26,0xf3]
//CHECK-V81aTHUMB: vqrdmlah.s32 q2, q3, q0 @ encoding: [0x26,0xff,0x50,0x4b]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s32 q2, q3, q0
//CHECK-V8: ^
@@ -72,28 +72,28 @@
vqrdmlsh.s16 d7, d6, d5
//CHECK-V81aARM: vqrdmlsh.s16 d7, d6, d5 @ encoding: [0x15,0x7c,0x16,0xf3]
//CHECK-V81aTHUMB: vqrdmlsh.s16 d7, d6, d5 @ encoding: [0x16,0xff,0x15,0x7c]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s16 d7, d6, d5
//CHECK-V8: ^
vqrdmlsh.s32 d0, d1, d2
//CHECK-V81aARM: vqrdmlsh.s32 d0, d1, d2 @ encoding: [0x12,0x0c,0x21,0xf3]
//CHECK-V81aTHUMB: vqrdmlsh.s32 d0, d1, d2 @ encoding: [0x21,0xff,0x12,0x0c]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s32 d0, d1, d2
//CHECK-V8: ^
vqrdmlsh.s16 q0, q1, q2
//CHECK-V81aARM: vqrdmlsh.s16 q0, q1, q2 @ encoding: [0x54,0x0c,0x12,0xf3]
//CHECK-V81aTHUMB: vqrdmlsh.s16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0c]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s16 q0, q1, q2
//CHECK-V8: ^
vqrdmlsh.s32 q3, q4, q5
//CHECK-V81aARM: vqrdmlsh.s32 q3, q4, q5 @ encoding: [0x5a,0x6c,0x28,0xf3]
//CHECK-V81aTHUMB: vqrdmlsh.s32 q3, q4, q5 @ encoding: [0x28,0xff,0x5a,0x6c]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s32 q3, q4, q5
//CHECK-V8: ^
@@ -119,28 +119,28 @@
vqrdmlah.s16 d0, d1, d2[0]
//CHECK-V81aARM: vqrdmlah.s16 d0, d1, d2[0] @ encoding: [0x42,0x0e,0x91,0xf2]
//CHECK-V81aTHUMB: vqrdmlah.s16 d0, d1, d2[0] @ encoding: [0x91,0xef,0x42,0x0e]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s16 d0, d1, d2[0]
//CHECK-V8: ^
vqrdmlah.s32 d0, d1, d2[0]
//CHECK-V81aARM: vqrdmlah.s32 d0, d1, d2[0] @ encoding: [0x42,0x0e,0xa1,0xf2]
//CHECK-V81aTHUMB: vqrdmlah.s32 d0, d1, d2[0] @ encoding: [0xa1,0xef,0x42,0x0e]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s32 d0, d1, d2[0]
//CHECK-V8: ^
vqrdmlah.s16 q0, q1, d2[0]
//CHECK-V81aARM: vqrdmlah.s16 q0, q1, d2[0] @ encoding: [0x42,0x0e,0x92,0xf3]
//CHECK-V81aTHUMB: vqrdmlah.s16 q0, q1, d2[0] @ encoding: [0x92,0xff,0x42,0x0e]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s16 q0, q1, d2[0]
//CHECK-V8: ^
vqrdmlah.s32 q0, q1, d2[0]
//CHECK-V81aARM: vqrdmlah.s32 q0, q1, d2[0] @ encoding: [0x42,0x0e,0xa2,0xf3]
//CHECK-V81aTHUMB: vqrdmlah.s32 q0, q1, d2[0] @ encoding: [0xa2,0xff,0x42,0x0e]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s32 q0, q1, d2[0]
//CHECK-V8: ^
@@ -148,27 +148,59 @@
vqrdmlsh.s16 d0, d1, d2[0]
//CHECK-V81aARM: vqrdmlsh.s16 d0, d1, d2[0] @ encoding: [0x42,0x0f,0x91,0xf2]
//CHECK-V81aTHUMB: vqrdmlsh.s16 d0, d1, d2[0] @ encoding: [0x91,0xef,0x42,0x0f]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s16 d0, d1, d2[0]
//CHECK-V8: ^
vqrdmlsh.s32 d0, d1, d2[0]
//CHECK-V81aARM: vqrdmlsh.s32 d0, d1, d2[0] @ encoding: [0x42,0x0f,0xa1,0xf2]
//CHECK-V81aTHUMB: vqrdmlsh.s32 d0, d1, d2[0] @ encoding: [0xa1,0xef,0x42,0x0f]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s32 d0, d1, d2[0]
//CHECK-V8: ^
vqrdmlsh.s16 q0, q1, d2[0]
//CHECK-V81aARM: vqrdmlsh.s16 q0, q1, d2[0] @ encoding: [0x42,0x0f,0x92,0xf3]
//CHECK-V81aTHUMB: vqrdmlsh.s16 q0, q1, d2[0] @ encoding: [0x92,0xff,0x42,0x0f]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s16 q0, q1, d2[0]
//CHECK-V8: ^
vqrdmlsh.s32 q0, q1, d2[0]
//CHECK-V81aARM: vqrdmlsh.s32 q0, q1, d2[0] @ encoding: [0x42,0x0f,0xa2,0xf3]
//CHECK-V81aTHUMB: vqrdmlsh.s32 q0, q1, d2[0] @ encoding: [0xa2,0xff,0x42,0x0f]
-//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s32 q0, q1, d2[0]
//CHECK-V8: ^
+
+ setpan #0
+//CHECK-V81aTHUMB: setpan #0 @ encoding: [0x10,0xb6]
+//CHECK-V81aARM: setpan #0 @ encoding: [0x00,0x00,0x10,0xf1]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8: setpan #0
+//CHECK-V8: ^
+
+ setpan #1
+//CHECK-V81aTHUMB: setpan #1 @ encoding: [0x18,0xb6]
+//CHECK-V81aARM: setpan #1 @ encoding: [0x00,0x02,0x10,0xf1]
+//CHECK-V8: error: instruction requires: armv8.1a
+//CHECK-V8: setpan #1
+//CHECK-V8: ^
+ setpan
+ setpan #-1
+ setpan #2
+//CHECK-ERROR: error: too few operands for instruction
+//CHECK-ERROR: setpan
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR: setpan #-1
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR: setpan #2
+//CHECK-ERROR: ^
+
+ it eq
+ setpaneq #0
+//CHECK-THUMB-ERROR: error: instruction 'setpan' is not predicable, but condition code specified
+//CHECK-THUMB-ERROR: setpaneq #0
+//CHECK-THUMB-ERROR: ^
diff --git a/test/MC/ARM/eh-compact-pr0.s b/test/MC/ARM/eh-compact-pr0.s
index 1d825bf..9c0581a 100644
--- a/test/MC/ARM/eh-compact-pr0.s
+++ b/test/MC/ARM/eh-compact-pr0.s
@@ -1,5 +1,7 @@
@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
-@ RUN: | llvm-readobj -s -sd -sr | FileCheck %s
+@ RUN: | llvm-readobj -s -sd -sr > %t
+@ RUN: FileCheck %s < %t
+@ RUN: FileCheck --check-prefix=RELOC %s < %t
@ Check the compact pr0 model
@@ -63,10 +65,13 @@ func2:
@ another relocation entry for __aeabi_unwind_cpp_pr0, so that the linker
@ will keep __aeabi_unwind_cpp_pr0.
@-------------------------------------------------------------------------------
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0
-@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
-@ CHECK: ]
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.exidx.TEST1
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0
+@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
+@ RELOC: ]
+@ RELOC: }
@-------------------------------------------------------------------------------
@@ -92,13 +97,15 @@ func2:
@ CHECK: 0000: 00000000 B0808480 |........|
@ CHECK: )
@ CHECK: }
-@ CHECK: ]
@-------------------------------------------------------------------------------
@ The first word should be relocated to .TEST2 section. Besides, there is
@ another relocation entry for __aeabi_unwind_cpp_pr0, so that the linker
@ will keep __aeabi_unwind_cpp_pr0.
@-------------------------------------------------------------------------------
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 .TEST2 0x0
-@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
-@ CHECK: ]
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.exidx.TEST2
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 .TEST2 0x0
+@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
+@ RELOC: ]
+@ RELOC: }
diff --git a/test/MC/ARM/eh-directive-handlerdata.s b/test/MC/ARM/eh-directive-handlerdata.s
index 793d357..980a5f0 100644
--- a/test/MC/ARM/eh-directive-handlerdata.s
+++ b/test/MC/ARM/eh-directive-handlerdata.s
@@ -1,5 +1,7 @@
@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
-@ RUN: | llvm-readobj -s -sd -sr | FileCheck %s
+@ RUN: | llvm-readobj -s -sd -sr > %t
+@ RUN: FileCheck %s < %t
+@ RUN: FileCheck --check-prefix=RELOC %s < %t
@ Check the .handlerdata directive (without .personality directive)
@@ -43,11 +45,14 @@ func1:
@ We should see a relocation entry to __aeabi_unwind_cpp_pr0, so that the
@ linker can keep __aeabi_unwind_cpp_pr0.
@-------------------------------------------------------------------------------
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0
-@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
-@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
-@ CHECK: ]
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.exidx.TEST1
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0
+@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
+@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
+@ RELOC: ]
+@ RELOC: }
@@ -100,8 +105,11 @@ func2:
@ We should see a relocation entry to __aeabi_unwind_cpp_pr0, so that the
@ linker can keep __aeabi_unwind_cpp_pr0.
@-------------------------------------------------------------------------------
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 .TEST2 0x0
-@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0
-@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0
-@ CHECK: ]
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.exidx.TEST2
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 .TEST2 0x0
+@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0
+@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0
+@ RELOC: ]
+@ RELOC: }
diff --git a/test/MC/ARM/eh-directive-personality.s b/test/MC/ARM/eh-directive-personality.s
index f493722..84e62bd 100644
--- a/test/MC/ARM/eh-directive-personality.s
+++ b/test/MC/ARM/eh-directive-personality.s
@@ -1,5 +1,7 @@
@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
-@ RUN: | llvm-readobj -s -sd -sr | FileCheck %s
+@ RUN: | llvm-readobj -s -sd -sr > %t
+@ RUN: FileCheck %s < %t
+@ RUN: FileCheck --check-prefix=RELOC %s < %t
@ Check the .personality directive.
@@ -32,19 +34,28 @@ func1:
@ CHECK: 0000: 00000000 B0B0B000 |........|
@ CHECK: )
@ CHECK: }
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
-@ CHECK: ]
+
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.extab.TEST1
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
+@ RELOC: ]
+@ RELOC: }
+
@ CHECK: Section {
@ CHECK: Name: .ARM.exidx.TEST1
@ CHECK: SectionData (
@ CHECK: 0000: 00000000 00000000 |........|
@ CHECK: )
@ CHECK: }
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0
-@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
-@ CHECK: ]
+
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.exidx.TEST1
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0
+@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
+@ RELOC: ]
+@ RELOC: }
@-------------------------------------------------------------------------------
@@ -74,16 +85,25 @@ func2:
@ CHECK: 0000: 00000000 B0B0B000 |........|
@ CHECK: )
@ CHECK: }
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
-@ CHECK: ]
+
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.extab.TEST2
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
+@ RELOC: ]
+@ RELOC: }
+
@ CHECK: Section {
@ CHECK: Name: .ARM.exidx.TEST2
@ CHECK: SectionData (
@ CHECK: 0000: 00000000 00000000 |........|
@ CHECK: )
@ CHECK: }
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 .TEST2 0x0
-@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0
-@ CHECK: ]
+
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.exidx.TEST2
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 .TEST2 0x0
+@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0
+@ RELOC: ]
+@ RELOC: }
diff --git a/test/MC/ARM/eh-directive-personalityindex.s b/test/MC/ARM/eh-directive-personalityindex.s
index 5517227..6db9425 100644
--- a/test/MC/ARM/eh-directive-personalityindex.s
+++ b/test/MC/ARM/eh-directive-personalityindex.s
@@ -1,5 +1,7 @@
@ RUN: llvm-mc -triple armv7-linux-eabi -filetype obj -o - %s \
-@ RUN: | llvm-readobj -s -sd -sr | FileCheck %s
+@ RUN: | llvm-readobj -s -sd -sr > %t
+@ RUN: FileCheck %s < %t
+@ RUN: FileCheck --check-prefix=RELOC %s < %t
.syntax unified
.thumb
@@ -23,13 +25,13 @@ pr0:
@ CHECK: )
@ CHECK: }
-@ CHECK: Section {
-@ CHECK: Name: .rel.ARM.exidx.pr0
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 .pr0 0x0
-@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
-@ CHECK: ]
-@ CHECK: }
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.exidx.pr0
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 .pr0 0x0
+@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
+@ RELOC: ]
+@ RELOC: }
.section .pr0.nontrivial
@@ -52,13 +54,13 @@ pr0_nontrivial:
@ CHECK: )
@ CHECK: }
-@ CHECK: Section {
-@ CHECK: Name: .rel.ARM.exidx.pr0.nontrivial
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 .pr0.nontrivial 0x0
-@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
-@ CHECK: ]
-@ CHECK: }
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.exidx.pr0.nontrivial
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 .pr0.nontrivial 0x0
+@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0
+@ RELOC: ]
+@ RELOC: }
.section .pr1
@@ -85,14 +87,14 @@ pr1:
@ CHECK: )
@ CHECK: }
-@ CHECK: Section {
-@ CHECK: Name: .rel.ARM.exidx.pr1
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 .pr1 0x0
-@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0
-@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.pr1 0x0
-@ CHECK: ]
-@ CHECK: }
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.exidx.pr1
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 .pr1 0x0
+@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0
+@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.pr1 0x0
+@ RELOC: ]
+@ RELOC: }
.section .pr1.nontrivial
@@ -122,14 +124,14 @@ pr1_nontrivial:
@ CHECK: )
@ CHECK: }
-@ CHECK: Section {
-@ CHECK: Name: .rel.ARM.exidx.pr1.nontrivial
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 .pr1.nontrivial 0x0
-@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0
-@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.pr1.nontrivial 0x0
-@ CHECK: ]
-@ CHECK: }
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.exidx.pr1.nontrivial
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 .pr1.nontrivial 0x0
+@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0
+@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.pr1.nontrivial 0x0
+@ RELOC: ]
+@ RELOC: }
.section .pr2
@@ -156,14 +158,14 @@ pr2:
@ CHECK: )
@ CHECK: }
-@ CHECK: Section {
-@ CHECK: Name: .rel.ARM.exidx.pr2
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 .pr2 0x0
-@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr2 0x0
-@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.pr2 0x0
-@ CHECK: ]
-@ CHECK: }
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.exidx.pr2
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 .pr2 0x0
+@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr2 0x0
+@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.pr2 0x0
+@ RELOC: ]
+@ RELOC: }
.section .pr2.nontrivial
.type pr2_nontrivial,%function
@@ -191,12 +193,11 @@ pr2_nontrivial:
@ CHECK: )
@ CHECK: }
-@ CHECK: Section {
-@ CHECK: Name: .rel.ARM.exidx.pr2.nontrivial
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 .pr2.nontrivial 0x0
-@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr2 0x0
-@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.pr2.nontrivial 0x0
-@ CHECK: ]
-@ CHECK: }
-
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.exidx.pr2.nontrivial
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 .pr2.nontrivial 0x0
+@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr2 0x0
+@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.pr2.nontrivial 0x0
+@ RELOC: ]
+@ RELOC: }
diff --git a/test/MC/ARM/eh-directive-section-multiple-func.s b/test/MC/ARM/eh-directive-section-multiple-func.s
index 9f632b8..e7198a4 100644
--- a/test/MC/ARM/eh-directive-section-multiple-func.s
+++ b/test/MC/ARM/eh-directive-section-multiple-func.s
@@ -1,5 +1,7 @@
@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
-@ RUN: | llvm-readobj -s -sd -sr -t | FileCheck %s
+@ RUN: | llvm-readobj -s -sd -sr -t > %t
+@ RUN: FileCheck %s < %t
+@ RUN: FileCheck --check-prefix=RELOC %s < %t
@ Check whether the section is switched back properly.
@@ -69,10 +71,14 @@ func2:
@ CHECK: 0000: 00000000 B0B0B000 00000000 B0B0B000 |................|
@ CHECK: )
@ CHECK: }
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
-@ CHECK: 0x8 R_ARM_PREL31 __gxx_personality_v0 0x0
-@ CHECK: ]
+
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.extab.TEST1
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
+@ RELOC: 0x8 R_ARM_PREL31 __gxx_personality_v0 0x0
+@ RELOC: ]
+@ RELOC: }
@-------------------------------------------------------------------------------
@@ -89,18 +95,21 @@ func2:
@ CHECK: 0000: 00000000 00000000 04000000 08000000 |................|
@ CHECK: )
@ CHECK: }
-@ CHECK: ]
@-------------------------------------------------------------------------------
@ The first word of each entry should be relocated to .TEST1 section.
@ The second word of each entry should be relocated to
@ .ARM.extab.TESET1 section.
@-------------------------------------------------------------------------------
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0
-@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
-@ CHECK: 0x8 R_ARM_PREL31 .TEST1 0x0
-@ CHECK: 0xC R_ARM_PREL31 .ARM.extab.TEST1 0x0
-@ CHECK: ]
+
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.exidx.TEST1
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0
+@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
+@ RELOC: 0x8 R_ARM_PREL31 .TEST1 0x0
+@ RELOC: 0xC R_ARM_PREL31 .ARM.extab.TEST1 0x0
+@ RELOC: ]
+@ RELOC: }
@-------------------------------------------------------------------------------
diff --git a/test/MC/ARM/eh-directive-section.s b/test/MC/ARM/eh-directive-section.s
index 7c1f32e..671d106 100644
--- a/test/MC/ARM/eh-directive-section.s
+++ b/test/MC/ARM/eh-directive-section.s
@@ -1,5 +1,7 @@
@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
-@ RUN: | llvm-readobj -s -sd -sr -t | FileCheck %s
+@ RUN: | llvm-readobj -s -sd -sr -t > %t
+@ RUN: FileCheck %s < %t
+@ RUN: FileCheck --check-prefix=RELOC %s < %t
@ Check the combination of .section, .fnstart, and .fnend directives.
@@ -64,9 +66,13 @@ func2:
@ CHECK: 0000: 00000000 B0B0B000 |........|
@ CHECK: )
@ CHECK: }
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
-@ CHECK: ]
+
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.extab.TEST1
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
+@ RELOC: ]
+@ RELOC: }
@-------------------------------------------------------------------------------
@@ -89,10 +95,14 @@ func2:
@ CHECK: 0000: 00000000 00000000 |........|
@ CHECK: )
@ CHECK: }
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0
-@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
-@ CHECK: ]
+
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.exidx.TEST1
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0
+@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
+@ RELOC: ]
+@ RELOC: }
@-------------------------------------------------------------------------------
@@ -115,9 +125,13 @@ func2:
@ CHECK: 0000: 00000000 B0B0B000 |........|
@ CHECK: )
@ CHECK: }
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
-@ CHECK: ]
+
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.extabTEST2
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
+@ RELOC: ]
+@ RELOC: }
@-------------------------------------------------------------------------------
@@ -140,11 +154,14 @@ func2:
@ CHECK: 0000: 00000000 00000000 |........|
@ CHECK: )
@ CHECK: }
-@ CHECK: ]
-@ CHECK: Relocations [
-@ CHECK: 0x0 R_ARM_PREL31 TEST2 0x0
-@ CHECK: 0x4 R_ARM_PREL31 .ARM.extabTEST2 0x0
-@ CHECK: ]
+
+@ RELOC: Section {
+@ RELOC: Name: .rel.ARM.exidxTEST2
+@ RELOC: Relocations [
+@ RELOC: 0x0 R_ARM_PREL31 TEST2 0x0
+@ RELOC: 0x4 R_ARM_PREL31 .ARM.extabTEST2 0x0
+@ RELOC: ]
+@ RELOC: }
diff --git a/test/MC/ARM/eh-link.s b/test/MC/ARM/eh-link.s
new file mode 100644
index 0000000..0c44c0e
--- /dev/null
+++ b/test/MC/ARM/eh-link.s
@@ -0,0 +1,90 @@
+@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
+@ RUN: | llvm-readobj -s | FileCheck %s
+
+@ Test that the ARM_EXIDX sections point (Link) to the corresponding text
+@ sections.
+
+@ FIXME: The section numbers are not important. If llvm-readobj printed the
+@ name first we could use a FileCheck variable.
+
+@ CHECK: Section {
+@ CHECK: Index: 6
+@ CHECK-NEXT: Name: .text
+@ CHECK-NEXT: Type: SHT_PROGBITS
+@ CHECK-NEXT: Flags [
+@ CHECK-NEXT: SHF_ALLOC
+@ CHECK-NEXT: SHF_EXECINSTR
+@ CHECK-NEXT: SHF_GROUP
+@ CHECK-NEXT: ]
+@ CHECK-NEXT: Address: 0x0
+@ CHECK-NEXT: Offset: 0x54
+@ CHECK-NEXT: Size: 4
+@ CHECK-NEXT: Link: 0
+@ CHECK-NEXT: Info: 0
+@ CHECK-NEXT: AddressAlignment: 1
+@ CHECK-NEXT: EntrySize: 0
+@ CHECK-NEXT: }
+@ CHECK-NEXT: Section {
+@ CHECK-NEXT: Index: 7
+@ CHECK-NEXT: Name: .ARM.exidx
+@ CHECK-NEXT: Type: SHT_ARM_EXIDX
+@ CHECK-NEXT: Flags [
+@ CHECK-NEXT: SHF_ALLOC
+@ CHECK-NEXT: SHF_GROUP
+@ CHECK-NEXT: SHF_LINK_ORDER
+@ CHECK-NEXT: ]
+@ CHECK-NEXT: Address: 0x0
+@ CHECK-NEXT: Offset: 0x58
+@ CHECK-NEXT: Size: 8
+@ CHECK-NEXT: Link: 6
+@ CHECK-NEXT: Info: 0
+@ CHECK-NEXT: AddressAlignment: 4
+@ CHECK-NEXT: EntrySize: 0
+@ CHECK-NEXT: }
+
+@ CHECK: Section {
+@ CHECK: Index: 9
+@ CHECK-NEXT: Name: .text
+@ CHECK-NEXT: Type: SHT_PROGBITS
+@ CHECK-NEXT: Flags [
+@ CHECK-NEXT: SHF_ALLOC
+@ CHECK-NEXT: SHF_EXECINSTR
+@ CHECK-NEXT: SHF_GROUP
+@ CHECK-NEXT: ]
+@ CHECK-NEXT: Address: 0x0
+@ CHECK-NEXT: Offset:
+@ CHECK-NEXT: Size: 4
+@ CHECK-NEXT: Link: 0
+@ CHECK-NEXT: Info: 0
+@ CHECK-NEXT: AddressAlignment: 1
+@ CHECK-NEXT: EntrySize: 0
+@ CHECK-NEXT: }
+@ CHECK-NEXT: Section {
+@ CHECK-NEXT: Index: 10
+@ CHECK-NEXT: Name: .ARM.exidx
+@ CHECK-NEXT: Type: SHT_ARM_EXIDX
+@ CHECK-NEXT: Flags [
+@ CHECK-NEXT: SHF_ALLOC
+@ CHECK-NEXT: SHF_GROUP
+@ CHECK-NEXT: SHF_LINK_ORDER
+@ CHECK-NEXT: ]
+@ CHECK-NEXT: Address: 0x0
+@ CHECK-NEXT: Offset:
+@ CHECK-NEXT: Size: 8
+@ CHECK-NEXT: Link: 9
+@ CHECK-NEXT: Info: 0
+@ CHECK-NEXT: AddressAlignment: 4
+@ CHECK-NEXT: EntrySize: 0
+@ CHECK-NEXT: }
+
+ .section .text,"axG",%progbits,f,comdat
+f:
+ .fnstart
+ mov pc, lr
+ .fnend
+
+ .section .text,"axG",%progbits,g,comdat
+g:
+ .fnstart
+ mov pc, lr
+ .fnend
diff --git a/test/MC/ARM/elf-movt.s b/test/MC/ARM/elf-movt.s
index 0080db4..1ff5da5 100644
--- a/test/MC/ARM/elf-movt.s
+++ b/test/MC/ARM/elf-movt.s
@@ -35,14 +35,14 @@ barf: @ @barf
@ OBJ-NEXT: 0000: F00F0FE3 F40F4FE3
@ OBJ-NEXT: )
@ OBJ-NEXT: }
-@ OBJ-NEXT: Section {
-@ OBJ-NEXT: Index: 2
-@ OBJ-NEXT: Name: .rel.text (1)
+@ OBJ: Section {
+@ OBJ: Index:
+@ OBJ: Name: .rel.text
@ OBJ-NEXT: Type: SHT_REL (0x9)
@ OBJ-NEXT: Flags [ (0x0)
@ OBJ-NEXT: ]
@ OBJ-NEXT: Address: 0x0
-@ OBJ-NEXT: Offset: 0x22C
+@ OBJ-NEXT: Offset:
@ OBJ-NEXT: Size: 16
@ OBJ-NEXT: Link: 6
@ OBJ-NEXT: Info: 1
diff --git a/test/MC/ARM/elf-reloc-01.ll b/test/MC/ARM/elf-reloc-01.ll
index 28be85b..7f3cc18 100644
--- a/test/MC/ARM/elf-reloc-01.ll
+++ b/test/MC/ARM/elf-reloc-01.ll
@@ -61,7 +61,7 @@ bb3: ; preds = %bb, %entry
declare void @exit(i32) noreturn nounwind
; OBJ: Relocations [
-; OBJ: Section (2) .rel.text {
+; OBJ: Section {{.*}} .rel.text {
; OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC _MergedGlobals
; OBJ: }
; OBJ: ]
diff --git a/test/MC/ARM/elf-reloc-02.ll b/test/MC/ARM/elf-reloc-02.ll
index 8b4feba..0ffb623 100644
--- a/test/MC/ARM/elf-reloc-02.ll
+++ b/test/MC/ARM/elf-reloc-02.ll
@@ -29,10 +29,10 @@ declare void @myhextochar(i32 %n, i8* nocapture %buffer) nounwind
define i32 @main() nounwind {
entry:
- %0 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 6) nounwind
- %1 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str1, i32 0, i32 0), i32 7) nounwind
- %2 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str2, i32 0, i32 0), i32 12) nounwind
- %3 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str3, i32 0, i32 0), i32 6) nounwind
+ %0 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 6) nounwind
+ %1 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str1, i32 0, i32 0), i32 7) nounwind
+ %2 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str2, i32 0, i32 0), i32 12) nounwind
+ %3 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str3, i32 0, i32 0), i32 6) nounwind
tail call void @exit(i32 55) noreturn nounwind
unreachable
}
@@ -42,7 +42,7 @@ declare i32 @write(...)
declare void @exit(i32) noreturn nounwind
;; OBJ: Relocations [
-;; OBJ: Section (2) .rel.text {
+;; OBJ: Section {{.*}} .rel.text {
;; OBJ-NEXT: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC .L.str
;; OBJ: }
;; OBJ: ]
diff --git a/test/MC/ARM/elf-reloc-03.ll b/test/MC/ARM/elf-reloc-03.ll
index a0fdc3e..4beb91f 100644
--- a/test/MC/ARM/elf-reloc-03.ll
+++ b/test/MC/ARM/elf-reloc-03.ll
@@ -81,7 +81,7 @@ entry:
%0 = load i32, i32* @startval, align 4
%1 = getelementptr inbounds [10 x i32 (...)*], [10 x i32 (...)*]* @vtable, i32 0, i32 %0
%2 = load i32 (...)*, i32 (...)** %1, align 4
- %3 = tail call i32 (...)* %2() nounwind
+ %3 = tail call i32 (...) %2() nounwind
tail call void @exit(i32 %3) noreturn nounwind
unreachable
}
@@ -89,7 +89,7 @@ entry:
declare void @exit(i32) noreturn nounwind
;; OBJ: Relocations [
-;; OBJ: Section (2) .rel.text {
+;; OBJ: Section {{.*}} .rel.text {
;; OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC vtable
;; OBJ: }
;; OBJ: ]
diff --git a/test/MC/ARM/elf-reloc-condcall.s b/test/MC/ARM/elf-reloc-condcall.s
index a0402bd..c4818b8 100644
--- a/test/MC/ARM/elf-reloc-condcall.s
+++ b/test/MC/ARM/elf-reloc-condcall.s
@@ -8,7 +8,7 @@
b some_label
// OBJ: Relocations [
-// OBJ-NEXT: Section (2) .rel.text {
+// OBJ-NEXT: Section {{.*}} .rel.text {
// OBJ-NEXT: 0x0 R_ARM_JUMP24 some_label 0x0
// OBJ-NEXT: 0x4 R_ARM_CALL some_label 0x0
// OBJ-NEXT: 0x8 R_ARM_CALL some_label 0x0
diff --git a/test/MC/ARM/elf-thumbfunc-reloc.ll b/test/MC/ARM/elf-thumbfunc-reloc.ll
index f502739..f35971a 100644
--- a/test/MC/ARM/elf-thumbfunc-reloc.ll
+++ b/test/MC/ARM/elf-thumbfunc-reloc.ll
@@ -29,10 +29,10 @@ entry:
; CHECK: ]
; CHECK: Relocations [
-; CHECK-NEXT: Section (2) .rel.text {
+; CHECK-NEXT: Section {{.*}} .rel.text {
; CHECK-NEXT: 0x8 R_ARM_THM_CALL foo 0x0
; CHECK-NEXT: }
-; CHECK-NEXT: Section (7) .rel.ARM.exidx {
+; CHECK-NEXT: Section {{.*}} .rel.ARM.exidx {
; CHECK-NEXT: 0x0 R_ARM_PREL31 .text 0x0
; CHECK-NEXT: 0x8 R_ARM_PREL31 .text 0x0
; CHECK-NEXT: }
diff --git a/test/MC/ARM/elf-thumbfunc-reloc.s b/test/MC/ARM/elf-thumbfunc-reloc.s
index ea7d507..dd380c3 100644
--- a/test/MC/ARM/elf-thumbfunc-reloc.s
+++ b/test/MC/ARM/elf-thumbfunc-reloc.s
@@ -22,7 +22,7 @@ ptr:
@@ make sure an R_ARM_THM_CALL relocation is generated for the call to g
@CHECK: Relocations [
-@CHECK-NEXT: Section (2) .rel.text {
+@CHECK-NEXT: Section {{.*}} .rel.text {
@CHECK-NEXT: 0x4 R_ARM_THM_CALL g 0x0
@CHECK-NEXT: }
diff --git a/test/MC/ARM/thumb1-relax-adr.s b/test/MC/ARM/thumb1-relax-adr.s
new file mode 100644
index 0000000..80b93ec
--- /dev/null
+++ b/test/MC/ARM/thumb1-relax-adr.s
@@ -0,0 +1,9 @@
+@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: not llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+
+ .global func1
+_func1:
+ adr r0, _func2
+@ CHECK-ERROR: unsupported relocation on symbol
+
diff --git a/test/MC/ARM/thumb1-relax-bcc.s b/test/MC/ARM/thumb1-relax-bcc.s
new file mode 100644
index 0000000..02fde2e
--- /dev/null
+++ b/test/MC/ARM/thumb1-relax-bcc.s
@@ -0,0 +1,12 @@
+@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o %t %s
+@ RUN: llvm-objdump -d -r -triple thumbv7m-none-eabi %t | FileCheck --check-prefix=CHECK-ELF %s
+
+ .global func1
+_func1:
+ bne _func2
+@ CHECK-ERROR: unsupported relocation on symbol
+
+@ CHECK-ELF: 7f f4 fe af bne.w #-4
+@ CHECK-ELF-NEXT: R_ARM_THM_JUMP24 _func2
diff --git a/test/MC/ARM/thumb1-relax-br.s b/test/MC/ARM/thumb1-relax-br.s
new file mode 100644
index 0000000..92a8275
--- /dev/null
+++ b/test/MC/ARM/thumb1-relax-br.s
@@ -0,0 +1,19 @@
+@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: llvm-mc -triple thumbv7m-none-macho -filetype=obj -o %t %s
+@ RUN: llvm-objdump -d -r -triple thumbv7m-none-macho %t | FileCheck --check-prefix=CHECK-MACHO %s
+@ RUN: llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o %t %s
+@ RUN: llvm-objdump -d -r -triple thumbv7m-none-eabi %t | FileCheck --check-prefix=CHECK-ELF %s
+
+ .global func1
+_func1:
+ @ There is no MachO relocation for Thumb1's unconditional branch, so
+ @ this is unrepresentable. FIXME: I think ELF could represent this.
+ b _func2
+
+@ CHECK-ERROR: unsupported relocation on symbol
+
+@ CHECK-MACHO: ff f7 fe bf b.w #-4
+@ CHECK-MACHO-NEXT: ARM_THUMB_RELOC_BR22
+
+@ CHECK-ELF: ff f7 fe bf b.w #-4
+@ CHECK-ELF-NEXT: R_ARM_THM_JUMP24 _func2
diff --git a/test/MC/ARM/thumb1-relax-ldrlit.s b/test/MC/ARM/thumb1-relax-ldrlit.s
new file mode 100644
index 0000000..96c5aa0
--- /dev/null
+++ b/test/MC/ARM/thumb1-relax-ldrlit.s
@@ -0,0 +1,9 @@
+@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: not llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+
+ .global func1
+_func1:
+ ldr r0, _func2
+@ CHECK-ERROR: unsupported relocation on symbol
+
diff --git a/test/MC/ARM/thumb2-bxj-v8.s b/test/MC/ARM/thumb2-bxj-v8.s
new file mode 100644
index 0000000..4420b6f
--- /dev/null
+++ b/test/MC/ARM/thumb2-bxj-v8.s
@@ -0,0 +1,11 @@
+@ RUN: not llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
+@ RUN: not llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
+@ RUN: not llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
+@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=ARM_MODE
+@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s 2>&1 | FileCheck %s
+
+bxj r13
+
+@ CHECK: bxj sp @ encoding: [0xcd,0xf3,0x00,0x8f]
+@ UNDEF: error: r13 (SP) is an unpredictable operand to BXJ
+@ ARM_MODE: error: instruction requires: arm-mode
diff --git a/test/MC/ARM/thumb2-bxj.s b/test/MC/ARM/thumb2-bxj.s
index e60d1a4..7687939 100644
--- a/test/MC/ARM/thumb2-bxj.s
+++ b/test/MC/ARM/thumb2-bxj.s
@@ -1,8 +1,8 @@
@ RUN: llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s | FileCheck %s
@ RUN: llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s | FileCheck %s
@ RUN: llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s | FileCheck %s
@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
-@ RUN: not llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
bxj r2
generated by cgit v1.1 at 2024-06-12 15:24:34 +0000