diff options
Diffstat (limited to 'test/MC/ARM')
28 files changed, 1424 insertions, 93 deletions
diff --git a/test/MC/ARM/Windows/invalid-relocation.s b/test/MC/ARM/Windows/invalid-relocation.s new file mode 100644 index 0000000..4f4c598 --- /dev/null +++ b/test/MC/ARM/Windows/invalid-relocation.s @@ -0,0 +1,14 @@ +# RUN: not llvm-mc -triple thumbv7-windows -filetype obj -o /dev/null 2>&1 %s \ +# RUN: | FileCheck %s + + .def invalid_relocation + .type 32 + .scl 2 + .endef + .global invalid_relocation + .thumb_func +invalid_relocation: + adr r0, invalid_relocation+1 + +# CHECK: LLVM ERROR: unsupported relocation type: fixup_t2_adr_pcrel_12 + diff --git a/test/MC/ARM/arm-elf-relocation-diagnostics.s b/test/MC/ARM/arm-elf-relocation-diagnostics.s new file mode 100644 index 0000000..5fe903f --- /dev/null +++ b/test/MC/ARM/arm-elf-relocation-diagnostics.s @@ -0,0 +1,27 @@ +@ RUN: not llvm-mc -triple armv7-eabi -filetype obj -o - %s 2>&1 \ +@ RUN: | FileCheck %s +@ RUN: not llvm-mc -triple thumbv7-eabi -filetype obj -o - %s 2>&1 \ +@ RUN: | FileCheck %s + + .byte target(sbrel) +@ CHECK: error: relocated expression must be 32-bit +@ CHECK: .byte target(sbrel) +@ CHECK: ^ + +@ TODO: enable these negative test cases +@ .hword target(sbrel) +@ @ CHECK-SBREL-HWORD: error: relocated expression must be 32-bit +@ @ CHECK-SBREL-HWORD: .hword target(sbrel) +@ @ CHECK-SBREL-HWORD: ^ +@ +@ .short target(sbrel) +@ @ CHECK-SBREL-SHORT: error: relocated expression must be 32-bit +@ @ CHECK-SBREL-SHORT: .short target(sbrel) +@ @ CHECK-SBREL-SHORT: ^ +@ +@ .quad target(sbrel) +@ @ CHECK-SBREL-SHORT: error: relocated expression must be 32-bit +@ @ CHECK-SBREL-SHORT: .quad target(sbrel) +@ @ CHECK-SBREL-SHORT: ^ + + diff --git a/test/MC/ARM/arm-elf-relocations.s b/test/MC/ARM/arm-elf-relocations.s new file mode 100644 index 0000000..4059591 --- /dev/null +++ b/test/MC/ARM/arm-elf-relocations.s @@ -0,0 +1,37 @@ +@ RUN: llvm-mc -triple armv7-eabi -filetype obj -o - %s | llvm-readobj -r - \ +@ RUN: | FileCheck %s +@ RUN: llvm-mc -triple thumbv7-eabi -filetype obj -o - %s | llvm-readobj -r - \ +@ RUN: | FileCheck %s + + .syntax unified + + .section .text.r_arm_abs8 + + .byte abs8_0 -128 + .byte abs8_1 +255 + +@ CHECK: Section {{.*}} .rel.text.r_arm_abs8 { +@ CHECK: 0x0 R_ARM_ABS8 abs8_0 0x0 +@ CHECK: 0x1 R_ARM_ABS8 abs8_1 0x0 +@ CHECK: } + + .section .text.r_arm_abs16 + + .short abs16_0 -32768 + .short abs16_1 +65535 + +@ CHECK: Section {{.*}} .rel.text.r_arm_abs16 { +@ CHECK: 0x0 R_ARM_ABS16 abs16_0 0x0 +@ CHECK: 0x2 R_ARM_ABS16 abs16_1 0x0 +@ CHECK: } + + .section .text.r_arm_sbrel32 + + .word target(sbrel) + .word target(SBREL) + +@ CHECK: Section {{.*}} .rel.text.r_arm_sbrel32 { +@ CHECK: 0x0 R_ARM_SBREL32 target 0x0 +@ CHECK: 0x4 R_ARM_SBREL32 target 0x0 +@ CHECK: } + diff --git a/test/MC/ARM/arm-load-store-multiple-deprecated.s b/test/MC/ARM/arm-load-store-multiple-deprecated.s new file mode 100644 index 0000000..9354822 --- /dev/null +++ b/test/MC/ARM/arm-load-store-multiple-deprecated.s @@ -0,0 +1,222 @@ +@ RUN: llvm-mc -triple armv6t2-linux-eabi -filetype asm -o - %s 2>&1 \ +@ RUN: | FileCheck %s + +@ RUN: not llvm-mc -triple armv7-linux-eabi -filetype asm -o - %s 2>&1 \ +@ RUN: | FileCheck %s -check-prefix CHECK -check-prefix CHECK-V7 + + .syntax unified + .arm + + .global stm + .type stm,%function +stm: + stm sp!, {r0, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stm sp!, {r0, pc} +@ CHECK: ^ + stm r0!, {r0, sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stm r0!, {r0, sp} +@ CHECK: ^ + stm r1!, {r0, sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stm r1!, {r0, sp, pc} +@ CHECK: ^ + stm r2!, {sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stm r2!, {sp, pc} +@ CHECK: ^ + stm sp!, {pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stm sp!, {pc} +@ CHECK: ^ + stm r0!, {sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stm r0!, {sp} +@ CHECK: ^ + + .global stmda + .type stmda,%function +stmda: + stmda sp!, {r0, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmda sp!, {r0, pc} +@ CHECK: ^ + stmda r0!, {r0, sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmda r0!, {r0, sp} +@ CHECK: ^ + stmda r1!, {r0, sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmda r1!, {r0, sp, pc} +@ CHECK: ^ + stmda r2!, {sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmda r2!, {sp, pc} +@ CHECK: ^ + stmda sp!, {pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmda sp!, {pc} +@ CHECK: ^ + stmda r0!, {sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmda r0!, {sp} +@ CHECK: ^ + + .global stmdb + .type stmdb,%function +stmdb: + stmdb sp!, {r0, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmdb sp!, {r0, pc} +@ CHECK: ^ + stmdb r0!, {r0, sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmdb r0!, {r0, sp} +@ CHECK: ^ + stmdb r1!, {r0, sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmdb r1!, {r0, sp, pc} +@ CHECK: ^ + stmdb r2!, {sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmdb r2!, {sp, pc} +@ CHECK: ^ + stmdb sp!, {pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmdb sp!, {pc} +@ CHECK: ^ + stmdb r0!, {sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmdb r0!, {sp} +@ CHECK: ^ + + .global stmib + .type stmib,%function +stmib: + stmib sp!, {r0, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmib sp!, {r0, pc} +@ CHECK: ^ + stmib r0!, {r0, sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmib r0!, {r0, sp} +@ CHECK: ^ + stmib r1!, {r0, sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmib r1!, {r0, sp, pc} +@ CHECK: ^ + stmib r2!, {sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmib r2!, {sp, pc} +@ CHECK: ^ + stmib sp!, {pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmib sp!, {pc} +@ CHECK: ^ + stmib r0!, {sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmib r0!, {sp} +@ CHECK: ^ + + + .global push + .type push,%function +push: + push {r0, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: push {r0, pc} +@ CHECK: ^ + push {r0, sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: push {r0, sp} +@ CHECK: ^ + push {r0, sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: push {r0, sp, pc} +@ CHECK: ^ + push {sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: push {sp, pc} +@ CHECK: ^ + push {pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: push {pc} +@ CHECK: ^ + push {sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: push {sp} +@ CHECK: ^ + + .global ldm + .type ldm,%function +ldm: + ldm r0!, {r1, sp} +@ CHECK: warning: use of SP in the list is deprecated + ldm r0!, {sp} +@ CHECK: warning: use of SP in the list is deprecated + ldm r0!, {r1, lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + ldm r0!, {lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + + .global ldmda + .type ldmda,%function +ldmda: + ldmda r0!, {r1, sp} +@ CHECK: warning: use of SP in the list is deprecated + ldmda r0!, {sp} +@ CHECK: warning: use of SP in the list is deprecated + ldmda r0!, {r1, lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + ldmda r0!, {lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + + .global ldmdb + .type ldmdb,%function +ldmdb: + ldmdb r0!, {r1, sp} +@ CHECK: warning: use of SP in the list is deprecated + ldmdb r0!, {sp} +@ CHECK: warning: use of SP in the list is deprecated + ldmdb r0!, {r1, lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + ldmdb r0!, {lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + + .global ldmib + .type ldmib,%function +ldmib: + ldmib r0!, {r1, sp} +@ CHECK: warning: use of SP in the list is deprecated + ldmib r0!, {sp} +@ CHECK: warning: use of SP in the list is deprecated + ldmib r0!, {r1, lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + ldmib r0!, {lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + + .global pop + .type pop,%function +pop: + pop {r0, sp} +@ CHECK: warning: use of SP in the list is deprecated +@ CHECK-V7: error: writeback register not allowed in register list + pop {sp} +@ CHECK: warning: use of SP in the list is deprecated +@ CHECK-V7: error: writeback register not allowed in register list + pop {r0, lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + pop {lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + + .global valid + .type valid,%function +valid: + stmdaeq r0, {r0} +@ CHECK: stmdaeq r0, {r0} + ldmdaeq r0, {r0} +@ CHECK: ldmdaeq r0, {r0} + pop {r0, pc} +@ CHECK: pop {r0, pc} + diff --git a/test/MC/ARM/arm-thumb-cpus.s b/test/MC/ARM/arm-thumb-cpus.s index 9005c7f..459b5c5 100644 --- a/test/MC/ARM/arm-thumb-cpus.s +++ b/test/MC/ARM/arm-thumb-cpus.s @@ -16,6 +16,9 @@ @ RUN: not llvm-mc -show-encoding -triple=armv6m-eabi < %s 2>&1 \ @ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY +@ RUN: not llvm-mc -show-encoding -triple=armv6sm-eabi < %s 2>&1 \ +@ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY + @ Make sure correct diagnostics are given for CPUs without support for @ one or other of the execution states. .thumb diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index e5e9617..a1f13b7 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -16,6 +16,15 @@ _func: @ ADC (immediate) @------------------------------------------------------------------------------ adc r1, r2, #0xf + adc r1, r2, $0xf + adc r1, r2, 0xf + adc r7, r8, #(0xff << 16) + adc r7, r8, #-2147483638 + adc r7, r8, #42, #2 + adc r7, r8, #40, #2 + adc r7, r8, $40, $2 + adc r7, r8, 40, 2 + adc r7, r8, (2 * 20), (1 << 1) adc r1, r2, #0xf0 adc r1, r2, #0xf00 adc r1, r2, #0xf000 @@ -25,20 +34,30 @@ _func: adc r1, r2, #0xf0000000 adc r1, r2, #0xf000000f adcs r1, r2, #0xf00 + adcs r7, r8, #40, #2 adcseq r1, r2, #0xf00 adceq r1, r2, #0xf00 @ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2] +@ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2] +@ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2] +@ CHECK: adc r7, r8, #16711680 @ encoding: [0xff,0x78,0xa8,0xe2] +@ CHECK: adc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xa8,0xe2] +@ CHECK: adc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xa8,0xe2] +@ CHECK: adc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xa8,0xe2] +@ CHECK: adc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xa8,0xe2] +@ CHECK: adc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xa8,0xe2] +@ CHECK: adc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xa8,0xe2] @ CHECK: adc r1, r2, #240 @ encoding: [0xf0,0x10,0xa2,0xe2] @ CHECK: adc r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0xe2] @ CHECK: adc r1, r2, #61440 @ encoding: [0x0f,0x1a,0xa2,0xe2] @ CHECK: adc r1, r2, #983040 @ encoding: [0x0f,0x18,0xa2,0xe2] @ CHECK: adc r1, r2, #15728640 @ encoding: [0x0f,0x16,0xa2,0xe2] @ CHECK: adc r1, r2, #251658240 @ encoding: [0x0f,0x14,0xa2,0xe2] -@ CHECK: adc r1, r2, #4026531840 @ encoding: [0x0f,0x12,0xa2,0xe2] -@ CHECK: adc r1, r2, #4026531855 @ encoding: [0xff,0x12,0xa2,0xe2] - +@ CHECK: adc r1, r2, #-268435456 @ encoding: [0x0f,0x12,0xa2,0xe2] +@ CHECK: adc r1, r2, #-268435441 @ encoding: [0xff,0x12,0xa2,0xe2] @ CHECK: adcs r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0xe2] +@ CHECK: adcs r7, r8, #40, #2 @ encoding: [0x28,0x71,0xb8,0xe2] @ CHECK: adcseq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0x02] @ CHECK: adceq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0x02] @@ -162,6 +181,16 @@ Lforward: @ ADD @------------------------------------------------------------------------------ add r4, r5, #0xf000 + add r4, r5, $0xf000 + add r4, r5, 0xf000 + add r4, r5, -0xf000 + add r7, r8, #(0xff << 16) + add r7, r8, #-2147483638 + add r7, r8, #42, #2 + add r7, r8, #40, #2 + add r7, r8, $40, $2 + add r7, r8, 40, 2 + add r7, r8, (2 * 20), (1 << 1) add r4, r5, r6 add r4, r5, r6, lsl #5 add r4, r5, r6, lsr #5 @@ -177,6 +206,16 @@ Lforward: @ destination register is optional add r5, #0xf000 + add r5, $0xf000 + add r5, 0xf000 + add r5, -0xf000 + add r7, #(0xff << 16) + add r7, #-2147483638 + add r7, #42, #2 + add r7, #40, #2 + add r7, $40, $2 + add r7, 40, 2 + add r7, (2 * 20), (1 << 1) add r4, r5 add r4, r5, lsl #5 add r4, r5, lsr #5 @@ -189,11 +228,25 @@ Lforward: add r6, r7, ror r9 add r4, r5, rrx - add r0, #-4 - add r4, r5, #-21 + add r0, #-4 + add r4, r5, #-21 add r0, pc, #0xc0000000 + addseq r0,pc,#0xc0000000 + + + add r0, pc, #(Lback - .) @ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2] +@ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2] +@ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2] +@ CHECK: sub r4, r5, #61440 @ encoding: [0x0f,0x4a,0x45,0xe2] +@ CHECK: add r7, r8, #16711680 @ encoding: [0xff,0x78,0x88,0xe2] +@ CHECK: add r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe2] +@ CHECK: add r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe2] +@ CHECK: add r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe2] +@ CHECK: add r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe2] +@ CHECK: add r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe2] +@ CHECK: add r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe2] @ CHECK: add r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe0] @ CHECK: add r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe0] @ CHECK: add r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe0] @@ -208,6 +261,16 @@ Lforward: @ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0] @ CHECK: add r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe2] +@ CHECK: add r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe2] +@ CHECK: add r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe2] +@ CHECK: sub r5, r5, #61440 @ encoding: [0x0f,0x5a,0x45,0xe2] +@ CHECK: add r7, r7, #16711680 @ encoding: [0xff,0x78,0x87,0xe2] +@ CHECK: add r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x87,0xe2] +@ CHECK: add r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x87,0xe2] +@ CHECK: add r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe2] +@ CHECK: add r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe2] +@ CHECK: add r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe2] +@ CHECK: add r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe2] @ CHECK: add r4, r4, r5 @ encoding: [0x05,0x40,0x84,0xe0] @ CHECK: add r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x84,0xe0] @ CHECK: add r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe0] @@ -222,7 +285,12 @@ Lforward: @ CHECK: sub r0, r0, #4 @ encoding: [0x04,0x00,0x40,0xe2] @ CHECK: sub r4, r5, #21 @ encoding: [0x15,0x40,0x45,0xe2] -@ CHECK: adr r0, #-1073741824 @ encoding: [0x03,0x01,0x8f,0xe2] +@ CHECK: adr r0, #-1073741824 @ encoding: [0x03,0x01,0x8f,0xe2] +@ CHECK: addseq r0, pc, #-1073741824 @ encoding: [0x03,0x01,0x9f,0x02] +@ CHECK: Ltmp0: +@ CHECK-NEXT: Ltmp1: +@ CHECK-NEXT: adr r0, (Ltmp1+8)+(Lback-Ltmp0) @ encoding: [A,A,0x0f'A',0xe2'A'] +@ CHECK-NEXT: @ fixup A - offset: 0, value: (Ltmp1+8)+(Lback-Ltmp0), kind: fixup_arm_adr_pcrel_12 @ Test right shift by 32, which is encoded as 0 add r3, r1, r2, lsr #32 @@ -231,9 +299,44 @@ Lforward: @ CHECK: add r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x81,0xe0] @------------------------------------------------------------------------------ +@ ADDS +@------------------------------------------------------------------------------ + adds r7, r8, #16711680 + adds r7, r8, $16711680 + adds r7, r8, 16711680 + adds r7, r8, #(0xff << 16) + adds r7, r8, #-2147483638 + adds r7, r8, #42, #2 + adds r7, r8, #40, #2 + adds r7, r8, $40, $2 + adds r7, r8, 40, 2 + adds r7, r8, (2 * 20), (1 << 1) + +@ CHECK: adds r7, r8, #16711680 @ encoding: [0xff,0x78,0x98,0xe2] +@ CHECK: adds r7, r8, #16711680 @ encoding: [0xff,0x78,0x98,0xe2] +@ CHECK: adds r7, r8, #16711680 @ encoding: [0xff,0x78,0x98,0xe2] +@ CHECK: adds r7, r8, #16711680 @ encoding: [0xff,0x78,0x98,0xe2] +@ CHECK: adds r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x98,0xe2] +@ CHECK: adds r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x98,0xe2] +@ CHECK: adds r7, r8, #40, #2 @ encoding: [0x28,0x71,0x98,0xe2] +@ CHECK: adds r7, r8, #40, #2 @ encoding: [0x28,0x71,0x98,0xe2] +@ CHECK: adds r7, r8, #40, #2 @ encoding: [0x28,0x71,0x98,0xe2] +@ CHECK: adds r7, r8, #40, #2 @ encoding: [0x28,0x71,0x98,0xe2] + +@------------------------------------------------------------------------------ @ AND @------------------------------------------------------------------------------ and r10, r1, #0xf + and r10, r1, $0xf + and r10, r1, 0xf + and r10, r1, -0xf + and r7, r8, #(0xff << 16) + and r7, r8, #-2147483638 + and r7, r8, #42, #2 + and r7, r8, #40, #2 + and r7, r8, $40, $2 + and r7, r8, 40, 2 + and r7, r8, (2 * 20), (1 << 1) and r10, r1, r6 and r10, r1, r6, lsl #10 and r10, r1, r6, lsr #10 @@ -249,6 +352,16 @@ Lforward: @ destination register is optional and r1, #0xf + and r1, $0xf + and r1, 0xf + and r1, -0xf + and r7, #(0xff << 16) + and r7, #-2147483638 + and r7, #42, #2 + and r7, #40, #2 + and r7, $40, $2 + and r7, 40, 2 + and r7, (2 * 20), (1 << 1) and r10, r1 and r10, r1, lsl #10 and r10, r1, lsr #10 @@ -262,6 +375,16 @@ Lforward: and r10, r1, rrx @ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2] +@ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2] +@ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2] +@ CHECK: bic r10, r1, #14 @ encoding: [0x0e,0xa0,0xc1,0xe3] +@ CHECK: and r7, r8, #16711680 @ encoding: [0xff,0x78,0x08,0xe2] +@ CHECK: and r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x08,0xe2] +@ CHECK: and r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x08,0xe2] +@ CHECK: and r7, r8, #40, #2 @ encoding: [0x28,0x71,0x08,0xe2] +@ CHECK: and r7, r8, #40, #2 @ encoding: [0x28,0x71,0x08,0xe2] +@ CHECK: and r7, r8, #40, #2 @ encoding: [0x28,0x71,0x08,0xe2] +@ CHECK: and r7, r8, #40, #2 @ encoding: [0x28,0x71,0x08,0xe2] @ CHECK: and r10, r1, r6 @ encoding: [0x06,0xa0,0x01,0xe0] @ CHECK: and r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0x01,0xe0] @ CHECK: and r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0x01,0xe0] @@ -276,6 +399,16 @@ Lforward: @ CHECK: bic r2, r3, #-2147483648 @ encoding: [0x02,0x21,0xc3,0xe3] @ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2] +@ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2] +@ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2] +@ CHECK: bic r1, r1, #14 @ encoding: [0x0e,0x10,0xc1,0xe3] +@ CHECK: and r7, r7, #16711680 @ encoding: [0xff,0x78,0x07,0xe2] +@ CHECK: and r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x07,0xe2] +@ CHECK: and r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x07,0xe2] +@ CHECK: and r7, r7, #40, #2 @ encoding: [0x28,0x71,0x07,0xe2] +@ CHECK: and r7, r7, #40, #2 @ encoding: [0x28,0x71,0x07,0xe2] +@ CHECK: and r7, r7, #40, #2 @ encoding: [0x28,0x71,0x07,0xe2] +@ CHECK: and r7, r7, #40, #2 @ encoding: [0x28,0x71,0x07,0xe2] @ CHECK: and r10, r10, r1 @ encoding: [0x01,0xa0,0x0a,0xe0] @ CHECK: and r10, r10, r1, lsl #10 @ encoding: [0x01,0xa5,0x0a,0xe0] @ CHECK: and r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0x0a,0xe0] @@ -348,6 +481,16 @@ Lforward: @ BIC @------------------------------------------------------------------------------ bic r10, r1, #0xf + bic r10, r1, $0xf + bic r10, r1, 0xf + bic r10, r1, -0xf + bic r7, r8, #(0xff << 16) + bic r7, r8, #-2147483638 + bic r7, r8, #42, #2 + bic r7, r8, #40, #2 + bic r7, r8, $40, $2 + bic r7, r8, 40, 2 + bic r7, r8, (2 * 20), (1 << 1) bic r10, r1, r6 bic r10, r1, r6, lsl #10 bic r10, r1, r6, lsr #10 @@ -362,6 +505,16 @@ Lforward: @ destination register is optional bic r1, #0xf + bic r1, $0xf + bic r1, 0xf + bic r1, -0xf + bic r7, #(0xff << 16) + bic r7, #-2147483638 + bic r7, #42, #2 + bic r7, #40, #2 + bic r7, $40, $2 + bic r7, 40, 2 + bic r7, (2 * 20), (1 << 1) bic r10, r1 bic r10, r1, lsl #10 bic r10, r1, lsr #10 @@ -375,6 +528,15 @@ Lforward: bic r10, r1, rrx @ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3] +@ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3] +@ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3] +@ CHECK: and r10, r1, #14 @ encoding: [0x0e,0xa0,0x01,0xe2] +@ CHECK: bic r7, r8, #16711680 @ encoding: [0xff,0x78,0xc8,0xe3] +@ CHECK: bic r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe3] +@ CHECK: bic r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe3] +@ CHECK: bic r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe3] +@ CHECK: bic r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe3] +@ CHECK: bic r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe3] @ CHECK: bic r10, r1, r6 @ encoding: [0x06,0xa0,0xc1,0xe1] @ CHECK: bic r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0xc1,0xe1] @ CHECK: bic r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0xc1,0xe1] @@ -389,6 +551,16 @@ Lforward: @ CHECK: bic r1, r1, #15 @ encoding: [0x0f,0x10,0xc1,0xe3] +@ CHECK: bic r1, r1, #15 @ encoding: [0x0f,0x10,0xc1,0xe3] +@ CHECK: bic r1, r1, #15 @ encoding: [0x0f,0x10,0xc1,0xe3] +@ CHECK: and r1, r1, #14 @ encoding: [0x0e,0x10,0x01,0xe2] +@ CHECK: bic r7, r7, #16711680 @ encoding: [0xff,0x78,0xc7,0xe3] +@ CHECK: bic r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xc7,0xe3] +@ CHECK: bic r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xc7,0xe3] +@ CHECK: bic r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe3] +@ CHECK: bic r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe3] +@ CHECK: bic r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe3] +@ CHECK: bic r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe3] @ CHECK: bic r10, r10, r1 @ encoding: [0x01,0xa0,0xca,0xe1] @ CHECK: bic r10, r10, r1, lsl #10 @ encoding: [0x01,0xa5,0xca,0xe1] @ CHECK: bic r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0xca,0xe1] @@ -505,6 +677,16 @@ Lforward: @ CMN @------------------------------------------------------------------------------ cmn r1, #0xf + cmn r1, $0xf + cmn r1, 0xf + cmn r1, -0xf + cmn r7, #(0xff << 16) + cmn r7, #-2147483638 + cmn r7, #42, #2 + cmn r7, #40, #2 + cmn r7, $40, $2 + cmn r7, 40, 2 + cmn r7, (20 * 2), (1 << 1) cmn r1, r6 cmn r1, r6, lsl #10 cmn r1, r6, lsr #10 @@ -518,6 +700,16 @@ Lforward: cmn r1, r6, rrx @ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3] +@ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3] +@ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3] +@ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3] +@ CHECK: cmn r7, #16711680 @ encoding: [0xff,0x08,0x77,0xe3] +@ CHECK: cmn r7, #-2147483638 @ encoding: [0x2a,0x01,0x77,0xe3] +@ CHECK: cmn r7, #-2147483638 @ encoding: [0x2a,0x01,0x77,0xe3] +@ CHECK: cmn r7, #40, #2 @ encoding: [0x28,0x01,0x77,0xe3] +@ CHECK: cmn r7, #40, #2 @ encoding: [0x28,0x01,0x77,0xe3] +@ CHECK: cmn r7, #40, #2 @ encoding: [0x28,0x01,0x77,0xe3] +@ CHECK: cmn r7, #40, #2 @ encoding: [0x28,0x01,0x77,0xe3] @ CHECK: cmn r1, r6 @ encoding: [0x06,0x00,0x71,0xe1] @ CHECK: cmn r1, r6, lsl #10 @ encoding: [0x06,0x05,0x71,0xe1] @ CHECK: cmn r1, r6, lsr #10 @ encoding: [0x26,0x05,0x71,0xe1] @@ -534,6 +726,16 @@ Lforward: @ CMP @------------------------------------------------------------------------------ cmp r1, #0xf + cmp r1, $0xf + cmp r1, 0xf + cmp r1, -0xf + cmp r7, #(0xff << 16) + cmp r7, #-2147483638 + cmp r7, #42, #2 + cmp r7, #40, #2 + cmp r7, $40, $2 + cmp r7, 40, 2 + cmp r7, (2 * 20), (1 << 1) cmp r1, r6 cmp r1, r6, lsl #10 cmp r1, r6, lsr #10 @@ -549,6 +751,16 @@ Lforward: cmp lr, #0 @ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3] +@ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3] +@ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3] +@ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3] +@ CHECK: cmp r7, #16711680 @ encoding: [0xff,0x08,0x57,0xe3] +@ CHECK: cmp r7, #-2147483638 @ encoding: [0x2a,0x01,0x57,0xe3] +@ CHECK: cmp r7, #-2147483638 @ encoding: [0x2a,0x01,0x57,0xe3] +@ CHECK: cmp r7, #40, #2 @ encoding: [0x28,0x01,0x57,0xe3] +@ CHECK: cmp r7, #40, #2 @ encoding: [0x28,0x01,0x57,0xe3] +@ CHECK: cmp r7, #40, #2 @ encoding: [0x28,0x01,0x57,0xe3] +@ CHECK: cmp r7, #40, #2 @ encoding: [0x28,0x01,0x57,0xe3] @ CHECK: cmp r1, r6 @ encoding: [0x06,0x00,0x51,0xe1] @ CHECK: cmp r1, r6, lsl #10 @ encoding: [0x06,0x05,0x51,0xe1] @ CHECK: cmp r1, r6, lsr #10 @ encoding: [0x26,0x05,0x51,0xe1] @@ -734,6 +946,15 @@ Lforward: @ EOR @------------------------------------------------------------------------------ eor r4, r5, #0xf000 + eor r4, r5, $0xf000 + eor r4, r5, 0xf000 + eor r7, r8, #(0xff << 16) + eor r7, r8, #-2147483638 + eor r7, r8, #42, #2 + eor r7, r8, #40, #2 + eor r7, r8, $40, $2 + eor r7, r8, 40, 2 + eor r7, r8, (20 * 2), (1 << 1) eor r4, r5, r6 eor r4, r5, r6, lsl #5 eor r4, r5, r6, lsr #5 @@ -748,6 +969,15 @@ Lforward: @ destination register is optional eor r5, #0xf000 + eor r5, $0xf000 + eor r5, 0xf000 + eor r7, #(0xff << 16) + eor r7, #-2147483638 + eor r7, #42, #2 + eor r7, #40, #2 + eor r7, $40, $2 + eor r7, 40, 2 + eor r7, (20 * 2), (1 << 1) eor r4, r5 eor r4, r5, lsl #5 eor r4, r5, lsr #5 @@ -761,6 +991,15 @@ Lforward: eor r4, r5, rrx @ CHECK: eor r4, r5, #61440 @ encoding: [0x0f,0x4a,0x25,0xe2] +@ CHECK: eor r4, r5, #61440 @ encoding: [0x0f,0x4a,0x25,0xe2] +@ CHECK: eor r4, r5, #61440 @ encoding: [0x0f,0x4a,0x25,0xe2] +@ CHECK: eor r7, r8, #16711680 @ encoding: [0xff,0x78,0x28,0xe2] +@ CHECK: eor r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x28,0xe2] +@ CHECK: eor r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x28,0xe2] +@ CHECK: eor r7, r8, #40, #2 @ encoding: [0x28,0x71,0x28,0xe2] +@ CHECK: eor r7, r8, #40, #2 @ encoding: [0x28,0x71,0x28,0xe2] +@ CHECK: eor r7, r8, #40, #2 @ encoding: [0x28,0x71,0x28,0xe2] +@ CHECK: eor r7, r8, #40, #2 @ encoding: [0x28,0x71,0x28,0xe2] @ CHECK: eor r4, r5, r6 @ encoding: [0x06,0x40,0x25,0xe0] @ CHECK: eor r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x25,0xe0] @ CHECK: eor r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x25,0xe0] @@ -775,6 +1014,15 @@ Lforward: @ CHECK: eor r5, r5, #61440 @ encoding: [0x0f,0x5a,0x25,0xe2] +@ CHECK: eor r5, r5, #61440 @ encoding: [0x0f,0x5a,0x25,0xe2] +@ CHECK: eor r5, r5, #61440 @ encoding: [0x0f,0x5a,0x25,0xe2] +@ CHECK: eor r7, r7, #16711680 @ encoding: [0xff,0x78,0x27,0xe2] +@ CHECK: eor r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x27,0xe2] +@ CHECK: eor r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x27,0xe2] +@ CHECK: eor r7, r7, #40, #2 @ encoding: [0x28,0x71,0x27,0xe2] +@ CHECK: eor r7, r7, #40, #2 @ encoding: [0x28,0x71,0x27,0xe2] +@ CHECK: eor r7, r7, #40, #2 @ encoding: [0x28,0x71,0x27,0xe2] +@ CHECK: eor r7, r7, #40, #2 @ encoding: [0x28,0x71,0x27,0xe2] @ CHECK: eor r4, r4, r5 @ encoding: [0x05,0x40,0x24,0xe0] @ CHECK: eor r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x24,0xe0] @ CHECK: eor r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x24,0xe0] @@ -1028,8 +1276,23 @@ Lforward: @ MOV (immediate) @------------------------------------------------------------------------------ mov r3, #7 + mov r3, $7 + mov r3, 7 + mov r3, -7 mov r4, #0xff0 mov r5, #0xff0000 + mov r7, #42, #0 + mov r7, #42, #10 + mov r7, #(0xff << 16) + mov r7, #-2147483638 + mov r7, #42, #2 + mov pc, #42, #2 + mov r7, #0, #2 + mov r7, #40, #2 + mov r7, $40, $2 + mov r7, 40, 2 + mov r7, (2 * 20), (1 << 1) + mov r7, #42, #30 mov r6, #0xffff movw r9, #0xffff movs r3, #7 @@ -1037,8 +1300,23 @@ Lforward: movseq r5, #0xff0000 @ CHECK: mov r3, #7 @ encoding: [0x07,0x30,0xa0,0xe3] +@ CHECK: mov r3, #7 @ encoding: [0x07,0x30,0xa0,0xe3] +@ CHECK: mov r3, #7 @ encoding: [0x07,0x30,0xa0,0xe3] +@ CHECK: mvn r3, #6 @ encoding: [0x06,0x30,0xe0,0xe3] @ CHECK: mov r4, #4080 @ encoding: [0xff,0x4e,0xa0,0xe3] @ CHECK: mov r5, #16711680 @ encoding: [0xff,0x58,0xa0,0xe3] +@ CHECK: mov r7, #42 @ encoding: [0x2a,0x70,0xa0,0xe3] +@ CHECK: mov r7, #176160768 @ encoding: [0x2a,0x75,0xa0,0xe3] +@ CHECK: mov r7, #16711680 @ encoding: [0xff,0x78,0xa0,0xe3] +@ CHECK: mov r7, #-2147483638 @ encoding: [0x2a,0x71,0xa0,0xe3] +@ CHECK: mov r7, #-2147483638 @ encoding: [0x2a,0x71,0xa0,0xe3] +@ CHECK: mov pc, #2147483658 @ encoding: [0x2a,0xf1,0xa0,0xe3] +@ CHECK: mov r7, #0, #2 @ encoding: [0x00,0x71,0xa0,0xe3] +@ CHECK: mov r7, #40, #2 @ encoding: [0x28,0x71,0xa0,0xe3] +@ CHECK: mov r7, #40, #2 @ encoding: [0x28,0x71,0xa0,0xe3] +@ CHECK: mov r7, #40, #2 @ encoding: [0x28,0x71,0xa0,0xe3] +@ CHECK: mov r7, #40, #2 @ encoding: [0x28,0x71,0xa0,0xe3] +@ CHECK: mov r7, #42, #30 @ encoding: [0x2a,0x7f,0xa0,0xe3] @ CHECK: movw r6, #65535 @ encoding: [0xff,0x6f,0x0f,0xe3] @ CHECK: movw r9, #65535 @ encoding: [0xff,0x9f,0x0f,0xe3] @ CHECK: movs r3, #7 @ encoding: [0x07,0x30,0xb0,0xe3] @@ -1132,6 +1410,8 @@ Lforward: @------------------------------------------------------------------------------ msr apsr, #5 + msr apsr, $5 + msr apsr, 5 msr apsr_g, #5 msr apsr_nzcvq, #5 msr APSR_nzcvq, #5 @@ -1145,8 +1425,17 @@ Lforward: msr spsr_fc, #5 msr SPSR_fsxc, #5 msr cpsr_fsxc, #5 + msr apsr_nzcvqg, #(0xff << 16) + msr APSR_nzcvq, #42, #2 + msr apsr_nzcvqg, #2147483658 + msr SPSR_fsxc, #40, #2 + msr SPSR_fsxc, $40, $2 + msr SPSR_fsxc, 40, 2 + msr SPSR_fsxc, (2 * 20), (1 << 1) @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] +@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] +@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] @ CHECK: msr APSR_g, #5 @ encoding: [0x05,0xf0,0x24,0xe3] @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] @@ -1160,6 +1449,13 @@ Lforward: @ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x69,0xe3] @ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3] @ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2f,0xe3] +@ CHECK: msr APSR_nzcvqg, #16711680 @ encoding: [0xff,0xf8,0x2c,0xe3] +@ CHECK: msr APSR_nzcvq, #2147483658 @ encoding: [0x2a,0xf1,0x28,0xe3] +@ CHECK: msr APSR_nzcvqg, #2147483658 @ encoding: [0x2a,0xf1,0x2c,0xe3] +@ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3] +@ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3] +@ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3] +@ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3] msr apsr, r0 msr apsr_g, r0 @@ -1210,15 +1506,37 @@ Lforward: @ MVN (immediate) @------------------------------------------------------------------------------ mvn r3, #7 + mvn r3, $7 + mvn r3, 7 + mvn r3, -7 + mvn r7, #~0xffffff00 mvn r4, #0xff0 mvn r5, #0xff0000 + mvn r7, #(0xff << 16) + mvn r7, #-2147483638 + mvn r7, #42, #2 + mvn r7, #40, #2 + mvn r7, $40, $2 + mvn r7, 40, 2 + mvn r7, (2 * 20), (1 << 1) mvns r3, #7 mvneq r4, #0xff0 mvnseq r5, #0xff0000 @ CHECK: mvn r3, #7 @ encoding: [0x07,0x30,0xe0,0xe3] +@ CHECK: mvn r3, #7 @ encoding: [0x07,0x30,0xe0,0xe3] +@ CHECK: mvn r3, #7 @ encoding: [0x07,0x30,0xe0,0xe3] +@ CHECK: mov r3, #6 @ encoding: [0x06,0x30,0xa0,0xe3] +@ CHECK: mvn r7, #255 @ encoding: [0xff,0x70,0xe0,0xe3] @ CHECK: mvn r4, #4080 @ encoding: [0xff,0x4e,0xe0,0xe3] @ CHECK: mvn r5, #16711680 @ encoding: [0xff,0x58,0xe0,0xe3] +@ CHECK: mvn r7, #16711680 @ encoding: [0xff,0x78,0xe0,0xe3] +@ CHECK: mvn r7, #-2147483638 @ encoding: [0x2a,0x71,0xe0,0xe3] +@ CHECK: mvn r7, #-2147483638 @ encoding: [0x2a,0x71,0xe0,0xe3] +@ CHECK: mvn r7, #40, #2 @ encoding: [0x28,0x71,0xe0,0xe3] +@ CHECK: mvn r7, #40, #2 @ encoding: [0x28,0x71,0xe0,0xe3] +@ CHECK: mvn r7, #40, #2 @ encoding: [0x28,0x71,0xe0,0xe3] +@ CHECK: mvn r7, #40, #2 @ encoding: [0x28,0x71,0xe0,0xe3] @ CHECK: mvns r3, #7 @ encoding: [0x07,0x30,0xf0,0xe3] @ CHECK: mvneq r4, #4080 @ encoding: [0xff,0x4e,0xe0,0x03] @ CHECK: mvnseq r5, #16711680 @ encoding: [0xff,0x58,0xf0,0x03] @@ -1285,6 +1603,15 @@ Lforward: @ ORR @------------------------------------------------------------------------------ orr r4, r5, #0xf000 + orr r4, r5, $0xf000 + orr r4, r5, 0xf000 + orr r7, r8, #(0xff << 16) + orr r7, r8, #-2147483638 + orr r7, r8, #42, #2 + orr r7, r8, #40, #2 + orr r7, r8, $40, $2 + orr r7, r8, 40, 2 + orr r7, r8, (2 * 20), (1 << 1) orr r4, r5, r6 orr r4, r5, r6, lsl #5 orr r4, r5, r6, lsr #5 @@ -1299,6 +1626,17 @@ Lforward: @ destination register is optional orr r5, #0xf000 + orr r5, $0xf000 + orr r5, 0xf000 + + orr r7, #(0xff << 16) + orr r7, #-2147483638 + orr r7, #42, #2 + orr r7, #40, #2 + orr r7, $40, $2 + orr r7, 40, 2 + orr r7, (2 * 20), (1 << 1) + orr r4, r5 orr r4, r5, lsl #5 orr r4, r5, lsr #5 @@ -1312,6 +1650,15 @@ Lforward: orr r4, r5, rrx @ CHECK: orr r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe3] +@ CHECK: orr r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe3] +@ CHECK: orr r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe3] +@ CHECK: orr r7, r8, #16711680 @ encoding: [0xff,0x78,0x88,0xe3] +@ CHECK: orr r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe3] +@ CHECK: orr r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe3] +@ CHECK: orr r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe3] +@ CHECK: orr r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe3] +@ CHECK: orr r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe3] +@ CHECK: orr r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe3] @ CHECK: orr r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe1] @ CHECK: orr r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe1] @ CHECK: orr r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe1] @@ -1325,6 +1672,15 @@ Lforward: @ CHECK: orr r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe1] @ CHECK: orr r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe3] +@ CHECK: orr r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe3] +@ CHECK: orr r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe3] +@ CHECK: orr r7, r7, #16711680 @ encoding: [0xff,0x78,0x87,0xe3] +@ CHECK: orr r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x87,0xe3] +@ CHECK: orr r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x87,0xe3] +@ CHECK: orr r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe3] +@ CHECK: orr r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe3] +@ CHECK: orr r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe3] +@ CHECK: orr r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe3] @ CHECK: orr r4, r4, r5 @ encoding: [0x05,0x40,0x84,0xe1] @ CHECK: orr r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x84,0xe1] @ CHECK: orr r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe1] @@ -1570,6 +1926,15 @@ Lforward: @ RSB @------------------------------------------------------------------------------ rsb r4, r5, #0xf000 + rsb r4, r5, $0xf000 + rsb r4, r5, 0xf000 + rsb r7, r8, #(0xff << 16) + rsb r7, r8, #-2147483638 + rsb r7, r8, #42, #2 + rsb r7, r8, #40, #2 + rsb r7, r8, $40, $2 + rsb r7, r8, 40, 2 + rsb r7, r8, (2 * 20), (1 << 1) rsb r4, r5, r6 rsb r4, r5, r6, lsl #5 rsblo r4, r5, r6, lsr #5 @@ -1584,6 +1949,15 @@ Lforward: @ destination register is optional rsb r5, #0xf000 + rsb r5, $0xf000 + rsb r5, 0xf000 + rsb r7, #(0xff << 16) + rsb r7, #-2147483638 + rsb r7, #42, #2 + rsb r7, #40, #2 + rsb r7, $40, $2 + rsb r7, 40, 2 + rsb r7, (2 * 20), (1 << 1) rsb r4, r5 rsb r4, r5, lsl #5 rsb r4, r5, lsr #5 @@ -1597,6 +1971,15 @@ Lforward: rsb r4, r5, rrx @ CHECK: rsb r4, r5, #61440 @ encoding: [0x0f,0x4a,0x65,0xe2] +@ CHECK: rsb r4, r5, #61440 @ encoding: [0x0f,0x4a,0x65,0xe2] +@ CHECK: rsb r4, r5, #61440 @ encoding: [0x0f,0x4a,0x65,0xe2] +@ CHECK: rsb r7, r8, #16711680 @ encoding: [0xff,0x78,0x68,0xe2] +@ CHECK: rsb r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x68,0xe2] +@ CHECK: rsb r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x68,0xe2] +@ CHECK: rsb r7, r8, #40, #2 @ encoding: [0x28,0x71,0x68,0xe2] +@ CHECK: rsb r7, r8, #40, #2 @ encoding: [0x28,0x71,0x68,0xe2] +@ CHECK: rsb r7, r8, #40, #2 @ encoding: [0x28,0x71,0x68,0xe2] +@ CHECK: rsb r7, r8, #40, #2 @ encoding: [0x28,0x71,0x68,0xe2] @ CHECK: rsb r4, r5, r6 @ encoding: [0x06,0x40,0x65,0xe0] @ CHECK: rsb r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x65,0xe0] @ CHECK: rsblo r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x65,0x30] @@ -1610,6 +1993,15 @@ Lforward: @ CHECK: rsb r4, r5, r6, rrx @ encoding: [0x66,0x40,0x65,0xe0] @ CHECK: rsb r5, r5, #61440 @ encoding: [0x0f,0x5a,0x65,0xe2] +@ CHECK: rsb r5, r5, #61440 @ encoding: [0x0f,0x5a,0x65,0xe2] +@ CHECK: rsb r5, r5, #61440 @ encoding: [0x0f,0x5a,0x65,0xe2] +@ CHECK: rsb r7, r7, #16711680 @ encoding: [0xff,0x78,0x67,0xe2] +@ CHECK: rsb r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x67,0xe2] +@ CHECK: rsb r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x67,0xe2] +@ CHECK: rsb r7, r7, #40, #2 @ encoding: [0x28,0x71,0x67,0xe2] +@ CHECK: rsb r7, r7, #40, #2 @ encoding: [0x28,0x71,0x67,0xe2] +@ CHECK: rsb r7, r7, #40, #2 @ encoding: [0x28,0x71,0x67,0xe2] +@ CHECK: rsb r7, r7, #40, #2 @ encoding: [0x28,0x71,0x67,0xe2] @ CHECK: rsb r4, r4, r5 @ encoding: [0x05,0x40,0x64,0xe0] @ CHECK: rsb r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x64,0xe0] @ CHECK: rsb r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x64,0xe0] @@ -1623,9 +2015,43 @@ Lforward: @ CHECK: rsb r4, r4, r5, rrx @ encoding: [0x65,0x40,0x64,0xe0] @------------------------------------------------------------------------------ +@ RSBS +@------------------------------------------------------------------------------ + rsbs r7, #16711680 + rsbs r7, $16711680 + rsbs r7, 16711680 + rsbs r7, #(0xff << 16) + rsbs r7, r8, #-2147483638 + rsbs r7, r8, #42, #2 + rsbs r7, r8, #40, #2 + rsbs r7, r8, $40, $2 + rsbs r7, r8, 40, 2 + rsbs r7, r8, (2 * 20), (1 << 1) + +@ CHECK: rsbs r7, r7, #16711680 @ encoding: [0xff,0x78,0x77,0xe2] +@ CHECK: rsbs r7, r7, #16711680 @ encoding: [0xff,0x78,0x77,0xe2] +@ CHECK: rsbs r7, r7, #16711680 @ encoding: [0xff,0x78,0x77,0xe2] +@ CHECK: rsbs r7, r7, #16711680 @ encoding: [0xff,0x78,0x77,0xe2] +@ CHECK: rsbs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x78,0xe2] +@ CHECK: rsbs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x78,0xe2] +@ CHECK: rsbs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x78,0xe2] +@ CHECK: rsbs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x78,0xe2] +@ CHECK: rsbs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x78,0xe2] +@ CHECK: rsbs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x78,0xe2] + +@------------------------------------------------------------------------------ @ RSC @------------------------------------------------------------------------------ rsc r4, r5, #0xf000 + rsc r4, r5, $0xf000 + rsc r4, r5, 0xf000 + rsc r7, r8, #(0xff << 16) + rsc r7, r8, #-2147483638 + rsc r7, r8, #42, #2 + rsc r7, r8, #40, #2 + rsc r7, r8, $40, $2 + rsc r7, r8, 40, 2 + rsc r7, r8, (2 * 20), (1 << 1) rsc r4, r5, r6 rsc r4, r5, r6, lsl #5 rsclo r4, r5, r6, lsr #5 @@ -1640,6 +2066,15 @@ Lforward: @ destination register is optional rsc r5, #0xf000 + rsc r5, $0xf000 + rsc r5, 0xf000 + rsc r7, #(0xff << 16) + rsc r7, #-2147483638 + rsc r7, #42, #2 + rsc r7, #40, #2 + rsc r7, $40, $2 + rsc r7, 40, 2 + rsc r7, (2 * 20), (1 << 1) rsc r4, r5 rsc r4, r5, lsl #5 rsc r4, r5, lsr #5 @@ -1652,6 +2087,15 @@ Lforward: rsc r6, r7, ror r9 @ CHECK: rsc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xe5,0xe2] +@ CHECK: rsc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xe5,0xe2] +@ CHECK: rsc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xe5,0xe2] +@ CHECK: rsc r7, r8, #16711680 @ encoding: [0xff,0x78,0xe8,0xe2] +@ CHECK: rsc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xe8,0xe2] +@ CHECK: rsc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xe8,0xe2] +@ CHECK: rsc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xe8,0xe2] +@ CHECK: rsc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xe8,0xe2] +@ CHECK: rsc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xe8,0xe2] +@ CHECK: rsc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xe8,0xe2] @ CHECK: rsc r4, r5, r6 @ encoding: [0x06,0x40,0xe5,0xe0] @ CHECK: rsc r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0xe5,0xe0] @ CHECK: rsclo r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xe5,0x30] @@ -1665,6 +2109,15 @@ Lforward: @ CHECK: rscs r1, r8, #4064 @ encoding: [0xfe,0x1e,0xf8,0xe2] @ CHECK: rsc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xe5,0xe2] +@ CHECK: rsc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xe5,0xe2] +@ CHECK: rsc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xe5,0xe2] +@ CHECK: rsc r7, r7, #16711680 @ encoding: [0xff,0x78,0xe7,0xe2] +@ CHECK: rsc r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xe7,0xe2] +@ CHECK: rsc r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xe7,0xe2] +@ CHECK: rsc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xe7,0xe2] +@ CHECK: rsc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xe7,0xe2] +@ CHECK: rsc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xe7,0xe2] +@ CHECK: rsc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xe7,0xe2] @ CHECK: rsc r4, r4, r5 @ encoding: [0x05,0x40,0xe4,0xe0] @ CHECK: rsc r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0xe4,0xe0] @ CHECK: rsc r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0xe4,0xe0] @@ -1728,6 +2181,15 @@ Lforward: @ SBC @------------------------------------------------------------------------------ sbc r4, r5, #0xf000 + sbc r4, r5, $0xf000 + sbc r4, r5, 0xf000 + sbc r7, r8, #(0xff << 16) + sbc r7, r8, #-2147483638 + sbc r7, r8, #42, #2 + sbc r7, r8, #40, #2 + sbc r7, r8, $40, $2 + sbc r7, r8, 40, 2 + sbc r7, r8, (20 * 2), (1 << 1) sbc r4, r5, r6 sbc r4, r5, r6, lsl #5 sbc r4, r5, r6, lsr #5 @@ -1741,6 +2203,15 @@ Lforward: @ destination register is optional sbc r5, #0xf000 + sbc r5, $0xf000 + sbc r5, 0xf000 + sbc r7, #(0xff << 16) + sbc r7, #-2147483638 + sbc r7, #42, #2 + sbc r7, #40, #2 + sbc r7, $40, $2 + sbc r7, 40, 2 + sbc r7, (20 * 2), (1 << 1) sbc r4, r5 sbc r4, r5, lsl #5 sbc r4, r5, lsr #5 @@ -1753,6 +2224,15 @@ Lforward: sbc r6, r7, ror r9 @ CHECK: sbc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xc5,0xe2] +@ CHECK: sbc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xc5,0xe2] +@ CHECK: sbc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xc5,0xe2] +@ CHECK: sbc r7, r8, #16711680 @ encoding: [0xff,0x78,0xc8,0xe2] +@ CHECK: sbc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe2] +@ CHECK: sbc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe2] +@ CHECK: sbc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe2] +@ CHECK: sbc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe2] +@ CHECK: sbc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe2] +@ CHECK: sbc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe2] @ CHECK: sbc r4, r5, r6 @ encoding: [0x06,0x40,0xc5,0xe0] @ CHECK: sbc r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0xc5,0xe0] @ CHECK: sbc r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xc5,0xe0] @@ -1765,6 +2245,15 @@ Lforward: @ CHECK: sbc r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0xc7,0xe0] @ CHECK: sbc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xc5,0xe2] +@ CHECK: sbc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xc5,0xe2] +@ CHECK: sbc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xc5,0xe2] +@ CHECK: sbc r7, r7, #16711680 @ encoding: [0xff,0x78,0xc7,0xe2] +@ CHECK: sbc r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xc7,0xe2] +@ CHECK: sbc r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xc7,0xe2] +@ CHECK: sbc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe2] +@ CHECK: sbc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe2] +@ CHECK: sbc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe2] +@ CHECK: sbc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe2] @ CHECK: sbc r4, r4, r5 @ encoding: [0x05,0x40,0xc4,0xe0] @ CHECK: sbc r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0xc4,0xe0] @ CHECK: sbc r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0xc4,0xe0] @@ -2383,6 +2872,15 @@ Lforward: @ SUB @------------------------------------------------------------------------------ sub r4, r5, #0xf000 + sub r4, r5, $0xf000 + sub r4, r5, 0xf000 + sub r7, r8, #(0xff << 16) + sub r7, r8, #-2147483638 + sub r7, r8, #42, #2 + sub r7, r8, #40, #2 + sub r7, r8, $40, $2 + sub r7, r8, 40, 2 + sub r7, r8, (20 * 2), (1 << 1) sub r4, r5, r6 sub r4, r5, r6, lsl #5 sub r4, r5, r6, lsr #5 @@ -2396,6 +2894,15 @@ Lforward: @ destination register is optional sub r5, #0xf000 + sub r5, $0xf000 + sub r5, 0xf000 + sub r7, #(0xff << 16) + sub r7, #-2147483638 + sub r7, #42, #2 + sub r7, #40, #2 + sub r7, $40, $2 + sub r7, 40, 2 + sub r7, (20 * 2), (1 << 1) sub r4, r5 sub r4, r5, lsl #5 sub r4, r5, lsr #5 @@ -2408,6 +2915,15 @@ Lforward: sub r6, r7, ror r9 @ CHECK: sub r4, r5, #61440 @ encoding: [0x0f,0x4a,0x45,0xe2] +@ CHECK: sub r4, r5, #61440 @ encoding: [0x0f,0x4a,0x45,0xe2] +@ CHECK: sub r4, r5, #61440 @ encoding: [0x0f,0x4a,0x45,0xe2] +@ CHECK: sub r7, r8, #16711680 @ encoding: [0xff,0x78,0x48,0xe2] +@ CHECK: sub r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x48,0xe2] +@ CHECK: sub r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x48,0xe2] +@ CHECK: sub r7, r8, #40, #2 @ encoding: [0x28,0x71,0x48,0xe2] +@ CHECK: sub r7, r8, #40, #2 @ encoding: [0x28,0x71,0x48,0xe2] +@ CHECK: sub r7, r8, #40, #2 @ encoding: [0x28,0x71,0x48,0xe2] +@ CHECK: sub r7, r8, #40, #2 @ encoding: [0x28,0x71,0x48,0xe2] @ CHECK: sub r4, r5, r6 @ encoding: [0x06,0x40,0x45,0xe0] @ CHECK: sub r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x45,0xe0] @ CHECK: sub r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x45,0xe0] @@ -2421,6 +2937,15 @@ Lforward: @ CHECK: sub r5, r5, #61440 @ encoding: [0x0f,0x5a,0x45,0xe2] +@ CHECK: sub r5, r5, #61440 @ encoding: [0x0f,0x5a,0x45,0xe2] +@ CHECK: sub r5, r5, #61440 @ encoding: [0x0f,0x5a,0x45,0xe2] +@ CHECK: sub r7, r7, #16711680 @ encoding: [0xff,0x78,0x47,0xe2] +@ CHECK: sub r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x47,0xe2] +@ CHECK: sub r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x47,0xe2] +@ CHECK: sub r7, r7, #40, #2 @ encoding: [0x28,0x71,0x47,0xe2] +@ CHECK: sub r7, r7, #40, #2 @ encoding: [0x28,0x71,0x47,0xe2 +@ CHECK: sub r7, r7, #40, #2 @ encoding: [0x28,0x71,0x47,0xe2] +@ CHECK: sub r7, r7, #40, #2 @ encoding: [0x28,0x71,0x47,0xe2] @ CHECK: sub r4, r4, r5 @ encoding: [0x05,0x40,0x44,0xe0] @ CHECK: sub r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x44,0xe0] @ CHECK: sub r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x44,0xe0] @@ -2439,6 +2964,31 @@ Lforward: @ CHECK: sub r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x41,0xe0] @------------------------------------------------------------------------------ +@ SUBS +@------------------------------------------------------------------------------ + subs r7, r8, #16711680 + subs r7, r8, $16711680 + subs r7, r8, 16711680 + subs r7, r8, #(0xff << 16) + subs r7, r8, #-2147483638 + subs r7, r8, #42, #2 + subs r7, r8, #40, #2 + subs r7, r8, $40, $2 + subs r7, r8, 40, 2 + subs r7, r8, (20 * 2), (1 << 1) + +@ CHECK: subs r7, r8, #16711680 @ encoding: [0xff,0x78,0x58,0xe2] +@ CHECK: subs r7, r8, #16711680 @ encoding: [0xff,0x78,0x58,0xe2] +@ CHECK: subs r7, r8, #16711680 @ encoding: [0xff,0x78,0x58,0xe2] +@ CHECK: subs r7, r8, #16711680 @ encoding: [0xff,0x78,0x58,0xe2] +@ CHECK: subs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x58,0xe2] +@ CHECK: subs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x58,0xe2] +@ CHECK: subs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x58,0xe2] +@ CHECK: subs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x58,0xe2] +@ CHECK: subs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x58,0xe2] +@ CHECK: subs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x58,0xe2] + +@------------------------------------------------------------------------------ @ SVC @------------------------------------------------------------------------------ svc #16 @@ -2560,6 +3110,15 @@ Lforward: @ TEQ @------------------------------------------------------------------------------ teq r5, #0xf000 + teq r5, $0xf000 + teq r5, 0xf000 + teq r7, #(0xff << 16) + teq r7, #-2147483638 + teq r7, #42, #2 + teq r7, #40, #2 + teq r7, $40, $2 + teq r7, 40, 2 + teq r7, (20 * 2), (1 << 1) teq r4, r5 teq r4, r5, lsl #5 teq r4, r5, lsr #5 @@ -2572,6 +3131,15 @@ Lforward: teq r6, r7, ror r9 @ CHECK: teq r5, #61440 @ encoding: [0x0f,0x0a,0x35,0xe3] +@ CHECK: teq r5, #61440 @ encoding: [0x0f,0x0a,0x35,0xe3] +@ CHECK: teq r5, #61440 @ encoding: [0x0f,0x0a,0x35,0xe3] +@ CHECK: teq r7, #16711680 @ encoding: [0xff,0x08,0x37,0xe3] +@ CHECK: teq r7, #-2147483638 @ encoding: [0x2a,0x01,0x37,0xe3] +@ CHECK: teq r7, #-2147483638 @ encoding: [0x2a,0x01,0x37,0xe3] +@ CHECK: teq r7, #40, #2 @ encoding: [0x28,0x01,0x37,0xe3] +@ CHECK: teq r7, #40, #2 @ encoding: [0x28,0x01,0x37,0xe3] +@ CHECK: teq r7, #40, #2 @ encoding: [0x28,0x01,0x37,0xe3] +@ CHECK: teq r7, #40, #2 @ encoding: [0x28,0x01,0x37,0xe3] @ CHECK: teq r4, r5 @ encoding: [0x05,0x00,0x34,0xe1] @ CHECK: teq r4, r5, lsl #5 @ encoding: [0x85,0x02,0x34,0xe1] @ CHECK: teq r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x34,0xe1] @@ -2588,6 +3156,15 @@ Lforward: @ TST @------------------------------------------------------------------------------ tst r5, #0xf000 + tst r5, $0xf000 + tst r5, 0xf000 + tst r7, #(0xff << 16) + tst r7, #-2147483638 + tst r7, #42, #2 + tst r7, #40, #2 + tst r7, $40, $2 + tst r7, 40, 2 + tst r7, (20 * 2), (1 << 1) tst r4, r5 tst r4, r5, lsl #5 tst r4, r5, lsr #5 @@ -2600,6 +3177,15 @@ Lforward: tst r6, r7, ror r9 @ CHECK: tst r5, #61440 @ encoding: [0x0f,0x0a,0x15,0xe3] +@ CHECK: tst r5, #61440 @ encoding: [0x0f,0x0a,0x15,0xe3] +@ CHECK: tst r5, #61440 @ encoding: [0x0f,0x0a,0x15,0xe3] +@ CHECK: tst r7, #16711680 @ encoding: [0xff,0x08,0x17,0xe3] +@ CHECK: tst r7, #-2147483638 @ encoding: [0x2a,0x01,0x17,0xe3] +@ CHECK: tst r7, #-2147483638 @ encoding: [0x2a,0x01,0x17,0xe3] +@ CHECK: tst r7, #40, #2 @ encoding: [0x28,0x01,0x17,0xe3] +@ CHECK: tst r7, #40, #2 @ encoding: [0x28,0x01,0x17,0xe3] +@ CHECK: tst r7, #40, #2 @ encoding: [0x28,0x01,0x17,0xe3] +@ CHECK: tst r7, #40, #2 @ encoding: [0x28,0x01,0x17,0xe3] @ CHECK: tst r4, r5 @ encoding: [0x05,0x00,0x14,0xe1] @ CHECK: tst r4, r5, lsl #5 @ encoding: [0x85,0x02,0x14,0xe1] @ CHECK: tst r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x14,0xe1] diff --git a/test/MC/ARM/coff-debugging-secrel.ll b/test/MC/ARM/coff-debugging-secrel.ll index 0e5c8e6..7323fc6 100644 --- a/test/MC/ARM/coff-debugging-secrel.ll +++ b/test/MC/ARM/coff-debugging-secrel.ll @@ -16,17 +16,17 @@ entry: !llvm.dbg.cu = !{!7} !llvm.module.flags = !{!9, !10} -!0 = metadata !{i32 1, i32 0, metadata !1, null} -!1 = metadata !{metadata !"0x2e\00function\00function\00\001\000\001\000\006\000\000\001", metadata !2, metadata !3, metadata !4, null, void ()* @function, null, null, metadata !6} ; [ DW_TAG_subprogram ], [line 1], [def], [function] -!2 = metadata !{metadata !"/Users/compnerd/work/llvm/test/MC/ARM/reduced.c", metadata !"/Users/compnerd/work/llvm"} -!3 = metadata !{metadata !"0x29", metadata !2} ; [ DW_TAG_file_type] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c] -!4 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !5, null, null, null} ; [ DW_TAG_subroutine_type ], [line 0, size 0, align 0, offset 0] [from ] -!5 = metadata !{null} -!6 = metadata !{} -!7 = metadata !{metadata !"0x11\0012\00clang version 3.5.0\000\00\000\00\001", metadata !2, metadata !6, metadata !6, metadata !8, metadata !6, metadata !6} ; [ DW_TAG_compile_unit ] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c] [DW_LANG_C99] -!8 = metadata !{metadata !1} -!9 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} -!10 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !MDLocation(line: 1, scope: !1) +!1 = !{!"0x2e\00function\00function\00\001\000\001\000\006\000\000\001", !2, !3, !4, null, void ()* @function, null, null, !6} ; [ DW_TAG_subprogram ], [line 1], [def], [function] +!2 = !{!"/Users/compnerd/work/llvm/test/MC/ARM/reduced.c", !"/Users/compnerd/work/llvm"} +!3 = !{!"0x29", !2} ; [ DW_TAG_file_type] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c] +!4 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ], [line 0, size 0, align 0, offset 0] [from ] +!5 = !{null} +!6 = !{} +!7 = !{!"0x11\0012\00clang version 3.5.0\000\00\000\00\001", !2, !6, !6, !8, !6, !6} ; [ DW_TAG_compile_unit ] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c] [DW_LANG_C99] +!8 = !{!1} +!9 = !{i32 2, !"Dwarf Version", i32 4} +!10 = !{i32 1, !"Debug Info Version", i32 2} ; CHECK-ITANIUM: Relocations [ ; CHECK-ITANIUM: Section {{.*}} .debug_info { diff --git a/test/MC/ARM/cpu-test.s b/test/MC/ARM/cpu-test.s new file mode 100644 index 0000000..7a61907 --- /dev/null +++ b/test/MC/ARM/cpu-test.s @@ -0,0 +1,17 @@ +// RUN: not llvm-mc -o - -triple arm-gnueabi-freebsd11.0 < %s > %t 2> %t2 +// RUN: FileCheck %s < %t +// RUN: FileCheck %s --check-prefix=CHECK-ERROR < %t2 + +// CHECK: .cpu cortex-a8 +.cpu cortex-a8 +// CHECK: dsb sy +dsb +.cpu arm9 +// CHECK-ERROR: error: instruction requires: data-barriers +dsb +// CHECK-ERROR: error: Unknown CPU name +.cpu foobar +// CHECK: .cpu cortex-m3 +.cpu cortex-m3 +// CHECK: sub sp, #16 +sub sp,#16 diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s index 6b9574b..6f66dc3 100644 --- a/test/MC/ARM/diagnostics.s +++ b/test/MC/ARM/diagnostics.s @@ -621,3 +621,83 @@ foo2: @ CHECK-ERRORS: error: destination register and base register can't be identical @ CHECK-ERRORS: ldrsb r0, [r0], r1 @ CHECK-ERRORS: ^ + + @ Out of range modified immediate values + mov r5, #-256, #6 + mov r6, #42, #7 + mvn r5, #256, #6 + mvn r6, #42, #298 + cmp r5, #65535, #6 + cmp r6, #42, #31 + cmn r5, #-1, #6 + cmn r6, #42, #32 + msr APSR_nzcvq, #-128, #2 + msr apsr_nzcvqg, #0, #1 + adc r7, r8, #-256, #2 + adc r7, r8, #128, #1 + sbc r7, r8, #-256, #2 + sbc r7, r8, #128, #1 + add r7, r8, #-2149, #0 + add r7, r8, #100, #1 + sub r7, r8, #-2149, #0 + sub r7, r8, #100, #1 + and r7, r8, #-2149, #0 + and r7, r8, #100, #1 + orr r7, r8, #-2149, #0 + orr r7, r8, #100, #1 + eor r7, r8, #-2149, #0 + eor r7, r8, #100, #1 + bic r7, r8, #-2149, #0 + bic r7, r8, #100, #1 + rsb r7, r8, #-2149, #0 + rsb r7, r8, #100, #1 + adds r7, r8, #-2149, #0 + adds r7, r8, #100, #1 + subs r7, r8, #-2149, #0 + subs r7, r8, #100, #1 + rsbs r7, r8, #-2149, #0 + rsbs r7, r8, #100, #1 + rsc r7, r8, #-2149, #0 + rsc r7, r8, #100, #1 + TST r7, #-2149, #0 + TST r7, #100, #1 + TEQ r7, #-2149, #0 + TEQ r7, #100, #1 +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] diff --git a/test/MC/ARM/directive-arch-iwmmxt.s b/test/MC/ARM/directive-arch-iwmmxt.s index db25ec6..c54846d 100644 --- a/test/MC/ARM/directive-arch-iwmmxt.s +++ b/test/MC/ARM/directive-arch-iwmmxt.s @@ -16,7 +16,7 @@ @ CHECK-ATTR: FileAttributes { @ CHECK-ATTR: Attribute { @ CHECK-ATTR: TagName: CPU_name -@ CHECK-ATTR: Value: IWMMXT +@ CHECK-ATTR: Value: iwmmxt @ CHECK-ATTR: } @ CHECK-ATTR: Attribute { @ CHECK-ATTR: TagName: CPU_arch diff --git a/test/MC/ARM/directive-arch-iwmmxt2.s b/test/MC/ARM/directive-arch-iwmmxt2.s index de94f97..a4e59b5 100644 --- a/test/MC/ARM/directive-arch-iwmmxt2.s +++ b/test/MC/ARM/directive-arch-iwmmxt2.s @@ -16,7 +16,7 @@ @ CHECK-ATTR: FileAttributes { @ CHECK-ATTR: Attribute { @ CHECK-ATTR: TagName: CPU_name -@ CHECK-ATTR: Value: IWMMXT2 +@ CHECK-ATTR: Value: iwmmxt2 @ CHECK-ATTR: } @ CHECK-ATTR: Attribute { @ CHECK-ATTR: TagName: CPU_arch diff --git a/test/MC/ARM/directive-cpu.s b/test/MC/ARM/directive-cpu.s index 952dd93..d81a03e 100644 --- a/test/MC/ARM/directive-cpu.s +++ b/test/MC/ARM/directive-cpu.s @@ -20,7 +20,6 @@ @ CHECK: 10000000 .cpu cortex-a8 -@ CHECK: 05 -@ CHECK: 434F52 5445582D 413800 +@ CHECK: 05636F72 7465782D 613800 @ CHECK: ) diff --git a/test/MC/ARM/directive-eabi_attribute-diagnostics.s b/test/MC/ARM/directive-eabi_attribute-diagnostics.s index d1ae352..2b0375e 100644 --- a/test/MC/ARM/directive-eabi_attribute-diagnostics.s +++ b/test/MC/ARM/directive-eabi_attribute-diagnostics.s @@ -29,6 +29,11 @@ @ CHECK: .eabi_attribute 0 @ CHECK: ^ + .eabi_attribute Tag_compatibility, 1 +@ CHECK: error: comma expected +@ CHECK: .eabi_attribute Tag_compatibility, 1 +@ CHECK: ^ + .eabi_attribute Tag_MPextension_use_old, 0 @ CHECK: error: attribute name not recognised: Tag_MPextension_use_old @ CHECK: .eabi_attribute Tag_MPextension_use_old, 0 diff --git a/test/MC/ARM/directive-eabi_attribute-overwrite.s b/test/MC/ARM/directive-eabi_attribute-overwrite.s index 6fdded3..e2c5099 100644 --- a/test/MC/ARM/directive-eabi_attribute-overwrite.s +++ b/test/MC/ARM/directive-eabi_attribute-overwrite.s @@ -3,13 +3,11 @@ .syntax unified .thumb - - .eabi_attribute Tag_compatibility, 1 .eabi_attribute Tag_compatibility, 1, "aeabi" @ CHECK-ATTR: FileAttributes { @ CHECK-ATTR: Attribute { -@ CHECK-ATTR: Value: 1, AEABI +@ CHECK-ATTR: Value: 1, aeabi @ CHECK-ATTR: TagName: compatibility @ CHECK-ATTR: Description: AEABI Conformant @ CHECK-ATTR: } diff --git a/test/MC/ARM/directive-eabi_attribute.s b/test/MC/ARM/directive-eabi_attribute.s index e2f1f9b..74a51ab 100644 --- a/test/MC/ARM/directive-eabi_attribute.s +++ b/test/MC/ARM/directive-eabi_attribute.s @@ -5,16 +5,24 @@ .syntax unified .thumb + .eabi_attribute Tag_conformance, "2.09" +@ CHECK: .eabi_attribute 67, "2.09" +@ Tag_conformance should be be emitted first in a file-scope +@ sub-subsection of the first public subsection of the attributes +@ section. 2.3.7.4 of ABI Addenda. +@ CHECK-OBJ: Tag: 67 +@ CHECK-OBJ-NEXT: TagName: conformance +@ CHECK-OBJ-NEXT: Value: 2.09 .eabi_attribute Tag_CPU_raw_name, "Cortex-A9" @ CHECK: .eabi_attribute 4, "Cortex-A9" @ CHECK-OBJ: Tag: 4 @ CHECK-OBJ-NEXT: TagName: CPU_raw_name -@ CHECK-OBJ-NEXT: Value: CORTEX-A9 +@ CHECK-OBJ-NEXT: Value: Cortex-A9 .eabi_attribute Tag_CPU_name, "cortex-a9" @ CHECK: .cpu cortex-a9 @ CHECK-OBJ: Tag: 5 @ CHECK-OBJ-NEXT: TagName: CPU_name -@ CHECK-OBJ-NEXT: Value: CORTEX-A9 +@ CHECK-OBJ-NEXT: Value: cortex-a9 .eabi_attribute Tag_CPU_arch, 10 @ CHECK: .eabi_attribute 6, 10 @ CHECK-OBJ: Tag: 6 @@ -165,12 +173,10 @@ @ CHECK-OBJ-NEXT: Value: 1 @ CHECK-OBJ-NEXT: TagName: ABI_FP_optimization_goals @ CHECK-OBJ-NEXT: Description: Speed - .eabi_attribute Tag_compatibility, 1 -@ CHECK: .eabi_attribute 32, 1 .eabi_attribute Tag_compatibility, 1, "aeabi" @ CHECK: .eabi_attribute 32, 1, "aeabi" @ CHECK-OBJ: Tag: 32 -@ CHECK-OBJ-NEXT: Value: 1, AEABI +@ CHECK-OBJ-NEXT: Value: 1, aeabi @ CHECK-OBJ-NEXT: TagName: compatibility @ CHECK-OBJ-NEXT: Description: AEABI Conformant .eabi_attribute Tag_CPU_unaligned_access, 0 @@ -213,18 +219,13 @@ @ CHECK: .eabi_attribute 65, "gnu" @ CHECK-OBJ: Tag: 65 @ CHECK-OBJ-NEXT: TagName: also_compatible_with -@ CHECK-OBJ-NEXT: Value: GNU +@ CHECK-OBJ-NEXT: Value: gnu .eabi_attribute Tag_T2EE_use, 0 @ CHECK: .eabi_attribute 66, 0 @ CHECK-OBJ: Tag: 66 @ CHECK-OBJ-NEXT: Value: 0 @ CHECK-OBJ-NEXT: TagName: T2EE_use @ CHECK-OBJ-NEXT: Description: Not Permitted - .eabi_attribute Tag_conformance, "2.09" -@ CHECK: .eabi_attribute 67, "2.09" -@ CHECK-OBJ: Tag: 67 -@ CHECK-OBJ-NEXT: TagName: conformance -@ CHECK-OBJ-NEXT: Value: 2.09 .eabi_attribute Tag_Virtualization_use, 0 @ CHECK: .eabi_attribute 68, 0 @ CHECK-OBJ: Tag: 68 diff --git a/test/MC/ARM/directive-fpu-diagnostics.s b/test/MC/ARM/directive-fpu-diagnostics.s new file mode 100644 index 0000000..67c6129 --- /dev/null +++ b/test/MC/ARM/directive-fpu-diagnostics.s @@ -0,0 +1,10 @@ +@ RUN: not llvm-mc -triple armv7 -filetype asm -o /dev/null %s 2>&1 \ +@ RUN: | FileCheck %s -strict-whitespace + + .text + .thumb + + .fpu invalid +@ CHECK: error: Unknown FPU name +@ CHECK: .fpu invalid +@ CHECK: ^ diff --git a/test/MC/ARM/dot-req.s b/test/MC/ARM/dot-req.s index 3b4cf5c..848c124 100644 --- a/test/MC/ARM/dot-req.s +++ b/test/MC/ARM/dot-req.s @@ -1,6 +1,9 @@ @ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s .syntax unified bar: +@ The line is duplicated on purpose, it is legal to redefine a req with +@ the same value. +fred .req r5 fred .req r5 mov r11, fred .unreq fred diff --git a/test/MC/ARM/ldr-pseudo-parse-errors.s b/test/MC/ARM/ldr-pseudo-parse-errors.s index 2e6114d..2516239 100644 --- a/test/MC/ARM/ldr-pseudo-parse-errors.s +++ b/test/MC/ARM/ldr-pseudo-parse-errors.s @@ -4,7 +4,7 @@ .text bar: mov r0, =0x101 -@ CHECK: error: unexpected token in operand +@ CHECK: error: unknown token in expression @ CHECK: mov r0, =0x101 @ CHECK: ^ diff --git a/test/MC/ARM/move-banked-regs.s b/test/MC/ARM/move-banked-regs.s index 3fac846..b3b91f5 100644 --- a/test/MC/ARM/move-banked-regs.s +++ b/test/MC/ARM/move-banked-regs.s @@ -8,13 +8,13 @@ mrs r11, r12_usr mrs r1, sp_usr mrs r2, lr_usr -@ CHECK-ARM: mrs r2, r8_usr @ encoding: [0x00,0x22,0x20,0xe1] -@ CHECK-ARM: mrs r3, r9_usr @ encoding: [0x00,0x32,0x21,0xe1] -@ CHECK-ARM: mrs r5, r10_usr @ encoding: [0x00,0x52,0x22,0xe1] -@ CHECK-ARM: mrs r7, r11_usr @ encoding: [0x00,0x72,0x23,0xe1] -@ CHECK-ARM: mrs r11, r12_usr @ encoding: [0x00,0xb2,0x24,0xe1] -@ CHECK-ARM: mrs r1, sp_usr @ encoding: [0x00,0x12,0x25,0xe1] -@ CHECK-ARM: mrs r2, lr_usr @ encoding: [0x00,0x22,0x26,0xe1] +@ CHECK-ARM: mrs r2, r8_usr @ encoding: [0x00,0x22,0x00,0xe1] +@ CHECK-ARM: mrs r3, r9_usr @ encoding: [0x00,0x32,0x01,0xe1] +@ CHECK-ARM: mrs r5, r10_usr @ encoding: [0x00,0x52,0x02,0xe1] +@ CHECK-ARM: mrs r7, r11_usr @ encoding: [0x00,0x72,0x03,0xe1] +@ CHECK-ARM: mrs r11, r12_usr @ encoding: [0x00,0xb2,0x04,0xe1] +@ CHECK-ARM: mrs r1, sp_usr @ encoding: [0x00,0x12,0x05,0xe1] +@ CHECK-ARM: mrs r2, lr_usr @ encoding: [0x00,0x22,0x06,0xe1] @ CHECK-THUMB: mrs r2, r8_usr @ encoding: [0xe0,0xf3,0x20,0x82] @ CHECK-THUMB: mrs r3, r9_usr @ encoding: [0xe1,0xf3,0x20,0x83] @ CHECK-THUMB: mrs r5, r10_usr @ encoding: [0xe2,0xf3,0x20,0x85] @@ -31,14 +31,14 @@ mrs r1, sp_fiq mrs r2, lr_fiq mrs r3, spsr_fiq -@ CHECK-ARM: mrs r2, r8_fiq @ encoding: [0x00,0x22,0x28,0xe1] -@ CHECK-ARM: mrs r3, r9_fiq @ encoding: [0x00,0x32,0x29,0xe1] -@ CHECK-ARM: mrs r5, r10_fiq @ encoding: [0x00,0x52,0x2a,0xe1] -@ CHECK-ARM: mrs r7, r11_fiq @ encoding: [0x00,0x72,0x2b,0xe1] -@ CHECK-ARM: mrs r11, r12_fiq @ encoding: [0x00,0xb2,0x2c,0xe1] -@ CHECK-ARM: mrs r1, sp_fiq @ encoding: [0x00,0x12,0x2d,0xe1] -@ CHECK-ARM: mrs r2, lr_fiq @ encoding: [0x00,0x22,0x2e,0xe1] -@ CHECK-ARM: mrs r3, SPSR_fiq @ encoding: [0x00,0x32,0x6e,0xe1] +@ CHECK-ARM: mrs r2, r8_fiq @ encoding: [0x00,0x22,0x08,0xe1] +@ CHECK-ARM: mrs r3, r9_fiq @ encoding: [0x00,0x32,0x09,0xe1] +@ CHECK-ARM: mrs r5, r10_fiq @ encoding: [0x00,0x52,0x0a,0xe1] +@ CHECK-ARM: mrs r7, r11_fiq @ encoding: [0x00,0x72,0x0b,0xe1] +@ CHECK-ARM: mrs r11, r12_fiq @ encoding: [0x00,0xb2,0x0c,0xe1] +@ CHECK-ARM: mrs r1, sp_fiq @ encoding: [0x00,0x12,0x0d,0xe1] +@ CHECK-ARM: mrs r2, lr_fiq @ encoding: [0x00,0x22,0x0e,0xe1] +@ CHECK-ARM: mrs r3, SPSR_fiq @ encoding: [0x00,0x32,0x4e,0xe1] @ CHECK-THUMB: mrs r2, r8_fiq @ encoding: [0xe8,0xf3,0x20,0x82] @ CHECK-THUMB: mrs r3, r9_fiq @ encoding: [0xe9,0xf3,0x20,0x83] @ CHECK-THUMB: mrs r5, r10_fiq @ encoding: [0xea,0xf3,0x20,0x85] @@ -51,9 +51,9 @@ mrs r4, lr_irq mrs r9, sp_irq mrs r1, spsr_irq -@ CHECK-ARM: mrs r4, lr_irq @ encoding: [0x00,0x43,0x20,0xe1] -@ CHECK-ARM: mrs r9, sp_irq @ encoding: [0x00,0x93,0x21,0xe1] -@ CHECK-ARM: mrs r1, SPSR_irq @ encoding: [0x00,0x13,0x60,0xe1] +@ CHECK-ARM: mrs r4, lr_irq @ encoding: [0x00,0x43,0x00,0xe1] +@ CHECK-ARM: mrs r9, sp_irq @ encoding: [0x00,0x93,0x01,0xe1] +@ CHECK-ARM: mrs r1, SPSR_irq @ encoding: [0x00,0x13,0x40,0xe1] @ CHECK-THUMB: mrs r4, lr_irq @ encoding: [0xe0,0xf3,0x30,0x84] @ CHECK-THUMB: mrs r9, sp_irq @ encoding: [0xe1,0xf3,0x30,0x89] @ CHECK-THUMB: mrs r1, SPSR_irq @ encoding: [0xf0,0xf3,0x30,0x81] @@ -61,9 +61,9 @@ mrs r1, lr_svc mrs r3, sp_svc mrs r5, spsr_svc -@ CHECK-ARM: mrs r1, lr_svc @ encoding: [0x00,0x13,0x22,0xe1] -@ CHECK-ARM: mrs r3, sp_svc @ encoding: [0x00,0x33,0x23,0xe1] -@ CHECK-ARM: mrs r5, SPSR_svc @ encoding: [0x00,0x53,0x62,0xe1] +@ CHECK-ARM: mrs r1, lr_svc @ encoding: [0x00,0x13,0x02,0xe1] +@ CHECK-ARM: mrs r3, sp_svc @ encoding: [0x00,0x33,0x03,0xe1] +@ CHECK-ARM: mrs r5, SPSR_svc @ encoding: [0x00,0x53,0x42,0xe1] @ CHECK-THUMB: mrs r1, lr_svc @ encoding: [0xe2,0xf3,0x30,0x81] @ CHECK-THUMB: mrs r3, sp_svc @ encoding: [0xe3,0xf3,0x30,0x83] @ CHECK-THUMB: mrs r5, SPSR_svc @ encoding: [0xf2,0xf3,0x30,0x85] @@ -71,9 +71,9 @@ mrs r5, lr_abt mrs r7, sp_abt mrs r9, spsr_abt -@ CHECK-ARM: mrs r5, lr_abt @ encoding: [0x00,0x53,0x24,0xe1] -@ CHECK-ARM: mrs r7, sp_abt @ encoding: [0x00,0x73,0x25,0xe1] -@ CHECK-ARM: mrs r9, SPSR_abt @ encoding: [0x00,0x93,0x64,0xe1] +@ CHECK-ARM: mrs r5, lr_abt @ encoding: [0x00,0x53,0x04,0xe1] +@ CHECK-ARM: mrs r7, sp_abt @ encoding: [0x00,0x73,0x05,0xe1] +@ CHECK-ARM: mrs r9, SPSR_abt @ encoding: [0x00,0x93,0x44,0xe1] @ CHECK-THUMB: mrs r5, lr_abt @ encoding: [0xe4,0xf3,0x30,0x85] @ CHECK-THUMB: mrs r7, sp_abt @ encoding: [0xe5,0xf3,0x30,0x87] @ CHECK-THUMB: mrs r9, SPSR_abt @ encoding: [0xf4,0xf3,0x30,0x89] @@ -81,9 +81,9 @@ mrs r9, lr_und mrs r11, sp_und mrs r12, spsr_und -@ CHECK-ARM: mrs r9, lr_und @ encoding: [0x00,0x93,0x26,0xe1] -@ CHECK-ARM: mrs r11, sp_und @ encoding: [0x00,0xb3,0x27,0xe1] -@ CHECK-ARM: mrs r12, SPSR_und @ encoding: [0x00,0xc3,0x66,0xe1] +@ CHECK-ARM: mrs r9, lr_und @ encoding: [0x00,0x93,0x06,0xe1] +@ CHECK-ARM: mrs r11, sp_und @ encoding: [0x00,0xb3,0x07,0xe1] +@ CHECK-ARM: mrs r12, SPSR_und @ encoding: [0x00,0xc3,0x46,0xe1] @ CHECK-THUMB: mrs r9, lr_und @ encoding: [0xe6,0xf3,0x30,0x89] @ CHECK-THUMB: mrs r11, sp_und @ encoding: [0xe7,0xf3,0x30,0x8b] @ CHECK-THUMB: mrs r12, SPSR_und @ encoding: [0xf6,0xf3,0x30,0x8c] @@ -92,9 +92,9 @@ mrs r2, lr_mon mrs r4, sp_mon mrs r6, spsr_mon -@ CHECK-ARM: mrs r2, lr_mon @ encoding: [0x00,0x23,0x2c,0xe1] -@ CHECK-ARM: mrs r4, sp_mon @ encoding: [0x00,0x43,0x2d,0xe1] -@ CHECK-ARM: mrs r6, SPSR_mon @ encoding: [0x00,0x63,0x6c,0xe1] +@ CHECK-ARM: mrs r2, lr_mon @ encoding: [0x00,0x23,0x0c,0xe1] +@ CHECK-ARM: mrs r4, sp_mon @ encoding: [0x00,0x43,0x0d,0xe1] +@ CHECK-ARM: mrs r6, SPSR_mon @ encoding: [0x00,0x63,0x4c,0xe1] @ CHECK-THUMB: mrs r2, lr_mon @ encoding: [0xec,0xf3,0x30,0x82] @ CHECK-THUMB: mrs r4, sp_mon @ encoding: [0xed,0xf3,0x30,0x84] @ CHECK-THUMB: mrs r6, SPSR_mon @ encoding: [0xfc,0xf3,0x30,0x86] @@ -103,9 +103,9 @@ mrs r6, elr_hyp mrs r8, sp_hyp mrs r10, spsr_hyp -@ CHECK-ARM: mrs r6, elr_hyp @ encoding: [0x00,0x63,0x2e,0xe1] -@ CHECK-ARM: mrs r8, sp_hyp @ encoding: [0x00,0x83,0x2f,0xe1] -@ CHECK-ARM: mrs r10, SPSR_hyp @ encoding: [0x00,0xa3,0x6e,0xe1] +@ CHECK-ARM: mrs r6, elr_hyp @ encoding: [0x00,0x63,0x0e,0xe1] +@ CHECK-ARM: mrs r8, sp_hyp @ encoding: [0x00,0x83,0x0f,0xe1] +@ CHECK-ARM: mrs r10, SPSR_hyp @ encoding: [0x00,0xa3,0x4e,0xe1] @ CHECK-THUMB: mrs r6, elr_hyp @ encoding: [0xee,0xf3,0x30,0x86] @ CHECK-THUMB: mrs r8, sp_hyp @ encoding: [0xef,0xf3,0x30,0x88] @ CHECK-THUMB: mrs r10, SPSR_hyp @ encoding: [0xfe,0xf3,0x30,0x8a] diff --git a/test/MC/ARM/pr22395-2.s b/test/MC/ARM/pr22395-2.s new file mode 100644 index 0000000..3d2a10d --- /dev/null +++ b/test/MC/ARM/pr22395-2.s @@ -0,0 +1,37 @@ +@ RUN: llvm-mc -triple armv4t-eabi -mattr +d16 -filetype asm -o - %s 2>&1 | FileCheck %s + + .text + .thumb + + .p2align 2 + + .fpu vfpv3 + vldmia r0, {d16-d31} +@ CHECK: vldmia r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31} +@ CHECK-NOT: error: register expected + + .fpu vfpv4 + vldmia r0, {d16-d31} +@ CHECK: vldmia r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31} +@ CHECK-NOT: error: register expected + + .fpu neon + vldmia r0, {d16-d31} +@ CHECK: vldmia r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31} +@ CHECK-NOT: error: register expected + + .fpu neon-vfpv4 + vldmia r0, {d16-d31} +@ CHECK: vldmia r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31} +@ CHECK-NOT: error: register expected + + .fpu neon-fp-armv8 + vldmia r0, {d16-d31} +@ CHECK: vldmia r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31} +@ CHECK-NOT: error: register expected + + .fpu crypto-neon-fp-armv8 + vldmia r0, {d16-d31} +@ CHECK: vldmia r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31} +@ CHECK-NOT: error: register expected + diff --git a/test/MC/ARM/pr22395.s b/test/MC/ARM/pr22395.s new file mode 100644 index 0000000..5da5d96 --- /dev/null +++ b/test/MC/ARM/pr22395.s @@ -0,0 +1,63 @@ +@ RUN: llvm-mc -triple armv4t-eabi -filetype asm -o - %s 2>&1 | FileCheck %s + + .text + .thumb + + .p2align 2 + + .fpu neon + vldmia r0, {d16-d31} + +@ CHECK: vldmia r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31} +@ CHECK-NOT: error: instruction requires: VFP2 + + .fpu vfpv3 + vadd.f32 s1, s2, s3 +@ CHECK: vadd.f32 s1, s2, s3 +@ CHECK-NOT: error: instruction requires: VPF2 + + .fpu vfpv3-d16 + vadd.f32 s1, s2, s3 +@ CHECK: vadd.f32 s1, s2, s3 +@ CHECK-NOT: error: instruction requires: VPF2 + + .fpu vfpv4 + vadd.f32 s1, s2, s3 +@ CHECK: vadd.f32 s1, s2, s3 +@ CHECK-NOT: error: instruction requires: VPF2 + + .fpu vfpv4-d16 + vadd.f32 s1, s2, s3 +@ CHECK: vadd.f32 s1, s2, s3 +@ CHECK-NOT: error: instruction requires: VPF2 + + .fpu fpv5-d16 + vadd.f32 s1, s2, s3 +@ CHECK: vadd.f32 s1, s2, s3 +@ CHECK-NOT: error: instruction requires: VPF2 + + .fpu fp-armv8 + vadd.f32 s1, s2, s3 +@ CHECK: vadd.f32 s1, s2, s3 +@ CHECK-NOT: error: instruction requires: VPF2 + + .fpu fp-armv8 + vadd.f32 s1, s2, s3 +@ CHECK: vadd.f32 s1, s2, s3 +@ CHECK-NOT: error: instruction requires: VPF2 + + .fpu neon + vadd.f32 s1, s2, s3 +@ CHECK: vadd.f32 s1, s2, s3 +@ CHECK-NOT: error: instruction requires: VPF2 + + .fpu neon-vfpv4 + vadd.f32 s1, s2, s3 +@ CHECK: vadd.f32 s1, s2, s3 +@ CHECK-NOT: error: instruction requires: VPF2 + + .fpu crypto-neon-fp-armv8 + vadd.f32 s1, s2, s3 +@ CHECK: vadd.f32 s1, s2, s3 +@ CHECK-NOT: error: instruction requires: VPF2 + diff --git a/test/MC/ARM/thumb-diagnostics.s b/test/MC/ARM/thumb-diagnostics.s index 2a79132..bd26d06 100644 --- a/test/MC/ARM/thumb-diagnostics.s +++ b/test/MC/ARM/thumb-diagnostics.s @@ -1,11 +1,11 @@ -@ RUN: not llvm-mc -triple=thumbv6-apple-darwin < %s 2> %t -@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s -@ RUN: not llvm-mc -triple=thumbv5-apple-darwin < %s 2> %t -@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V5 < %t %s -@ RUN: not llvm-mc -triple=thumbv7m < %s 2> %t -@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V7M < %t %s -@ RUN: not llvm-mc -triple=thumbv8 < %s 2> %t -@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V8 < %t %s +@ RUN: not llvm-mc -triple=thumbv6-apple-darwin -o /dev/null < %s 2>&1 \ +@ RUN: | FileCheck --check-prefix=CHECK-ERRORS %s +@ RUN: not llvm-mc -triple=thumbv5-apple-darwin -o /dev/null < %s 2>&1 \ +@ RUN: | FileCheck --check-prefix=CHECK-ERRORS-V5 %s +@ RUN: not llvm-mc -triple=thumbv7m -o /dev/null < %s 2>&1 \ +@ RUN: | FileCheck --check-prefix=CHECK-ERRORS-V7M %s +@ RUN: not llvm-mc -triple=thumbv8 -o /dev/null < %s 2>&1 \ +@ RUN: | FileCheck --check-prefix=CHECK-ERRORS-V8 %s @ Check for various assembly diagnostic messages on invalid input. @@ -83,25 +83,25 @@ error: invalid operand for instruction @ CHECK-ERRORS-V8: error: writeback register not allowed in register list @ CHECK-ERRORS-V8: ldmdb r2!, {r2, r3, r4} @ CHECK-ERRORS-V8: ^ -@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: error: SP may not be in the register list @ CHECK-ERRORS-V7M: ldm r0, {r2, sp} @ CHECK-ERRORS-V7M: ^ -@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: error: SP may not be in the register list @ CHECK-ERRORS-V7M: ldmia r0, {r2-r3, sp} @ CHECK-ERRORS-V7M: ^ -@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: error: SP may not be in the register list @ CHECK-ERRORS-V7M: ldmia r0!, {r2-r3, sp} @ CHECK-ERRORS-V7M: ^ -@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: error: SP may not be in the register list @ CHECK-ERRORS-V7M: ldmfd r2, {r1, r3-r6, sp} @ CHECK-ERRORS-V7M: ^ -@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: error: SP may not be in the register list @ CHECK-ERRORS-V7M: ldmfd r2!, {r1, r3-r6, sp} @ CHECK-ERRORS-V7M: ^ -@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: error: SP may not be in the register list @ CHECK-ERRORS-V7M: ldmdb r1, {r2, r3, sp} @ CHECK-ERRORS-V7M: ^ -@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: error: SP may not be in the register list @ CHECK-ERRORS-V7M: ldmdb r1!, {r2, r3, sp} @ CHECK-ERRORS-V7M: ^ @@ -137,16 +137,16 @@ error: invalid operand for instruction @ CHECK-ERRORS-V8: error: writeback register not allowed in register list @ CHECK-ERRORS-V8: stmdb r2!, {r0, r2} @ CHECK-ERRORS-V8: ^ -@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: error: SP may not be in the register list @ CHECK-ERRORS-V7M: stm r1!, {r2, sp} @ CHECK-ERRORS-V7M: ^ -@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: error: SP may not be in the register list @ CHECK-ERRORS-V7M: stmia r4!, {r0-r3, sp} @ CHECK-ERRORS-V7M: ^ -@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: error: SP may not be in the register list @ CHECK-ERRORS-V7M: stmdb r1, {r2, r3, sp} @ CHECK-ERRORS-V7M: ^ -@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: error: SP may not be in the register list @ CHECK-ERRORS-V7M: stmdb r1!, {r2, r3, sp} @ CHECK-ERRORS-V7M: ^ @@ -206,7 +206,7 @@ error: invalid operand for instruction @ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: add sp, sp, #512 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: error: instruction requires: arm-mode +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: add r2, sp, #1024 @ CHECK-ERRORS: ^ diff --git a/test/MC/ARM/thumb-load-store-multiple.s b/test/MC/ARM/thumb-load-store-multiple.s new file mode 100644 index 0000000..6958450 --- /dev/null +++ b/test/MC/ARM/thumb-load-store-multiple.s @@ -0,0 +1,100 @@ +@ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o - %s 2>&1 \ +@ RUN: | FileCheck %s +@ RUN: not llvm-mc -triple thumbv7a-eabi -filetype asm -o - %s 2>&1 \ +@ RUN: | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7A %s +@ RUN: not llvm-mc -triple thumbv7m-eabi -filetype asm -o - %s 2>&1 \ +@ RUN: | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s + + .syntax unified + .thumb + + .global ldm + .type ldm,%function +ldm: + ldm r0!, {r1, sp} +@ CHECK: error: SP may not be in the register list +@ CHECK: ldm r0!, {r1, sp} +@ CHECK: ^ + ldm r0!, {lr, pc} +@ CHECK: error: PC and LR may not be in the register list simultaneously +@ CHECK: ldm r0!, {lr, pc} +@ CHECK: ^ + itt eq + ldmeq r0!, {r1, pc} + ldmeq r0!, {r2, lr} +@ CHECK: error: instruction must be outside of IT block or the last instruction in an IT block +@ CHECK: ldmeq r0!, {r1, pc} +@ CHECK: ^ + + .global ldmdb + .type ldmdb,%function +ldmdb: + ldmdb r0!, {r1, sp} +@ CHECK: error: SP may not be in the register list + ldmdb r0!, {lr, pc} +@ error: PC and LR may not be in the register list simultaneously + itt eq + ldmeq r0!, {r1, pc} + ldmeq r0!, {r2, lr} +@ CHECK: error: instruction must be outside of IT block or the last instruction in an IT block +@ CHECK: ldmeq r0!, {r1, pc} +@ CHECK: ^ + + .global stm + .type stm,%function +stm: + stm r0!, {r1, sp} +@ CHECK: error: SP may not be in the register list + stm r0!, {r2, pc} +@ CHECK: error: PC may not be in the register list + stm r0!, {sp, pc} +@ CHECK: error: SP and PC may not be in the register list + + .global stmdb + .type stmdb,%function +stmdb: + stmdb r0!, {r1, sp} +@ CHECK: error: SP may not be in the register list + stmdb r0!, {r2, pc} +@ CHECK: error: PC may not be in the register list + stmdb r0!, {sp, pc} +@ CHECK: error: SP and PC may not be in the register list + + .global push + .type push,%function +push: + push {sp} +@ CHECK: error: SP may not be in the register list + push {pc} +@ CHECK: error: PC may not be in the register list + push {sp, pc} +@ CHECK: error: SP and PC may not be in the register list + + .global pop + .type pop,%function +pop: + pop {sp} +@ CHECK-V7M: error: SP may not be in the register list + pop {lr, pc} +@ CHECK: error: PC and LR may not be in the register list simultaneously +@ CHECK: pop {lr, pc} +@ CHECK: ^ + itt eq + popeq {r1, pc} + popeq {r2, lr} +@ CHECK: error: instruction must be outside of IT block or the last instruction in an IT block +@ CHECK: popeq {r1, pc} +@ CHECK: ^ + + .global valid + .type valid,%function +valid: + pop {sp} +@ CHECK-V7A: ldr sp, [sp], #4 + pop {sp, pc} +@ CHECK-V7A: pop.w {sp, pc} + push.w {r0} +@ CHECK: str r0, [sp, #-4] + pop.w {r0} +@ CHECK: ldr r0, [sp], #4 + diff --git a/test/MC/ARM/thumb2-diagnostics.s b/test/MC/ARM/thumb2-diagnostics.s index b2b14bc..8fd161c 100644 --- a/test/MC/ARM/thumb2-diagnostics.s +++ b/test/MC/ARM/thumb2-diagnostics.s @@ -87,4 +87,7 @@ foo2: @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction - +ssat r0, #1, r0, asr #32 +usat r0, #1, r0, asr #32 +@ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode +@ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode diff --git a/test/MC/ARM/thumb2-dsp-diag.s b/test/MC/ARM/thumb2-dsp-diag.s new file mode 100644 index 0000000..cb0e774 --- /dev/null +++ b/test/MC/ARM/thumb2-dsp-diag.s @@ -0,0 +1,24 @@ +; RUN: not llvm-mc -triple=thumbv7m < %s 2> %t +; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +sxtab r0, r0, r0 +sxtah r0, r0, r0 +sxtab16 r0, r0, r0 +sxtb16 r0, r0 +sxtb16 r0, r0, ror #8 +; CHECK-ERRORS: error: instruction requires: arm-mode +; CHECK-ERRORS: error: instruction requires: arm-mode +; CHECK-ERRORS: error: instruction requires: arm-mode +; CHECK-ERRORS: error: instruction requires: arm-mode +; CHECK-ERRORS: error: invalid operand for instruction + +uxtab r0, r0, r0 +uxtah r0, r0, r0 +uxtab16 r0, r0, r0 +uxtb16 r0, r0 +uxtb16 r0, r0, ror #8 +; CHECK-ERRORS: error: instruction requires: arm-mode +; CHECK-ERRORS: error: instruction requires: arm-mode +; CHECK-ERRORS: error: instruction requires: arm-mode +; CHECK-ERRORS: error: instruction requires: arm-mode +; CHECK-ERRORS: error: invalid operand for instruction diff --git a/test/MC/ARM/v8_IT_manual.s b/test/MC/ARM/v8_IT_manual.s index 4b63aa8..160e98c 100644 --- a/test/MC/ARM/v8_IT_manual.s +++ b/test/MC/ARM/v8_IT_manual.s @@ -554,11 +554,11 @@ pushge {r1, r3, r7} @ PUSH, encoding T2 (32-bit) @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block it ge -pushge {r1, r13, r7} +pushge {r1, r3, r7} @ PUSH, encoding T3 (32-bit) @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block it ge -pushge {r13} +pushge {r3} @ REV, encoding T1 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block @@ -614,9 +614,10 @@ stmge r1!, {r2, r3} @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block it ge stmge r1, {r2, r3} +@ STM, encoding T3 (32-bit) @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block it ge -stmge r1!, {r2, r13} +stmge r1!, {r2, r3} @ LDM, encoding T1 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block diff --git a/test/MC/ARM/virtexts-arm.s b/test/MC/ARM/virtexts-arm.s new file mode 100644 index 0000000..a67a8fe --- /dev/null +++ b/test/MC/ARM/virtexts-arm.s @@ -0,0 +1,42 @@ +# RUN: llvm-mc -triple armv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-ARM + + hvc #1 + hvc #7 + hvc #257 + hvc #65535 +# CHECK-ARM: [0x71,0x00,0x40,0xe1] +# CHECK-ARM: [0x77,0x00,0x40,0xe1] +# CHECK-ARM: [0x71,0x10,0x40,0xe1] +# CHECK-ARM: [0x7f,0xff,0x4f,0xe1] + + eret + ereteq + eretne + ereths + eretlo + eretmi + eretpl + eretvs + eretvc + erethi + eretls + eretge + eretlt + eretgt + eretle +# CHECK-ARM: [0x6e,0x00,0x60,0xe1] +# CHECK-ARM: [0x6e,0x00,0x60,0x01] +# CHECK-ARM: [0x6e,0x00,0x60,0x11] +# CHECK-ARM: [0x6e,0x00,0x60,0x21] +# CHECK-ARM: [0x6e,0x00,0x60,0x31] +# CHECK-ARM: [0x6e,0x00,0x60,0x41] +# CHECK-ARM: [0x6e,0x00,0x60,0x51] +# CHECK-ARM: [0x6e,0x00,0x60,0x61] +# CHECK-ARM: [0x6e,0x00,0x60,0x71] +# CHECK-ARM: [0x6e,0x00,0x60,0x81] +# CHECK-ARM: [0x6e,0x00,0x60,0x91] +# CHECK-ARM: [0x6e,0x00,0x60,0xa1] +# CHECK-ARM: [0x6e,0x00,0x60,0xb1] +# CHECK-ARM: [0x6e,0x00,0x60,0xc1] +# CHECK-ARM: [0x6e,0x00,0x60,0xd1] + diff --git a/test/MC/ARM/virtexts-thumb.s b/test/MC/ARM/virtexts-thumb.s new file mode 100644 index 0000000..d911e1d --- /dev/null +++ b/test/MC/ARM/virtexts-thumb.s @@ -0,0 +1,59 @@ +# RUN: llvm-mc -triple thumbv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-THUMB + + hvc #1 + hvc #7 + hvc #257 + hvc #65535 +# CHECK-THUMB: [0xe0,0xf7,0x01,0x80] +# CHECK-THUMB: [0xe0,0xf7,0x07,0x80] +# CHECK-THUMB: [0xe0,0xf7,0x01,0x81] +# CHECK-THUMB: [0xef,0xf7,0xff,0x8f] + + hvc.w #1 + hvc.w #7 + hvc.w #257 + hvc.w #65535 +# CHECK-THUMB: [0xe0,0xf7,0x01,0x80] +# CHECK-THUMB: [0xe0,0xf7,0x07,0x80] +# CHECK-THUMB: [0xe0,0xf7,0x01,0x81] +# CHECK-THUMB: [0xef,0xf7,0xff,0x8f] + + eret + it eq; ereteq + it ne; eretne + it hs; ereths + it lo; eretlo + it mi; eretmi + it pl; eretpl + it vs; eretvs + it vc; eretvc + it hi; erethi + it ls; eretls + it ge; eretge + it lt; eretlt + it gt; eretgt + it le; eretle +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] + +# SUBS PC, LR, #0 should have the same encoding as ERET. +# The conditional forms can't be tested becuse the ARM assembler parser doesn't +# accept SUBS<cond> PC, LR, #<imm>, only the unconditonal form is allowed. This +# is due to the way that the custom parser handles optional operands; see the +# FIXME in ARM/AsmParser/ARMAsmParser.cpp. + + subs pc, lr, #0 +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] |