diff options
Diffstat (limited to 'test/MC/Disassembler/AArch64')
25 files changed, 5451 insertions, 1274 deletions
diff --git a/test/MC/Disassembler/AArch64/a64-ignored-fields.txt b/test/MC/Disassembler/AArch64/a64-ignored-fields.txt index 799ecdf..1860bf6 100644 --- a/test/MC/Disassembler/AArch64/a64-ignored-fields.txt +++ b/test/MC/Disassembler/AArch64/a64-ignored-fields.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s # The "Rm" bits are ignored, but the canonical representation has them filled # with 0s. This is what we should produce even if the input bit-pattern had diff --git a/test/MC/Disassembler/AArch64/arm64-advsimd.txt b/test/MC/Disassembler/AArch64/arm64-advsimd.txt new file mode 100644 index 0000000..cceee67 --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-advsimd.txt @@ -0,0 +1,2283 @@ +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 --disassemble < %s | FileCheck %s + +0x00 0xb8 0x20 0x0e +0x00 0xb8 0x20 0x4e +0x00 0xb8 0x60 0x0e +0x00 0xb8 0x60 0x4e +0x00 0xb8 0xa0 0x0e +0x00 0xb8 0xa0 0x4e + +# CHECK: abs.8b v0, v0 +# CHECK: abs.16b v0, v0 +# CHECK: abs.4h v0, v0 +# CHECK: abs.8h v0, v0 +# CHECK: abs.2s v0, v0 +# CHECK: abs.4s v0, v0 + +0x00 0x84 0x20 0x0e +0x00 0x84 0x20 0x4e +0x00 0x84 0x60 0x0e +0x00 0x84 0x60 0x4e +0x00 0x84 0xa0 0x0e +0x00 0x84 0xa0 0x4e +0x00 0x84 0xe0 0x4e + +# CHECK: add.8b v0, v0, v0 +# CHECK: add.16b v0, v0, v0 +# CHECK: add.4h v0, v0, v0 +# CHECK: add.8h v0, v0, v0 +# CHECK: add.2s v0, v0, v0 +# CHECK: add.4s v0, v0, v0 +# CHECK: add.2d v0, v0, v0 + +0x41 0x84 0xe3 0x5e + +# CHECK: add d1, d2, d3 + +0x00 0x40 0x20 0x0e +0x00 0x40 0x20 0x4e +0x00 0x40 0x60 0x0e +0x00 0x40 0x60 0x4e +0x00 0x40 0xa0 0x0e +0x00 0x40 0xa0 0x4e + +# CHECK: addhn.8b v0, v0, v0 +# CHECK: addhn2.16b v0, v0, v0 +# CHECK: addhn.4h v0, v0, v0 +# CHECK: addhn2.8h v0, v0, v0 +# CHECK: addhn.2s v0, v0, v0 +# CHECK: addhn2.4s v0, v0, v0 + +0x00 0xbc 0x20 0x0e +0x00 0xbc 0x20 0x4e +0x00 0xbc 0x60 0x0e +0x00 0xbc 0x60 0x4e +0x00 0xbc 0xa0 0x0e +0x00 0xbc 0xa0 0x4e +0x00 0xbc 0xe0 0x4e + +# CHECK: addp.8b v0, v0, v0 +# CHECK: addp.16b v0, v0, v0 +# CHECK: addp.4h v0, v0, v0 +# CHECK: addp.8h v0, v0, v0 +# CHECK: addp.2s v0, v0, v0 +# CHECK: addp.4s v0, v0, v0 +# CHECK: addp.2d v0, v0, v0 + +0x00 0xb8 0xf1 0x5e + +# CHECK: addp.2d d0, v0 + +0x00 0xb8 0x31 0x0e +0x00 0xb8 0x31 0x4e +0x00 0xb8 0x71 0x0e +0x00 0xb8 0x71 0x4e +0x00 0xb8 0xb1 0x4e + +# CHECK: addv.8b b0, v0 +# CHECK: addv.16b b0, v0 +# CHECK: addv.4h h0, v0 +# CHECK: addv.8h h0, v0 +# CHECK: addv.4s s0, v0 + + +# INS/DUP +0x60 0x0c 0x08 0x4e +0x60 0x0c 0x04 0x4e +0x60 0x0c 0x04 0x0e +0x60 0x0c 0x02 0x4e +0x60 0x0c 0x02 0x0e +0x60 0x0c 0x01 0x4e +0x60 0x0c 0x01 0x0e + +# CHECK: dup.2d v0, x3 +# CHECK: dup.4s v0, w3 +# CHECK: dup.2s v0, w3 +# CHECK: dup.8h v0, w3 +# CHECK: dup.4h v0, w3 +# CHECK: dup.16b v0, w3 +# CHECK: dup.8b v0, w3 + +0x60 0x04 0x18 0x4e +0x60 0x04 0x0c 0x0e +0x60 0x04 0x0c 0x4e +0x60 0x04 0x06 0x0e +0x60 0x04 0x06 0x4e +0x60 0x04 0x03 0x0e +0x60 0x04 0x03 0x4e + +# CHECK: dup.2d v0, v3[1] +# CHECK: dup.2s v0, v3[1] +# CHECK: dup.4s v0, v3[1] +# CHECK: dup.4h v0, v3[1] +# CHECK: dup.8h v0, v3[1] +# CHECK: dup.8b v0, v3[1] +# CHECK: dup.16b v0, v3[1] + + +0x43 0x2c 0x14 0x4e +0x43 0x2c 0x14 0x4e +0x43 0x3c 0x14 0x0e +0x43 0x3c 0x14 0x0e +0x43 0x3c 0x18 0x4e +0x43 0x3c 0x18 0x4e + +# CHECK: smov.s x3, v2[2] +# CHECK: smov.s x3, v2[2] +# CHECK: mov.s w3, v2[2] +# CHECK: mov.s w3, v2[2] +# CHECK: mov.d x3, v2[1] +# CHECK: mov.d x3, v2[1] + +0xa2 0x1c 0x18 0x4e +0xa2 0x1c 0x0c 0x4e +0xa2 0x1c 0x06 0x4e +0xa2 0x1c 0x03 0x4e + +0xa2 0x1c 0x18 0x4e +0xa2 0x1c 0x0c 0x4e +0xa2 0x1c 0x06 0x4e +0xa2 0x1c 0x03 0x4e + +# CHECK: ins.d v2[1], x5 +# CHECK: ins.s v2[1], w5 +# CHECK: ins.h v2[1], w5 +# CHECK: ins.b v2[1], w5 + +# CHECK: ins.d v2[1], x5 +# CHECK: ins.s v2[1], w5 +# CHECK: ins.h v2[1], w5 +# CHECK: ins.b v2[1], w5 + +0xe2 0x45 0x18 0x6e +0xe2 0x25 0x0c 0x6e +0xe2 0x15 0x06 0x6e +0xe2 0x0d 0x03 0x6e + +0xe2 0x05 0x18 0x6e +0xe2 0x45 0x1c 0x6e +0xe2 0x35 0x1e 0x6e +0xe2 0x2d 0x15 0x6e + +# CHECK: ins.d v2[1], v15[1] +# CHECK: ins.s v2[1], v15[1] +# CHECK: ins.h v2[1], v15[1] +# CHECK: ins.b v2[1], v15[1] + +# CHECK: ins.d v2[1], v15[0] +# CHECK: ins.s v2[3], v15[2] +# CHECK: ins.h v2[7], v15[3] +# CHECK: ins.b v2[10], v15[5] + +0x00 0x1c 0x20 0x0e +0x00 0x1c 0x20 0x4e + +# CHECK: and.8b v0, v0, v0 +# CHECK: and.16b v0, v0, v0 + +0x00 0x1c 0x60 0x0e + +# CHECK: bic.8b v0, v0, v0 + +0x00 0x8c 0x20 0x2e +0x00 0x3c 0x20 0x0e +0x00 0x34 0x20 0x0e +0x00 0x34 0x20 0x2e +0x00 0x3c 0x20 0x2e +0x00 0x8c 0x20 0x0e +0x00 0xd4 0xa0 0x2e +0x00 0xec 0x20 0x2e +0x00 0xec 0xa0 0x2e +0x00 0xd4 0x20 0x2e +0x00 0xd4 0x20 0x0e +0x00 0xe4 0x20 0x0e +0x00 0xe4 0x20 0x2e +0x00 0xe4 0xa0 0x2e +0x00 0xfc 0x20 0x2e +0x00 0xc4 0x20 0x2e +0x00 0xc4 0x20 0x0e +0x00 0xf4 0x20 0x2e +0x00 0xf4 0x20 0x0e +0x00 0xc4 0xa0 0x2e +0x00 0xc4 0xa0 0x0e +0x00 0xf4 0xa0 0x2e +0x00 0xf4 0xa0 0x0e +0x00 0xcc 0x20 0x0e +0x00 0xcc 0xa0 0x0e +0x00 0xdc 0x20 0x0e +0x00 0xdc 0x20 0x2e +0x00 0xfc 0x20 0x0e +0x00 0xfc 0xa0 0x0e +0x00 0xd4 0xa0 0x0e +0x00 0x94 0x20 0x0e +0x00 0x94 0x20 0x2e +0x00 0x9c 0x20 0x0e +0x00 0x9c 0x20 0x2e +0x00 0x7c 0x20 0x0e +0x00 0x74 0x20 0x0e +0x00 0x04 0x20 0x0e +0x00 0x24 0x20 0x0e +0x00 0xa4 0x20 0x0e +0x00 0x64 0x20 0x0e +0x00 0xac 0x20 0x0e +0x00 0x6c 0x20 0x0e +0x00 0x0c 0x20 0x0e +0x00 0xb4 0x60 0x0e +0x00 0xb4 0x60 0x2e +0x00 0x5c 0x20 0x0e +0x00 0x4c 0x20 0x0e +0x00 0x2c 0x20 0x0e +0x00 0x14 0x20 0x0e +0x00 0x54 0x20 0x0e +0x00 0x44 0x20 0x0e +0x00 0x84 0x20 0x2e +0x00 0x7c 0x20 0x2e +0x00 0x74 0x20 0x2e +0x00 0x04 0x20 0x2e +0x00 0x24 0x20 0x2e +0x00 0xa4 0x20 0x2e +0x00 0x64 0x20 0x2e +0x00 0xac 0x20 0x2e +0x00 0x6c 0x20 0x2e +0x00 0x0c 0x20 0x2e +0x00 0x5c 0x20 0x2e +0x00 0x4c 0x20 0x2e +0x00 0x2c 0x20 0x2e +0x00 0x14 0x20 0x2e +0x00 0x54 0x20 0x2e +0x00 0x44 0x20 0x2e + +# CHECK: cmeq.8b v0, v0, v0 +# CHECK: cmge.8b v0, v0, v0 +# CHECK: cmgt.8b v0, v0, v0 +# CHECK: cmhi.8b v0, v0, v0 +# CHECK: cmhs.8b v0, v0, v0 +# CHECK: cmtst.8b v0, v0, v0 +# CHECK: fabd.2s v0, v0, v0 +# CHECK: facge.2s v0, v0, v0 +# CHECK: facgt.2s v0, v0, v0 +# CHECK: faddp.2s v0, v0, v0 +# CHECK: fadd.2s v0, v0, v0 +# CHECK: fcmeq.2s v0, v0, v0 +# CHECK: fcmge.2s v0, v0, v0 +# CHECK: fcmgt.2s v0, v0, v0 +# CHECK: fdiv.2s v0, v0, v0 +# CHECK: fmaxnmp.2s v0, v0, v0 +# CHECK: fmaxnm.2s v0, v0, v0 +# CHECK: fmaxp.2s v0, v0, v0 +# CHECK: fmax.2s v0, v0, v0 +# CHECK: fminnmp.2s v0, v0, v0 +# CHECK: fminnm.2s v0, v0, v0 +# CHECK: fminp.2s v0, v0, v0 +# CHECK: fmin.2s v0, v0, v0 +# CHECK: fmla.2s v0, v0, v0 +# CHECK: fmls.2s v0, v0, v0 +# CHECK: fmulx.2s v0, v0, v0 +# CHECK: fmul.2s v0, v0, v0 +# CHECK: frecps.2s v0, v0, v0 +# CHECK: frsqrts.2s v0, v0, v0 +# CHECK: fsub.2s v0, v0, v0 +# CHECK: mla.8b v0, v0, v0 +# CHECK: mls.8b v0, v0, v0 +# CHECK: mul.8b v0, v0, v0 +# CHECK: pmul.8b v0, v0, v0 +# CHECK: saba.8b v0, v0, v0 +# CHECK: sabd.8b v0, v0, v0 +# CHECK: shadd.8b v0, v0, v0 +# CHECK: shsub.8b v0, v0, v0 +# CHECK: smaxp.8b v0, v0, v0 +# CHECK: smax.8b v0, v0, v0 +# CHECK: sminp.8b v0, v0, v0 +# CHECK: smin.8b v0, v0, v0 +# CHECK: sqadd.8b v0, v0, v0 +# CHECK: sqdmulh.4h v0, v0, v0 +# CHECK: sqrdmulh.4h v0, v0, v0 +# CHECK: sqrshl.8b v0, v0, v0 +# CHECK: sqshl.8b v0, v0, v0 +# CHECK: sqsub.8b v0, v0, v0 +# CHECK: srhadd.8b v0, v0, v0 +# CHECK: srshl.8b v0, v0, v0 +# CHECK: sshl.8b v0, v0, v0 +# CHECK: sub.8b v0, v0, v0 +# CHECK: uaba.8b v0, v0, v0 +# CHECK: uabd.8b v0, v0, v0 +# CHECK: uhadd.8b v0, v0, v0 +# CHECK: uhsub.8b v0, v0, v0 +# CHECK: umaxp.8b v0, v0, v0 +# CHECK: umax.8b v0, v0, v0 +# CHECK: uminp.8b v0, v0, v0 +# CHECK: umin.8b v0, v0, v0 +# CHECK: uqadd.8b v0, v0, v0 +# CHECK: uqrshl.8b v0, v0, v0 +# CHECK: uqshl.8b v0, v0, v0 +# CHECK: uqsub.8b v0, v0, v0 +# CHECK: urhadd.8b v0, v0, v0 +# CHECK: urshl.8b v0, v0, v0 +# CHECK: ushl.8b v0, v0, v0 + +0x00 0x1c 0xe0 0x2e +0x00 0x1c 0xa0 0x2e +0x00 0x1c 0x60 0x2e +0x00 0x1c 0x20 0x2e +0x00 0x1c 0xe0 0x0e +0x00 0x1c 0xa1 0x0e + +# CHECK: bif.8b v0, v0, v0 +# CHECK: bit.8b v0, v0, v0 +# CHECK: bsl.8b v0, v0, v0 +# CHECK: eor.8b v0, v0, v0 +# CHECK: orn.8b v0, v0, v0 +# CHECK: orr.8b v0, v0, v1 + +0x00 0x68 0x20 0x0e +0x00 0x68 0x20 0x4e +0x00 0x68 0x60 0x0e +0x00 0x68 0x60 0x4e +0x00 0x68 0xa0 0x0e +0x00 0x68 0xa0 0x4e + +# CHECK: sadalp.4h v0, v0 +# CHECK: sadalp.8h v0, v0 +# CHECK: sadalp.2s v0, v0 +# CHECK: sadalp.4s v0, v0 +# CHECK: sadalp.1d v0, v0 +# CHECK: sadalp.2d v0, v0 + +0x00 0x48 0x20 0x0e +0x00 0x48 0x20 0x2e +0x00 0x58 0x20 0x0e +0x00 0xf8 0xa0 0x0e +0x00 0xc8 0x21 0x0e +0x00 0xc8 0x21 0x2e +0x00 0xb8 0x21 0x0e +0x00 0xb8 0x21 0x2e +0x00 0xa8 0x21 0x0e +0x00 0xa8 0x21 0x2e +0x00 0xa8 0xa1 0x0e +0x00 0xa8 0xa1 0x2e +0x00 0xb8 0xa1 0x0e +0x00 0xb8 0xa1 0x2e +0x00 0xf8 0xa0 0x2e +0x00 0xd8 0xa1 0x0e +0x00 0xd8 0xa1 0x2e +0x00 0xf8 0xa1 0x2e +0x00 0xb8 0x20 0x2e +0x00 0x58 0x20 0x2e +0x00 0x58 0x60 0x2e +0x00 0x18 0x20 0x0e +0x00 0x08 0x20 0x2e +0x00 0x08 0x20 0x0e +0x00 0x68 0x20 0x0e +0x00 0x28 0x20 0x0e +0x00 0xd8 0x21 0x0e +0x00 0x38 0x21 0x2e +0x00 0x78 0x20 0x0e +0x00 0x78 0x20 0x2e +0x00 0x48 0x21 0x0e +0x00 0x28 0x21 0x2e +0x00 0x38 0x20 0x0e +0x00 0x68 0x20 0x2e +0x00 0x28 0x20 0x2e +0x00 0xd8 0x21 0x2e +0x00 0x48 0x21 0x2e +0x00 0xc8 0xa1 0x0e +0x00 0xc8 0xa1 0x2e +0x00 0x38 0x20 0x2e +0x00 0x28 0x21 0x0e +0x00 0x48 0x20 0x0e +0x00 0x48 0x20 0x2e +0x00 0x58 0x20 0x0e +0x00 0xf8 0xa0 0x0e +0x00 0xc8 0x21 0x0e +0x00 0xc8 0x21 0x2e +0x00 0xb8 0x21 0x0e +0x00 0xb8 0x21 0x2e +0x00 0xa8 0x21 0x0e +0x00 0xa8 0x21 0x2e +0x00 0xa8 0xa1 0x0e +0x00 0xa8 0xa1 0x2e +0x00 0xb8 0xa1 0x0e +0x00 0xb8 0xa1 0x2e +0x00 0xf8 0xa0 0x2e +0x00 0xd8 0xa1 0x0e +0x00 0xd8 0xa1 0x2e +0x00 0xf8 0xa1 0x2e +0x00 0xb8 0x20 0x2e +0x00 0x58 0x20 0x2e +0x00 0x58 0x60 0x2e +0x00 0x18 0x20 0x0e +0x00 0x08 0x20 0x2e +0x00 0x08 0x20 0x0e +0x00 0x68 0x20 0x0e +0x00 0x28 0x20 0x0e +0x00 0xd8 0x21 0x0e +0x00 0x38 0x21 0x2e +0x00 0x78 0x20 0x0e +0x00 0x78 0x20 0x2e +0x00 0x48 0x21 0x0e +0x00 0x28 0x21 0x2e +0x00 0x38 0x20 0x0e +0x00 0x68 0x20 0x2e +0x00 0x28 0x20 0x2e +0x00 0xd8 0x21 0x2e +0x00 0x48 0x21 0x2e +0x00 0xc8 0xa1 0x0e +0x00 0xc8 0xa1 0x2e +0x00 0x38 0x20 0x2e +0x00 0x28 0x21 0x0e + +# CHECK: cls.8b v0, v0 +# CHECK: clz.8b v0, v0 +# CHECK: cnt.8b v0, v0 +# CHECK: fabs.2s v0, v0 +# CHECK: fcvtas.2s v0, v0 +# CHECK: fcvtau.2s v0, v0 +# CHECK: fcvtms.2s v0, v0 +# CHECK: fcvtmu.2s v0, v0 +# CHECK: fcvtns.2s v0, v0 +# CHECK: fcvtnu.2s v0, v0 +# CHECK: fcvtps.2s v0, v0 +# CHECK: fcvtpu.2s v0, v0 +# CHECK: fcvtzs.2s v0, v0 +# CHECK: fcvtzu.2s v0, v0 +# CHECK: fneg.2s v0, v0 +# CHECK: frecpe.2s v0, v0 +# CHECK: frsqrte.2s v0, v0 +# CHECK: fsqrt.2s v0, v0 +# CHECK: neg.8b v0, v0 +# CHECK: mvn.8b v0, v0 +# CHECK: rbit.8b v0, v0 +# CHECK: rev16.8b v0, v0 +# CHECK: rev32.8b v0, v0 +# CHECK: rev64.8b v0, v0 +# CHECK: sadalp.4h v0, v0 +# CHECK: saddlp.4h v0, v0 +# CHECK: scvtf.2s v0, v0 +# CHECK: shll.8h v0, v0, #8 +# CHECK: sqabs.8b v0, v0 +# CHECK: sqneg.8b v0, v0 +# CHECK: sqxtn.8b v0, v0 +# CHECK: sqxtun.8b v0, v0 +# CHECK: suqadd.8b v0, v0 +# CHECK: uadalp.4h v0, v0 +# CHECK: uaddlp.4h v0, v0 +# CHECK: ucvtf.2s v0, v0 +# CHECK: uqxtn.8b v0, v0 +# CHECK: urecpe.2s v0, v0 +# CHECK: ursqrte.2s v0, v0 +# CHECK: usqadd.8b v0, v0 +# CHECK: xtn.8b v0, v0 + +0x00 0x98 0x20 0x0e +0x00 0x98 0x20 0x4e +0x00 0x98 0x60 0x0e +0x00 0x98 0x60 0x4e +0x00 0x98 0xa0 0x0e +0x00 0x98 0xa0 0x4e +0x00 0x98 0xe0 0x4e + +# CHECK: cmeq.8b v0, v0, #0 +# CHECK: cmeq.16b v0, v0, #0 +# CHECK: cmeq.4h v0, v0, #0 +# CHECK: cmeq.8h v0, v0, #0 +# CHECK: cmeq.2s v0, v0, #0 +# CHECK: cmeq.4s v0, v0, #0 +# CHECK: cmeq.2d v0, v0, #0 + +0x00 0x88 0x20 0x2e +0x00 0x88 0x20 0x0e +0x00 0x98 0x20 0x2e +0x00 0xa8 0x20 0x0e +0x00 0xd8 0xa0 0x0e +0x00 0xc8 0xa0 0x2e +0x00 0xc8 0xa0 0x0e +0x00 0xd8 0xa0 0x2e +0x00 0xe8 0xa0 0x0e + +# CHECK: cmge.8b v0, v0, #0 +# CHECK: cmgt.8b v0, v0, #0 +# CHECK: cmle.8b v0, v0, #0 +# CHECK: cmlt.8b v0, v0, #0 +# CHECK: fcmeq.2s v0, v0, #0 +# CHECK: fcmge.2s v0, v0, #0 +# CHECK: fcmgt.2s v0, v0, #0 +# CHECK: fcmle.2s v0, v0, #0 +# CHECK: fcmlt.2s v0, v0, #0 + +0x00 0x78 0x21 0x0e +0x00 0x78 0x21 0x4e +0x00 0x78 0x61 0x0e +0x00 0x78 0x61 0x4e +0x00 0x68 0x21 0x0e +0x00 0x68 0x21 0x4e +0x00 0x68 0x61 0x0e +0x00 0x68 0x61 0x4e +0x00 0x68 0x61 0x2e +0x00 0x68 0x61 0x6e + +# CHECK: fcvtl v0.4s, v0.4h +# CHECK: fcvtl2 v0.4s, v0.8h +# CHECK: fcvtl v0.2d, v0.2s +# CHECK: fcvtl2 v0.2d, v0.4s +# CHECK: fcvtn v0.4h, v0.4s +# CHECK: fcvtn2 v0.8h, v0.4s +# CHECK: fcvtn v0.2s, v0.2d +# CHECK: fcvtn2 v0.4s, v0.2d +# CHECK: fcvtxn v0.2s, v0.2d +# CHECK: fcvtxn2 v0.4s, v0.2d + +#===-------------------------------------------------------------------------=== +# AdvSIMD modified immediate instructions +#===-------------------------------------------------------------------------=== + +0x20 0x14 0x00 0x2f +0x20 0x34 0x00 0x2f +0x20 0x54 0x00 0x2f +0x20 0x74 0x00 0x2f + +# CHECK: bic.2s v0, #0x1 +# CHECK: bic.2s v0, #0x1, lsl #8 +# CHECK: bic.2s v0, #0x1, lsl #16 +# CHECK: bic.2s v0, #0x1, lsl #24 + +0x20 0x94 0x00 0x2f +0x20 0x94 0x00 0x2f +0x20 0xb4 0x00 0x2f + +# CHECK: bic.4h v0, #0x1 +# CHECK: bic.4h v0, #0x1 +# FIXME: bic.4h v0, #0x1, lsl #8 +# 'bic.4h' should be selected over "fcvtnu.2s v0, v1, #0" + +0x20 0x14 0x00 0x6f +0x20 0x34 0x00 0x6f +0x20 0x54 0x00 0x6f +0x20 0x74 0x00 0x6f + +# CHECK: bic.4s v0, #0x1 +# CHECK: bic.4s v0, #0x1, lsl #8 +# CHECK: bic.4s v0, #0x1, lsl #16 +# CHECK: bic.4s v0, #0x1, lsl #24 + +0x20 0x94 0x00 0x6f +0x20 0xb4 0x00 0x6f + +# CHECK: bic.8h v0, #0x1 +# FIXME: bic.8h v0, #0x1, lsl #8 +# "bic.8h" should be selected over "fcvtnu.4s v0, v1, #0" + +0x00 0xf4 0x02 0x6f + +# CHECK: fmov.2d v0, #0.12500000 + +0x00 0xf4 0x02 0x0f +0x00 0xf4 0x02 0x4f + +# CHECK: fmov.2s v0, #0.12500000 +# CHECK: fmov.4s v0, #0.12500000 + +0x20 0x14 0x00 0x0f +0x20 0x34 0x00 0x0f +0x20 0x54 0x00 0x0f +0x20 0x74 0x00 0x0f + +# CHECK: orr.2s v0, #0x1 +# CHECK: orr.2s v0, #0x1, lsl #8 +# CHECK: orr.2s v0, #0x1, lsl #16 +# CHECK: orr.2s v0, #0x1, lsl #24 + +0x20 0x94 0x00 0x0f +0x20 0xb4 0x00 0x0f + +# CHECK: orr.4h v0, #0x1 +# FIXME: orr.4h v0, #0x1, lsl #8 +# 'orr.4h' should be selected over "fcvtns.2s v0, v1, #0" + +0x20 0x14 0x00 0x4f +0x20 0x34 0x00 0x4f +0x20 0x54 0x00 0x4f +0x20 0x74 0x00 0x4f + +# CHECK: orr.4s v0, #0x1 +# CHECK: orr.4s v0, #0x1, lsl #8 +# CHECK: orr.4s v0, #0x1, lsl #16 +# CHECK: orr.4s v0, #0x1, lsl #24 + +0x20 0x94 0x00 0x4f +0x20 0xb4 0x00 0x4f + +# CHECK: orr.8h v0, #0x1 +# CHECK: orr.8h v0, #0x1, lsl #8 + +0x21 0x70 0x40 0x0c +0x42 0xa0 0x40 0x4c +0x64 0x64 0x40 0x0c +0x87 0x24 0x40 0x4c +0x0c 0xa8 0x40 0x0c +0x0a 0x68 0x40 0x4c +0x2d 0xac 0x40 0x0c +0x4f 0x7c 0x40 0x4c +0xe0 0x03 0x40 0x0d + +# CHECK: ld1.8b { v1 }, [x1] +# CHECK: ld1.16b { v2, v3 }, [x2] +# CHECK: ld1.4h { v4, v5, v6 }, [x3] +# CHECK: ld1.8h { v7, v8, v9, v10 }, [x4] +# CHECK: ld1.2s { v12, v13 }, [x0] +# CHECK: ld1.4s { v10, v11, v12 }, [x0] +# CHECK: ld1.1d { v13, v14 }, [x1] +# CHECK: ld1.2d { v15 }, [x2] +# CHECK: ld1.b { v0 }[0], [sp] + +0x41 0x70 0xdf 0x0c +0x41 0xa0 0xdf 0x0c +0x41 0x60 0xdf 0x0c +0x41 0x20 0xdf 0x0c +0x42 0x70 0xdf 0x4c +0x42 0xa0 0xdf 0x4c +0x42 0x60 0xdf 0x4c +0x42 0x20 0xdf 0x4c +0x64 0x74 0xdf 0x0c +0x64 0xa4 0xdf 0x0c +0x64 0x64 0xdf 0x0c +0x64 0x24 0xdf 0x0c +0x87 0x74 0xdf 0x4c +0x87 0xa4 0xdf 0x4c +0x87 0x64 0xdf 0x4c +0x87 0x24 0xdf 0x4c +0x0c 0x78 0xdf 0x0c +0x0c 0xa8 0xdf 0x0c +0x0c 0x68 0xdf 0x0c +0x0c 0x28 0xdf 0x0c +0x0a 0x78 0xdf 0x4c +0x0a 0xa8 0xdf 0x4c +0x0a 0x68 0xdf 0x4c +0x0a 0x28 0xdf 0x4c +0x2d 0x7c 0xdf 0x0c +0x2d 0xac 0xdf 0x0c +0x2d 0x6c 0xdf 0x0c +0x2d 0x2c 0xdf 0x0c +0x4f 0x7c 0xdf 0x4c +0x4f 0xac 0xdf 0x4c +0x4f 0x6c 0xdf 0x4c +0x4f 0x2c 0xdf 0x4c + +# CHECK: ld1.8b { v1 }, [x2], #8 +# CHECK: ld1.8b { v1, v2 }, [x2], #16 +# CHECK: ld1.8b { v1, v2, v3 }, [x2], #24 +# CHECK: ld1.8b { v1, v2, v3, v4 }, [x2], #32 +# CHECK: ld1.16b { v2 }, [x2], #16 +# CHECK: ld1.16b { v2, v3 }, [x2], #32 +# CHECK: ld1.16b { v2, v3, v4 }, [x2], #48 +# CHECK: ld1.16b { v2, v3, v4, v5 }, [x2], #64 +# CHECK: ld1.4h { v4 }, [x3], #8 +# CHECK: ld1.4h { v4, v5 }, [x3], #16 +# CHECK: ld1.4h { v4, v5, v6 }, [x3], #24 +# CHECK: ld1.4h { v4, v5, v6, v7 }, [x3], #32 +# CHECK: ld1.8h { v7 }, [x4], #16 +# CHECK: ld1.8h { v7, v8 }, [x4], #32 +# CHECK: ld1.8h { v7, v8, v9 }, [x4], #48 +# CHECK: ld1.8h { v7, v8, v9, v10 }, [x4], #64 +# CHECK: ld1.2s { v12 }, [x0], #8 +# CHECK: ld1.2s { v12, v13 }, [x0], #16 +# CHECK: ld1.2s { v12, v13, v14 }, [x0], #24 +# CHECK: ld1.2s { v12, v13, v14, v15 }, [x0], #32 +# CHECK: ld1.4s { v10 }, [x0], #16 +# CHECK: ld1.4s { v10, v11 }, [x0], #32 +# CHECK: ld1.4s { v10, v11, v12 }, [x0], #48 +# CHECK: ld1.4s { v10, v11, v12, v13 }, [x0], #64 +# CHECK: ld1.1d { v13 }, [x1], #8 +# CHECK: ld1.1d { v13, v14 }, [x1], #16 +# CHECK: ld1.1d { v13, v14, v15 }, [x1], #24 +# CHECK: ld1.1d { v13, v14, v15, v16 }, [x1], #32 +# CHECK: ld1.2d { v15 }, [x2], #16 +# CHECK: ld1.2d { v15, v16 }, [x2], #32 +# CHECK: ld1.2d { v15, v16, v17 }, [x2], #48 +# CHECK: ld1.2d { v15, v16, v17, v18 }, [x2], #64 + +0x21 0x70 0x00 0x0c +0x42 0xa0 0x00 0x4c +0x64 0x64 0x00 0x0c +0x87 0x24 0x00 0x4c +0x0c 0xa8 0x00 0x0c +0x0a 0x68 0x00 0x4c +0x2d 0xac 0x00 0x0c +0x4f 0x7c 0x00 0x4c + +# CHECK: st1.8b { v1 }, [x1] +# CHECK: st1.16b { v2, v3 }, [x2] +# CHECK: st1.4h { v4, v5, v6 }, [x3] +# CHECK: st1.8h { v7, v8, v9, v10 }, [x4] +# CHECK: st1.2s { v12, v13 }, [x0] +# CHECK: st1.4s { v10, v11, v12 }, [x0] +# CHECK: st1.1d { v13, v14 }, [x1] +# CHECK: st1.2d { v15 }, [x2] + +0x61 0x08 0x40 0x0d +0x82 0x84 0x40 0x4d +0xa3 0x58 0x40 0x0d +0xc4 0x80 0x40 0x4d + +# CHECK: ld1.b { v1 }[2], [x3] +# CHECK: ld1.d { v2 }[1], [x4] +# CHECK: ld1.h { v3 }[3], [x5] +# CHECK: ld1.s { v4 }[2], [x6] + +0x61 0x08 0xdf 0x0d +0x82 0x84 0xdf 0x4d +0xa3 0x58 0xdf 0x0d +0xc4 0x80 0xdf 0x4d + +# CHECK: ld1.b { v1 }[2], [x3], #1 +# CHECK: ld1.d { v2 }[1], [x4], #8 +# CHECK: ld1.h { v3 }[3], [x5], #2 +# CHECK: ld1.s { v4 }[2], [x6], #4 + +0x61 0x08 0x00 0x0d +0x82 0x84 0x00 0x4d +0xa3 0x58 0x00 0x0d +0xc4 0x80 0x00 0x4d + +# CHECK: st1.b { v1 }[2], [x3] +# CHECK: st1.d { v2 }[1], [x4] +# CHECK: st1.h { v3 }[3], [x5] +# CHECK: st1.s { v4 }[2], [x6] + +0x61 0x08 0x9f 0x0d +0x82 0x84 0x9f 0x4d +0xa3 0x58 0x9f 0x0d +0xc4 0x80 0x9f 0x4d + +# CHECK: st1.b { v1 }[2], [x3], #1 +# CHECK: st1.d { v2 }[1], [x4], #8 +# CHECK: st1.h { v3 }[3], [x5], #2 +# CHECK: st1.s { v4 }[2], [x6], #4 + +0x61 0x08 0xc4 0x0d +0x82 0x84 0xc5 0x4d +0xa3 0x58 0xc6 0x0d +0xc4 0x80 0xc7 0x4d + +# CHECK: ld1.b { v1 }[2], [x3], x4 +# CHECK: ld1.d { v2 }[1], [x4], x5 +# CHECK: ld1.h { v3 }[3], [x5], x6 +# CHECK: ld1.s { v4 }[2], [x6], x7 + +0x61 0x08 0x84 0x0d +0x82 0x84 0x85 0x4d +0xa3 0x58 0x86 0x0d +0xc4 0x80 0x87 0x4d + +# CHECK: st1.b { v1 }[2], [x3], x4 +# CHECK: st1.d { v2 }[1], [x4], x5 +# CHECK: st1.h { v3 }[3], [x5], x6 +# CHECK: st1.s { v4 }[2], [x6], x7 + +0x41 0x70 0xc3 0x0c +0x42 0xa0 0xc4 0x4c +0x64 0x64 0xc5 0x0c +0x87 0x24 0xc6 0x4c +0x0c 0xa8 0xc7 0x0c +0x0a 0x68 0xc8 0x4c +0x2d 0xac 0xc9 0x0c +0x4f 0x7c 0xca 0x4c + +# CHECK: ld1.8b { v1 }, [x2], x3 +# CHECK: ld1.16b { v2, v3 }, [x2], x4 +# CHECK: ld1.4h { v4, v5, v6 }, [x3], x5 +# CHECK: ld1.8h { v7, v8, v9, v10 }, [x4], x6 +# CHECK: ld1.2s { v12, v13 }, [x0], x7 +# CHECK: ld1.4s { v10, v11, v12 }, [x0], x8 +# CHECK: ld1.1d { v13, v14 }, [x1], x9 +# CHECK: ld1.2d { v15 }, [x2], x10 + +0x41 0x70 0x83 0x0c +0x42 0xa0 0x84 0x4c +0x64 0x64 0x85 0x0c +0x87 0x24 0x86 0x4c +0x0c 0xa8 0x87 0x0c +0x0a 0x68 0x88 0x4c +0x2d 0xac 0x89 0x0c +0x4f 0x7c 0x8a 0x4c + +# CHECK: st1.8b { v1 }, [x2], x3 +# CHECK: st1.16b { v2, v3 }, [x2], x4 +# CHECK: st1.4h { v4, v5, v6 }, [x3], x5 +# CHECK: st1.8h { v7, v8, v9, v10 }, [x4], x6 +# CHECK: st1.2s { v12, v13 }, [x0], x7 +# CHECK: st1.4s { v10, v11, v12 }, [x0], x8 +# CHECK: st1.1d { v13, v14 }, [x1], x9 +# CHECK: st1.2d { v15 }, [x2], x10 + +0x41 0x70 0x9f 0x0c +0x41 0xa0 0x9f 0x0c +0x41 0x60 0x9f 0x0c +0x41 0x20 0x9f 0x0c +0x42 0x70 0x9f 0x4c +0x42 0xa0 0x9f 0x4c +0x42 0x60 0x9f 0x4c +0x42 0x20 0x9f 0x4c +0x64 0x74 0x9f 0x0c +0x64 0xa4 0x9f 0x0c +0x64 0x64 0x9f 0x0c +0x64 0x24 0x9f 0x0c +0x87 0x74 0x9f 0x4c +0x87 0xa4 0x9f 0x4c +0x87 0x64 0x9f 0x4c +0x87 0x24 0x9f 0x4c +0x0c 0x78 0x9f 0x0c +0x0c 0xa8 0x9f 0x0c +0x0c 0x68 0x9f 0x0c +0x0c 0x28 0x9f 0x0c +0x0a 0x78 0x9f 0x4c +0x0a 0xa8 0x9f 0x4c +0x0a 0x68 0x9f 0x4c +0x0a 0x28 0x9f 0x4c +0x2d 0x7c 0x9f 0x0c +0x2d 0xac 0x9f 0x0c +0x2d 0x6c 0x9f 0x0c +0x2d 0x2c 0x9f 0x0c +0x4f 0x7c 0x9f 0x4c +0x4f 0xac 0x9f 0x4c +0x4f 0x6c 0x9f 0x4c +0x4f 0x2c 0x9f 0x4c + +# CHECK: st1.8b { v1 }, [x2], #8 +# CHECK: st1.8b { v1, v2 }, [x2], #16 +# CHECK: st1.8b { v1, v2, v3 }, [x2], #24 +# CHECK: st1.8b { v1, v2, v3, v4 }, [x2], #32 +# CHECK: st1.16b { v2 }, [x2], #16 +# CHECK: st1.16b { v2, v3 }, [x2], #32 +# CHECK: st1.16b { v2, v3, v4 }, [x2], #48 +# CHECK: st1.16b { v2, v3, v4, v5 }, [x2], #64 +# CHECK: st1.4h { v4 }, [x3], #8 +# CHECK: st1.4h { v4, v5 }, [x3], #16 +# CHECK: st1.4h { v4, v5, v6 }, [x3], #24 +# CHECK: st1.4h { v4, v5, v6, v7 }, [x3], #32 +# CHECK: st1.8h { v7 }, [x4], #16 +# CHECK: st1.8h { v7, v8 }, [x4], #32 +# CHECK: st1.8h { v7, v8, v9 }, [x4], #48 +# CHECK: st1.8h { v7, v8, v9, v10 }, [x4], #64 +# CHECK: st1.2s { v12 }, [x0], #8 +# CHECK: st1.2s { v12, v13 }, [x0], #16 +# CHECK: st1.2s { v12, v13, v14 }, [x0], #24 +# CHECK: st1.2s { v12, v13, v14, v15 }, [x0], #32 +# CHECK: st1.4s { v10 }, [x0], #16 +# CHECK: st1.4s { v10, v11 }, [x0], #32 +# CHECK: st1.4s { v10, v11, v12 }, [x0], #48 +# CHECK: st1.4s { v10, v11, v12, v13 }, [x0], #64 +# CHECK: st1.1d { v13 }, [x1], #8 +# CHECK: st1.1d { v13, v14 }, [x1], #16 +# CHECK: st1.1d { v13, v14, v15 }, [x1], #24 +# CHECK: st1.1d { v13, v14, v15, v16 }, [x1], #32 +# CHECK: st1.2d { v15 }, [x2], #16 +# CHECK: st1.2d { v15, v16 }, [x2], #32 +# CHECK: st1.2d { v15, v16, v17 }, [x2], #48 +# CHECK: st1.2d { v15, v16, v17, v18 }, [x2], #64 + +0x21 0xc0 0x40 0x0d +0x21 0xc0 0xc2 0x0d +0x64 0xc4 0x40 0x0d +0x64 0xc4 0xc5 0x0d +0xa9 0xc8 0x40 0x0d +0xa9 0xc8 0xc6 0x0d +0xec 0xcc 0x40 0x0d +0xec 0xcc 0xc8 0x0d + +# CHECK: ld1r.8b { v1 }, [x1] +# CHECK: ld1r.8b { v1 }, [x1], x2 +# CHECK: ld1r.4h { v4 }, [x3] +# CHECK: ld1r.4h { v4 }, [x3], x5 +# CHECK: ld1r.2s { v9 }, [x5] +# CHECK: ld1r.2s { v9 }, [x5], x6 +# CHECK: ld1r.1d { v12 }, [x7] +# CHECK: ld1r.1d { v12 }, [x7], x8 + +0x21 0xc0 0xdf 0x0d +0x21 0xc4 0xdf 0x0d +0x21 0xc8 0xdf 0x0d +0x21 0xcc 0xdf 0x0d + +# CHECK: ld1r.8b { v1 }, [x1], #1 +# CHECK: ld1r.4h { v1 }, [x1], #2 +# CHECK: ld1r.2s { v1 }, [x1], #4 +# CHECK: ld1r.1d { v1 }, [x1], #8 + +0x45 0x80 0x40 0x4c +0x0a 0x88 0x40 0x0c + +# CHECK: ld2.16b { v5, v6 }, [x2] +# CHECK: ld2.2s { v10, v11 }, [x0] + +0x45 0x80 0x00 0x4c +0x0a 0x88 0x00 0x0c + +# CHECK: st2.16b { v5, v6 }, [x2] +# CHECK: st2.2s { v10, v11 }, [x0] + +0x61 0x08 0x20 0x0d +0x82 0x84 0x20 0x4d +0xc3 0x50 0x20 0x0d +0xe4 0x90 0x20 0x4d + +# CHECK: st2.b { v1, v2 }[2], [x3] +# CHECK: st2.d { v2, v3 }[1], [x4] +# CHECK: st2.h { v3, v4 }[2], [x6] +# CHECK: st2.s { v4, v5 }[3], [x7] + +0x61 0x08 0xbf 0x0d +0x82 0x84 0xbf 0x4d +0xa3 0x58 0xbf 0x0d +0xc4 0x80 0xbf 0x4d + +# CHECK: st2.b { v1, v2 }[2], [x3], #2 +# CHECK: st2.d { v2, v3 }[1], [x4], #16 +# CHECK: st2.h { v3, v4 }[3], [x5], #4 +# CHECK: st2.s { v4, v5 }[2], [x6], #8 + +0x61 0x08 0x60 0x0d +0x82 0x84 0x60 0x4d +0xc3 0x50 0x60 0x0d +0xe4 0x90 0x60 0x4d + +# CHECK: ld2.b { v1, v2 }[2], [x3] +# CHECK: ld2.d { v2, v3 }[1], [x4] +# CHECK: ld2.h { v3, v4 }[2], [x6] +# CHECK: ld2.s { v4, v5 }[3], [x7] + +0x61 0x08 0xff 0x0d +0x82 0x84 0xff 0x4d +0xa3 0x58 0xff 0x0d +0xc4 0x80 0xff 0x4d + +# CHECK: ld2.b { v1, v2 }[2], [x3], #2 +# CHECK: ld2.d { v2, v3 }[1], [x4], #16 +# CHECK: ld2.h { v3, v4 }[3], [x5], #4 +# CHECK: ld2.s { v4, v5 }[2], [x6], #8 + +0x61 0x08 0xe4 0x0d +0x82 0x84 0xe6 0x4d +0xa3 0x58 0xe8 0x0d +0xc4 0x80 0xea 0x4d + +# CHECK: ld2.b { v1, v2 }[2], [x3], x4 +# CHECK: ld2.d { v2, v3 }[1], [x4], x6 +# CHECK: ld2.h { v3, v4 }[3], [x5], x8 +# CHECK: ld2.s { v4, v5 }[2], [x6], x10 + +0x61 0x08 0xa4 0x0d +0x82 0x84 0xa6 0x4d +0xa3 0x58 0xa8 0x0d +0xc4 0x80 0xaa 0x4d + +# CHECK: st2.b { v1, v2 }[2], [x3], x4 +# CHECK: st2.d { v2, v3 }[1], [x4], x6 +# CHECK: st2.h { v3, v4 }[3], [x5], x8 +# CHECK: st2.s { v4, v5 }[2], [x6], x10 + +0x64 0x84 0xc5 0x0c +0x0c 0x88 0xc7 0x0c + +# CHECK: ld2.4h { v4, v5 }, [x3], x5 +# CHECK: ld2.2s { v12, v13 }, [x0], x7 + +0x00 0x80 0xdf 0x0c +0x00 0x80 0xdf 0x4c +0x00 0x84 0xdf 0x0c +0x00 0x84 0xdf 0x4c +0x00 0x88 0xdf 0x0c +0x00 0x88 0xdf 0x4c +0x00 0x8c 0xdf 0x4c + +# CHECK: ld2.8b { v0, v1 }, [x0], #16 +# CHECK: ld2.16b { v0, v1 }, [x0], #32 +# CHECK: ld2.4h { v0, v1 }, [x0], #16 +# CHECK: ld2.8h { v0, v1 }, [x0], #32 +# CHECK: ld2.2s { v0, v1 }, [x0], #16 +# CHECK: ld2.4s { v0, v1 }, [x0], #32 +# CHECK: ld2.2d { v0, v1 }, [x0], #32 + +0x64 0x84 0x85 0x0c +0x0c 0x88 0x87 0x0c + +# CHECK: st2.4h { v4, v5 }, [x3], x5 +# CHECK: st2.2s { v12, v13 }, [x0], x7 + +0x00 0x80 0x9f 0x0c +0x00 0x80 0x9f 0x4c +0x00 0x84 0x9f 0x0c +0x00 0x84 0x9f 0x4c +0x00 0x88 0x9f 0x0c +0x00 0x88 0x9f 0x4c +0x00 0x8c 0x9f 0x4c + +# CHECK: st2.8b { v0, v1 }, [x0], #16 +# CHECK: st2.16b { v0, v1 }, [x0], #32 +# CHECK: st2.4h { v0, v1 }, [x0], #16 +# CHECK: st2.8h { v0, v1 }, [x0], #32 +# CHECK: st2.2s { v0, v1 }, [x0], #16 +# CHECK: st2.4s { v0, v1 }, [x0], #32 +# CHECK: st2.2d { v0, v1 }, [x0], #32 + +0x21 0xc0 0x60 0x0d +0x21 0xc0 0xe2 0x0d +0x21 0xc0 0x60 0x4d +0x21 0xc0 0xe2 0x4d +0x21 0xc4 0x60 0x0d +0x21 0xc4 0xe2 0x0d +0x21 0xc4 0x60 0x4d +0x21 0xc4 0xe2 0x4d +0x21 0xc8 0x60 0x0d +0x21 0xc8 0xe2 0x0d +0x21 0xcc 0x60 0x4d +0x21 0xcc 0xe2 0x4d +0x21 0xcc 0x60 0x0d +0x21 0xcc 0xe2 0x0d + +# CHECK: ld2r.8b { v1, v2 }, [x1] +# CHECK: ld2r.8b { v1, v2 }, [x1], x2 +# CHECK: ld2r.16b { v1, v2 }, [x1] +# CHECK: ld2r.16b { v1, v2 }, [x1], x2 +# CHECK: ld2r.4h { v1, v2 }, [x1] +# CHECK: ld2r.4h { v1, v2 }, [x1], x2 +# CHECK: ld2r.8h { v1, v2 }, [x1] +# CHECK: ld2r.8h { v1, v2 }, [x1], x2 +# CHECK: ld2r.2s { v1, v2 }, [x1] +# CHECK: ld2r.2s { v1, v2 }, [x1], x2 +# CHECK: ld2r.2d { v1, v2 }, [x1] +# CHECK: ld2r.2d { v1, v2 }, [x1], x2 +# CHECK: ld2r.1d { v1, v2 }, [x1] +# CHECK: ld2r.1d { v1, v2 }, [x1], x2 + +0x21 0xc0 0xff 0x0d +0x21 0xc0 0xff 0x4d +0x21 0xc4 0xff 0x0d +0x21 0xc4 0xff 0x4d +0x21 0xc8 0xff 0x0d +0x21 0xcc 0xff 0x4d +0x21 0xcc 0xff 0x0d + +# CHECK: ld2r.8b { v1, v2 }, [x1], #2 +# CHECK: ld2r.16b { v1, v2 }, [x1], #2 +# CHECK: ld2r.4h { v1, v2 }, [x1], #4 +# CHECK: ld2r.8h { v1, v2 }, [x1], #4 +# CHECK: ld2r.2s { v1, v2 }, [x1], #8 +# CHECK: ld2r.2d { v1, v2 }, [x1], #16 +# CHECK: ld2r.1d { v1, v2 }, [x1], #16 + +0x21 0x40 0x40 0x0c +0x45 0x40 0x40 0x4c +0x0a 0x48 0x40 0x0c + +# CHECK: ld3.8b { v1, v2, v3 }, [x1] +# CHECK: ld3.16b { v5, v6, v7 }, [x2] +# CHECK: ld3.2s { v10, v11, v12 }, [x0] + +0x21 0x40 0x00 0x0c +0x45 0x40 0x00 0x4c +0x0a 0x48 0x00 0x0c + +# CHECK: st3.8b { v1, v2, v3 }, [x1] +# CHECK: st3.16b { v5, v6, v7 }, [x2] +# CHECK: st3.2s { v10, v11, v12 }, [x0] + +0x61 0x28 0xc4 0x0d +0x82 0xa4 0xc5 0x4d +0xa3 0x78 0xc6 0x0d +0xc4 0xa0 0xc7 0x4d + +# CHECK: ld3.b { v1, v2, v3 }[2], [x3], x4 +# CHECK: ld3.d { v2, v3, v4 }[1], [x4], x5 +# CHECK: ld3.h { v3, v4, v5 }[3], [x5], x6 +# CHECK: ld3.s { v4, v5, v6 }[2], [x6], x7 + +0x61 0x28 0x84 0x0d +0x82 0xa4 0x85 0x4d +0xa3 0x78 0x86 0x0d +0xc4 0xa0 0x87 0x4d + +# CHECK: st3.b { v1, v2, v3 }[2], [x3], x4 +# CHECK: st3.d { v2, v3, v4 }[1], [x4], x5 +# CHECK: st3.h { v3, v4, v5 }[3], [x5], x6 +# CHECK: st3.s { v4, v5, v6 }[2], [x6], x7 + +0x61 0x28 0x9f 0x0d +0x82 0xa4 0x9f 0x4d +0xa3 0x78 0x9f 0x0d +0xc4 0xa0 0x9f 0x4d + +# CHECK: st3.b { v1, v2, v3 }[2], [x3], #3 +# CHECK: st3.d { v2, v3, v4 }[1], [x4], #24 +# CHECK: st3.h { v3, v4, v5 }[3], [x5], #6 +# CHECK: st3.s { v4, v5, v6 }[2], [x6], #12 + +0x41 0x40 0xc3 0x0c +0x42 0x40 0xc4 0x4c +0x64 0x44 0xc5 0x0c +0x87 0x44 0xc6 0x4c +0x0c 0x48 0xc7 0x0c +0x0a 0x48 0xc8 0x4c +0x4f 0x4c 0xca 0x4c + +# CHECK: ld3.8b { v1, v2, v3 }, [x2], x3 +# CHECK: ld3.16b { v2, v3, v4 }, [x2], x4 +# CHECK: ld3.4h { v4, v5, v6 }, [x3], x5 +# CHECK: ld3.8h { v7, v8, v9 }, [x4], x6 +# CHECK: ld3.2s { v12, v13, v14 }, [x0], x7 +# CHECK: ld3.4s { v10, v11, v12 }, [x0], x8 +# CHECK: ld3.2d { v15, v16, v17 }, [x2], x10 + +0x00 0x40 0xdf 0x0c +0x00 0x40 0xdf 0x4c +0x00 0x44 0xdf 0x0c +0x00 0x44 0xdf 0x4c +0x00 0x48 0xdf 0x0c +0x00 0x48 0xdf 0x4c +0x00 0x4c 0xdf 0x4c + +# CHECK: ld3.8b { v0, v1, v2 }, [x0], #24 +# CHECK: ld3.16b { v0, v1, v2 }, [x0], #48 +# CHECK: ld3.4h { v0, v1, v2 }, [x0], #24 +# CHECK: ld3.8h { v0, v1, v2 }, [x0], #48 +# CHECK: ld3.2s { v0, v1, v2 }, [x0], #24 +# CHECK: ld3.4s { v0, v1, v2 }, [x0], #48 +# CHECK: ld3.2d { v0, v1, v2 }, [x0], #48 + +0x41 0x40 0x83 0x0c +0x42 0x40 0x84 0x4c +0x64 0x44 0x85 0x0c +0x87 0x44 0x86 0x4c +0x0c 0x48 0x87 0x0c +0x0a 0x48 0x88 0x4c +0x4f 0x4c 0x8a 0x4c + +# CHECK: st3.8b { v1, v2, v3 }, [x2], x3 +# CHECK: st3.16b { v2, v3, v4 }, [x2], x4 +# CHECK: st3.4h { v4, v5, v6 }, [x3], x5 +# CHECK: st3.8h { v7, v8, v9 }, [x4], x6 +# CHECK: st3.2s { v12, v13, v14 }, [x0], x7 +# CHECK: st3.4s { v10, v11, v12 }, [x0], x8 +# CHECK: st3.2d { v15, v16, v17 }, [x2], x10 + +0x00 0x40 0x9f 0x0c +0x00 0x40 0x9f 0x4c +0x00 0x44 0x9f 0x0c +0x00 0x44 0x9f 0x4c +0x00 0x48 0x9f 0x0c +0x00 0x48 0x9f 0x4c +0x00 0x4c 0x9f 0x4c + +# CHECK: st3.8b { v0, v1, v2 }, [x0], #24 +# CHECK: st3.16b { v0, v1, v2 }, [x0], #48 +# CHECK: st3.4h { v0, v1, v2 }, [x0], #24 +# CHECK: st3.8h { v0, v1, v2 }, [x0], #48 +# CHECK: st3.2s { v0, v1, v2 }, [x0], #24 +# CHECK: st3.4s { v0, v1, v2 }, [x0], #48 +# CHECK: st3.2d { v0, v1, v2 }, [x0], #48 + +0x61 0x28 0x40 0x0d +0x82 0xa4 0x40 0x4d +0xc3 0x70 0x40 0x0d +0xe4 0xb0 0x40 0x4d + +# CHECK: ld3.b { v1, v2, v3 }[2], [x3] +# CHECK: ld3.d { v2, v3, v4 }[1], [x4] +# CHECK: ld3.h { v3, v4, v5 }[2], [x6] +# CHECK: ld3.s { v4, v5, v6 }[3], [x7] + +0x61 0x28 0xdf 0x0d +0x82 0xa4 0xdf 0x4d +0xa3 0x78 0xdf 0x0d +0xc4 0xa0 0xdf 0x4d + +# CHECK: ld3.b { v1, v2, v3 }[2], [x3], #3 +# CHECK: ld3.d { v2, v3, v4 }[1], [x4], #24 +# CHECK: ld3.h { v3, v4, v5 }[3], [x5], #6 +# CHECK: ld3.s { v4, v5, v6 }[2], [x6], #12 + +0x61 0x28 0x00 0x0d +0x82 0xa4 0x00 0x4d +0xc3 0x70 0x00 0x0d +0xe4 0xb0 0x00 0x4d + +# CHECK: st3.b { v1, v2, v3 }[2], [x3] +# CHECK: st3.d { v2, v3, v4 }[1], [x4] +# CHECK: st3.h { v3, v4, v5 }[2], [x6] +# CHECK: st3.s { v4, v5, v6 }[3], [x7] + +0x21 0xe0 0x40 0x0d +0x21 0xe0 0xc2 0x0d +0x21 0xe0 0x40 0x4d +0x21 0xe0 0xc2 0x4d +0x21 0xe4 0x40 0x0d +0x21 0xe4 0xc2 0x0d +0x21 0xe4 0x40 0x4d +0x21 0xe4 0xc2 0x4d +0x21 0xe8 0x40 0x0d +0x21 0xe8 0xc2 0x0d +0x21 0xec 0x40 0x4d +0x21 0xec 0xc2 0x4d +0x21 0xec 0x40 0x0d +0x21 0xec 0xc2 0x0d + +# CHECK: ld3r.8b { v1, v2, v3 }, [x1] +# CHECK: ld3r.8b { v1, v2, v3 }, [x1], x2 +# CHECK: ld3r.16b { v1, v2, v3 }, [x1] +# CHECK: ld3r.16b { v1, v2, v3 }, [x1], x2 +# CHECK: ld3r.4h { v1, v2, v3 }, [x1] +# CHECK: ld3r.4h { v1, v2, v3 }, [x1], x2 +# CHECK: ld3r.8h { v1, v2, v3 }, [x1] +# CHECK: ld3r.8h { v1, v2, v3 }, [x1], x2 +# CHECK: ld3r.2s { v1, v2, v3 }, [x1] +# CHECK: ld3r.2s { v1, v2, v3 }, [x1], x2 +# CHECK: ld3r.2d { v1, v2, v3 }, [x1] +# CHECK: ld3r.2d { v1, v2, v3 }, [x1], x2 +# CHECK: ld3r.1d { v1, v2, v3 }, [x1] +# CHECK: ld3r.1d { v1, v2, v3 }, [x1], x2 + +0x21 0xe0 0xdf 0x0d +0x21 0xe0 0xdf 0x4d +0x21 0xe4 0xdf 0x0d +0x21 0xe4 0xdf 0x4d +0x21 0xe8 0xdf 0x0d +0x21 0xec 0xdf 0x4d +0x21 0xec 0xdf 0x0d + +# CHECK: ld3r.8b { v1, v2, v3 }, [x1], #3 +# CHECK: ld3r.16b { v1, v2, v3 }, [x1], #3 +# CHECK: ld3r.4h { v1, v2, v3 }, [x1], #6 +# CHECK: ld3r.8h { v1, v2, v3 }, [x1], #6 +# CHECK: ld3r.2s { v1, v2, v3 }, [x1], #12 +# CHECK: ld3r.2d { v1, v2, v3 }, [x1], #24 +# CHECK: ld3r.1d { v1, v2, v3 }, [x1], #24 + +0x21 0x00 0x40 0x0c +0x45 0x00 0x40 0x4c +0x0a 0x08 0x40 0x0c + +# CHECK: ld4.8b { v1, v2, v3, v4 }, [x1] +# CHECK: ld4.16b { v5, v6, v7, v8 }, [x2] +# CHECK: ld4.2s { v10, v11, v12, v13 }, [x0] + +0x21 0x00 0x00 0x0c +0x45 0x00 0x00 0x4c +0x0a 0x08 0x00 0x0c + +# CHECK: st4.8b { v1, v2, v3, v4 }, [x1] +# CHECK: st4.16b { v5, v6, v7, v8 }, [x2] +# CHECK: st4.2s { v10, v11, v12, v13 }, [x0] + +0x61 0x28 0xe4 0x0d +0x82 0xa4 0xe5 0x4d +0xa3 0x78 0xe6 0x0d +0xc4 0xa0 0xe7 0x4d + +# CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3], x4 +# CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4], x5 +# CHECK: ld4.h { v3, v4, v5, v6 }[3], [x5], x6 +# CHECK: ld4.s { v4, v5, v6, v7 }[2], [x6], x7 + +0x61 0x28 0xff 0x0d +0x82 0xa4 0xff 0x4d +0xa3 0x78 0xff 0x0d +0xc4 0xa0 0xff 0x4d + +# CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3], #4 +# CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4], #32 +# CHECK: ld4.h { v3, v4, v5, v6 }[3], [x5], #8 +# CHECK: ld4.s { v4, v5, v6, v7 }[2], [x6], #16 + +0x61 0x28 0xa4 0x0d +0x82 0xa4 0xa5 0x4d +0xa3 0x78 0xa6 0x0d +0xc4 0xa0 0xa7 0x4d + +# CHECK: st4.b { v1, v2, v3, v4 }[2], [x3], x4 +# CHECK: st4.d { v2, v3, v4, v5 }[1], [x4], x5 +# CHECK: st4.h { v3, v4, v5, v6 }[3], [x5], x6 +# CHECK: st4.s { v4, v5, v6, v7 }[2], [x6], x7 + +0x61 0x28 0xbf 0x0d +0x82 0xa4 0xbf 0x4d +0xa3 0x78 0xbf 0x0d +0xc4 0xa0 0xbf 0x4d + +# CHECK: st4.b { v1, v2, v3, v4 }[2], [x3], #4 +# CHECK: st4.d { v2, v3, v4, v5 }[1], [x4], #32 +# CHECK: st4.h { v3, v4, v5, v6 }[3], [x5], #8 +# CHECK: st4.s { v4, v5, v6, v7 }[2], [x6], #16 + +0x41 0x00 0xc3 0x0c +0x42 0x00 0xc4 0x4c +0x64 0x04 0xc5 0x0c +0x87 0x04 0xc6 0x4c +0x0c 0x08 0xc7 0x0c +0x0a 0x08 0xc8 0x4c +0x4f 0x0c 0xca 0x4c + +# CHECK: ld4.8b { v1, v2, v3, v4 }, [x2], x3 +# CHECK: ld4.16b { v2, v3, v4, v5 }, [x2], x4 +# CHECK: ld4.4h { v4, v5, v6, v7 }, [x3], x5 +# CHECK: ld4.8h { v7, v8, v9, v10 }, [x4], x6 +# CHECK: ld4.2s { v12, v13, v14, v15 }, [x0], x7 +# CHECK: ld4.4s { v10, v11, v12, v13 }, [x0], x8 +# CHECK: ld4.2d { v15, v16, v17, v18 }, [x2], x10 + +0x00 0x00 0xdf 0x0c +0x00 0x00 0xdf 0x4c +0x00 0x04 0xdf 0x0c +0x00 0x04 0xdf 0x4c +0x00 0x08 0xdf 0x0c +0x00 0x08 0xdf 0x4c +0x00 0x0c 0xdf 0x4c + +# CHECK: ld4.8b { v0, v1, v2, v3 }, [x0], #32 +# CHECK: ld4.16b { v0, v1, v2, v3 }, [x0], #64 +# CHECK: ld4.4h { v0, v1, v2, v3 }, [x0], #32 +# CHECK: ld4.8h { v0, v1, v2, v3 }, [x0], #64 +# CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], #32 +# CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], #64 +# CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], #64 + +0x00 0x00 0x9f 0x0c +0x00 0x00 0x9f 0x4c +0x00 0x04 0x9f 0x0c +0x00 0x04 0x9f 0x4c +0x00 0x08 0x9f 0x0c +0x00 0x08 0x9f 0x4c +0x00 0x0c 0x9f 0x4c + +# CHECK: st4.8b { v0, v1, v2, v3 }, [x0], #32 +# CHECK: st4.16b { v0, v1, v2, v3 }, [x0], #64 +# CHECK: st4.4h { v0, v1, v2, v3 }, [x0], #32 +# CHECK: st4.8h { v0, v1, v2, v3 }, [x0], #64 +# CHECK: st4.2s { v0, v1, v2, v3 }, [x0], #32 +# CHECK: st4.4s { v0, v1, v2, v3 }, [x0], #64 +# CHECK: st4.2d { v0, v1, v2, v3 }, [x0], #64 + +0x41 0x00 0x83 0x0c +0x42 0x00 0x84 0x4c +0x64 0x04 0x85 0x0c +0x87 0x04 0x86 0x4c +0x0c 0x08 0x87 0x0c +0x0a 0x08 0x88 0x4c +0x4f 0x0c 0x8a 0x4c + +# CHECK: st4.8b { v1, v2, v3, v4 }, [x2], x3 +# CHECK: st4.16b { v2, v3, v4, v5 }, [x2], x4 +# CHECK: st4.4h { v4, v5, v6, v7 }, [x3], x5 +# CHECK: st4.8h { v7, v8, v9, v10 }, [x4], x6 +# CHECK: st4.2s { v12, v13, v14, v15 }, [x0], x7 +# CHECK: st4.4s { v10, v11, v12, v13 }, [x0], x8 +# CHECK: st4.2d { v15, v16, v17, v18 }, [x2], x10 + +0x61 0x28 0x60 0x0d +0x82 0xa4 0x60 0x4d +0xc3 0x70 0x60 0x0d +0xe4 0xb0 0x60 0x4d + +# CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3] +# CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4] +# CHECK: ld4.h { v3, v4, v5, v6 }[2], [x6] +# CHECK: ld4.s { v4, v5, v6, v7 }[3], [x7] + +0x61 0x28 0x20 0x0d +0x82 0xa4 0x20 0x4d +0xc3 0x70 0x20 0x0d +0xe4 0xb0 0x20 0x4d + +# CHECK: st4.b { v1, v2, v3, v4 }[2], [x3] +# CHECK: st4.d { v2, v3, v4, v5 }[1], [x4] +# CHECK: st4.h { v3, v4, v5, v6 }[2], [x6] +# CHECK: st4.s { v4, v5, v6, v7 }[3], [x7] + +0x21 0xe0 0x60 0x0d +0x21 0xe0 0xe2 0x0d +0x21 0xe0 0x60 0x4d +0x21 0xe0 0xe2 0x4d +0x21 0xe4 0x60 0x0d +0x21 0xe4 0xe2 0x0d +0x21 0xe4 0x60 0x4d +0x21 0xe4 0xe2 0x4d +0x21 0xe8 0x60 0x0d +0x21 0xe8 0xe2 0x0d +0x21 0xec 0x60 0x4d +0x21 0xec 0xe2 0x4d +0x21 0xec 0x60 0x0d +0x21 0xec 0xe2 0x0d + +# CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1] +# CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1], x2 +# CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1] +# CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1], x2 +# CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1] +# CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1], x2 +# CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1] +# CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1], x2 +# CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1] +# CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1], x2 +# CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1] +# CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1], x2 +# CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1] +# CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1], x2 + +0x21 0xe0 0xff 0x0d +0x21 0xe0 0xff 0x4d +0x21 0xe4 0xff 0x0d +0x21 0xe4 0xff 0x4d +0x21 0xe8 0xff 0x0d +0x21 0xec 0xff 0x4d +0x21 0xec 0xff 0x0d + +# CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1], #4 +# CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1], #4 +# CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1], #8 +# CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1], #8 +# CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1], #16 +# CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1], #32 +# CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1], #32 + +0x20 0xe4 0x00 0x2f +0x20 0xe4 0x00 0x6f +0x20 0xe4 0x00 0x0f +0x20 0xe4 0x00 0x4f + +# CHECK: movi d0, #0x000000000000ff +# CHECK: movi.2d v0, #0x000000000000ff +# CHECK: movi.8b v0, #0x1 +# CHECK: movi.16b v0, #0x1 + +0x20 0x04 0x00 0x0f +0x20 0x24 0x00 0x0f +0x20 0x44 0x00 0x0f +0x20 0x64 0x00 0x0f + +# CHECK: movi.2s v0, #0x1 +# CHECK: movi.2s v0, #0x1, lsl #8 +# CHECK: movi.2s v0, #0x1, lsl #16 +# CHECK: movi.2s v0, #0x1, lsl #24 + +0x20 0x04 0x00 0x4f +0x20 0x24 0x00 0x4f +0x20 0x44 0x00 0x4f +0x20 0x64 0x00 0x4f + +# CHECK: movi.4s v0, #0x1 +# CHECK: movi.4s v0, #0x1, lsl #8 +# CHECK: movi.4s v0, #0x1, lsl #16 +# CHECK: movi.4s v0, #0x1, lsl #24 + +0x20 0x84 0x00 0x0f +0x20 0xa4 0x00 0x0f + +# CHECK: movi.4h v0, #0x1 +# CHECK: movi.4h v0, #0x1, lsl #8 + +0x20 0x84 0x00 0x4f +0x20 0xa4 0x00 0x4f + +# CHECK: movi.8h v0, #0x1 +# CHECK: movi.8h v0, #0x1, lsl #8 + +0x20 0x04 0x00 0x2f +0x20 0x24 0x00 0x2f +0x20 0x44 0x00 0x2f +0x20 0x64 0x00 0x2f + +# CHECK: mvni.2s v0, #0x1 +# CHECK: mvni.2s v0, #0x1, lsl #8 +# CHECK: mvni.2s v0, #0x1, lsl #16 +# CHECK: mvni.2s v0, #0x1, lsl #24 + +0x20 0x04 0x00 0x6f +0x20 0x24 0x00 0x6f +0x20 0x44 0x00 0x6f +0x20 0x64 0x00 0x6f + +# CHECK: mvni.4s v0, #0x1 +# CHECK: mvni.4s v0, #0x1, lsl #8 +# CHECK: mvni.4s v0, #0x1, lsl #16 +# CHECK: mvni.4s v0, #0x1, lsl #24 + +0x20 0x84 0x00 0x2f +0x20 0xa4 0x00 0x2f + +# CHECK: mvni.4h v0, #0x1 +# CHECK: mvni.4h v0, #0x1, lsl #8 + +0x20 0x84 0x00 0x6f +0x20 0xa4 0x00 0x6f + +# CHECK: mvni.8h v0, #0x1 +# CHECK: mvni.8h v0, #0x1, lsl #8 + +0x20 0xc4 0x00 0x2f +0x20 0xd4 0x00 0x2f +0x20 0xc4 0x00 0x6f +0x20 0xd4 0x00 0x6f + +# CHECK: mvni.2s v0, #0x1, msl #8 +# CHECK: mvni.2s v0, #0x1, msl #16 +# CHECK: mvni.4s v0, #0x1, msl #8 +# CHECK: mvni.4s v0, #0x1, msl #16 + +0x00 0x88 0x21 0x2e +0x00 0x98 0x21 0x2e +0x00 0x98 0xa1 0x2e +0x00 0x98 0x21 0x0e +0x00 0x88 0x21 0x0e +0x00 0x88 0xa1 0x0e +0x00 0x98 0xa1 0x0e + +# CHECK: frinta.2s v0, v0 +# CHECK: frintx.2s v0, v0 +# CHECK: frinti.2s v0, v0 +# CHECK: frintm.2s v0, v0 +# CHECK: frintn.2s v0, v0 +# CHECK: frintp.2s v0, v0 +# CHECK: frintz.2s v0, v0 + +#===-------------------------------------------------------------------------=== +# AdvSIMD scalar x index instructions +#===-------------------------------------------------------------------------=== + +0x00 0x18 0xa0 0x5f +0x00 0x18 0xc0 0x5f +0x00 0x58 0xa0 0x5f +0x00 0x58 0xc0 0x5f +0x00 0x98 0xa0 0x7f +0x00 0x98 0xc0 0x7f +0x00 0x98 0xa0 0x5f +0x00 0x98 0xc0 0x5f +0x00 0x38 0x70 0x5f +0x00 0x38 0xa0 0x5f +0x00 0x78 0x70 0x5f +0x00 0xc8 0x70 0x5f +0x00 0xc8 0xa0 0x5f +0x00 0xb8 0x70 0x5f +0x00 0xb8 0xa0 0x5f +0x00 0xd8 0x70 0x5f +0x00 0xd8 0xa0 0x5f + +# CHECK: fmla.s s0, s0, v0[3] +# CHECK: fmla.d d0, d0, v0[1] +# CHECK: fmls.s s0, s0, v0[3] +# CHECK: fmls.d d0, d0, v0[1] +# CHECK: fmulx.s s0, s0, v0[3] +# CHECK: fmulx.d d0, d0, v0[1] +# CHECK: fmul.s s0, s0, v0[3] +# CHECK: fmul.d d0, d0, v0[1] +# CHECK: sqdmlal.h s0, h0, v0[7] +# CHECK: sqdmlal.s d0, s0, v0[3] +# CHECK: sqdmlsl.h s0, h0, v0[7] +# CHECK: sqdmulh.h h0, h0, v0[7] +# CHECK: sqdmulh.s s0, s0, v0[3] +# CHECK: sqdmull.h s0, h0, v0[7] +# CHECK: sqdmull.s d0, s0, v0[3] +# CHECK: sqrdmulh.h h0, h0, v0[7] +# CHECK: sqrdmulh.s s0, s0, v0[3] + +#===-------------------------------------------------------------------------=== +# AdvSIMD vector x index instructions +#===-------------------------------------------------------------------------=== + + 0x00 0x10 0x80 0x0f + 0x00 0x10 0xa0 0x4f + 0x00 0x18 0xc0 0x4f + 0x00 0x50 0x80 0x0f + 0x00 0x50 0xa0 0x4f + 0x00 0x58 0xc0 0x4f + 0x00 0x90 0x80 0x2f + 0x00 0x90 0xa0 0x6f + 0x00 0x98 0xc0 0x6f + 0x00 0x90 0x80 0x0f + 0x00 0x90 0xa0 0x4f + 0x00 0x98 0xc0 0x4f + 0x00 0x00 0x40 0x2f + 0x00 0x00 0x50 0x6f + 0x00 0x08 0x80 0x2f + 0x00 0x08 0xa0 0x6f + 0x00 0x40 0x40 0x2f + 0x00 0x40 0x50 0x6f + 0x00 0x48 0x80 0x2f + 0x00 0x48 0xa0 0x6f + 0x00 0x80 0x40 0x0f + 0x00 0x80 0x50 0x4f + 0x00 0x88 0x80 0x0f + 0x00 0x88 0xa0 0x4f + 0x00 0x20 0x40 0x0f + 0x00 0x20 0x50 0x4f + 0x00 0x28 0x80 0x0f + 0x00 0x28 0xa0 0x4f + 0x00 0x60 0x40 0x0f + 0x00 0x60 0x50 0x4f + 0x00 0x68 0x80 0x0f + 0x00 0x68 0xa0 0x4f + 0x00 0xa0 0x40 0x0f + 0x00 0xa0 0x50 0x4f + 0x00 0xa8 0x80 0x0f + 0x00 0xa8 0xa0 0x4f + 0x00 0x30 0x40 0x0f + 0x00 0x30 0x50 0x4f + 0x00 0x38 0x80 0x0f + 0x00 0x38 0xa0 0x4f + 0x00 0x70 0x40 0x0f + 0x00 0x70 0x50 0x4f + 0x00 0x78 0x80 0x0f + 0x00 0x78 0xa0 0x4f + 0x00 0xc0 0x40 0x0f + 0x00 0xc0 0x50 0x4f + 0x00 0xc8 0x80 0x0f + 0x00 0xc8 0xa0 0x4f + 0x00 0xb0 0x40 0x0f + 0x00 0xb0 0x50 0x4f + 0x00 0xb8 0x80 0x0f + 0x00 0xb8 0xa0 0x4f + 0x00 0xd0 0x40 0x0f + 0x00 0xd0 0x50 0x4f + 0x00 0xd8 0x80 0x0f + 0x00 0xd8 0xa0 0x4f + 0x00 0x20 0x40 0x2f + 0x00 0x20 0x50 0x6f + 0x00 0x28 0x80 0x2f + 0x00 0x28 0xa0 0x6f + 0x00 0x60 0x40 0x2f + 0x00 0x60 0x50 0x6f + 0x00 0x68 0x80 0x2f + 0x00 0x68 0xa0 0x6f + 0x00 0xa0 0x40 0x2f + 0x00 0xa0 0x50 0x6f + 0x00 0xa8 0x80 0x2f + 0x00 0xa8 0xa0 0x6f + +# CHECK: fmla.2s v0, v0, v0[0] +# CHECK: fmla.4s v0, v0, v0[1] +# CHECK: fmla.2d v0, v0, v0[1] +# CHECK: fmls.2s v0, v0, v0[0] +# CHECK: fmls.4s v0, v0, v0[1] +# CHECK: fmls.2d v0, v0, v0[1] +# CHECK: fmulx.2s v0, v0, v0[0] +# CHECK: fmulx.4s v0, v0, v0[1] +# CHECK: fmulx.2d v0, v0, v0[1] +# CHECK: fmul.2s v0, v0, v0[0] +# CHECK: fmul.4s v0, v0, v0[1] +# CHECK: fmul.2d v0, v0, v0[1] +# CHECK: mla.4h v0, v0, v0[0] +# CHECK: mla.8h v0, v0, v0[1] +# CHECK: mla.2s v0, v0, v0[2] +# CHECK: mla.4s v0, v0, v0[3] +# CHECK: mls.4h v0, v0, v0[0] +# CHECK: mls.8h v0, v0, v0[1] +# CHECK: mls.2s v0, v0, v0[2] +# CHECK: mls.4s v0, v0, v0[3] +# CHECK: mul.4h v0, v0, v0[0] +# CHECK: mul.8h v0, v0, v0[1] +# CHECK: mul.2s v0, v0, v0[2] +# CHECK: mul.4s v0, v0, v0[3] +# CHECK: smlal.4s v0, v0, v0[0] +# CHECK: smlal2.4s v0, v0, v0[1] +# CHECK: smlal.2d v0, v0, v0[2] +# CHECK: smlal2.2d v0, v0, v0[3] +# CHECK: smlsl.4s v0, v0, v0[0] +# CHECK: smlsl2.4s v0, v0, v0[1] +# CHECK: smlsl.2d v0, v0, v0[2] +# CHECK: smlsl2.2d v0, v0, v0[3] +# CHECK: smull.4s v0, v0, v0[0] +# CHECK: smull2.4s v0, v0, v0[1] +# CHECK: smull.2d v0, v0, v0[2] +# CHECK: smull2.2d v0, v0, v0[3] +# CHECK: sqdmlal.4s v0, v0, v0[0] +# CHECK: sqdmlal2.4s v0, v0, v0[1] +# CHECK: sqdmlal.2d v0, v0, v0[2] +# CHECK: sqdmlal2.2d v0, v0, v0[3] +# CHECK: sqdmlsl.4s v0, v0, v0[0] +# CHECK: sqdmlsl2.4s v0, v0, v0[1] +# CHECK: sqdmlsl.2d v0, v0, v0[2] +# CHECK: sqdmlsl2.2d v0, v0, v0[3] +# CHECK: sqdmulh.4h v0, v0, v0[0] +# CHECK: sqdmulh.8h v0, v0, v0[1] +# CHECK: sqdmulh.2s v0, v0, v0[2] +# CHECK: sqdmulh.4s v0, v0, v0[3] +# CHECK: sqdmull.4s v0, v0, v0[0] +# CHECK: sqdmull2.4s v0, v0, v0[1] +# CHECK: sqdmull.2d v0, v0, v0[2] +# CHECK: sqdmull2.2d v0, v0, v0[3] +# CHECK: sqrdmulh.4h v0, v0, v0[0] +# CHECK: sqrdmulh.8h v0, v0, v0[1] +# CHECK: sqrdmulh.2s v0, v0, v0[2] +# CHECK: sqrdmulh.4s v0, v0, v0[3] +# CHECK: umlal.4s v0, v0, v0[0] +# CHECK: umlal2.4s v0, v0, v0[1] +# CHECK: umlal.2d v0, v0, v0[2] +# CHECK: umlal2.2d v0, v0, v0[3] +# CHECK: umlsl.4s v0, v0, v0[0] +# CHECK: umlsl2.4s v0, v0, v0[1] +# CHECK: umlsl.2d v0, v0, v0[2] +# CHECK: umlsl2.2d v0, v0, v0[3] +# CHECK: umull.4s v0, v0, v0[0] +# CHECK: umull2.4s v0, v0, v0[1] +# CHECK: umull.2d v0, v0, v0[2] +# CHECK: umull2.2d v0, v0, v0[3] + + +#===-------------------------------------------------------------------------=== +# AdvSIMD scalar + shift instructions +#===-------------------------------------------------------------------------=== + + 0x00 0x54 0x41 0x5f + 0x00 0x54 0x41 0x7f + 0x00 0x9c 0x09 0x5f + 0x00 0x9c 0x12 0x5f + 0x00 0x9c 0x23 0x5f + 0x00 0x8c 0x09 0x7f + 0x00 0x8c 0x12 0x7f + 0x00 0x8c 0x23 0x7f + 0x00 0x64 0x09 0x7f + 0x00 0x64 0x12 0x7f + 0x00 0x64 0x23 0x7f + 0x00 0x64 0x44 0x7f + 0x00 0x74 0x09 0x5f + 0x00 0x74 0x12 0x5f + 0x00 0x74 0x23 0x5f + 0x00 0x74 0x44 0x5f + 0x00 0x94 0x09 0x5f + 0x00 0x94 0x12 0x5f + 0x00 0x94 0x23 0x5f + 0x00 0x84 0x09 0x7f + 0x00 0x84 0x12 0x7f + 0x00 0x84 0x23 0x7f + 0x00 0x44 0x41 0x7f + 0x00 0x24 0x41 0x5f + 0x00 0x34 0x41 0x5f + 0x00 0x04 0x41 0x5f + 0x00 0xe4 0x21 0x7f + 0x00 0xe4 0x42 0x7f + 0x00 0x9c 0x09 0x7f + 0x00 0x9c 0x12 0x7f + 0x00 0x9c 0x23 0x7f + 0x00 0x74 0x09 0x7f + 0x00 0x74 0x12 0x7f + 0x00 0x74 0x23 0x7f + 0x00 0x74 0x44 0x7f + 0x00 0x94 0x09 0x7f + 0x00 0x94 0x12 0x7f + 0x00 0x94 0x23 0x7f + 0x00 0x24 0x41 0x7f + 0x00 0x34 0x41 0x7f + 0x00 0x04 0x41 0x7f + 0x00 0x14 0x41 0x7f + +# CHECK: shl d0, d0, #1 +# CHECK: sli d0, d0, #1 +# CHECK: sqrshrn b0, h0, #7 +# CHECK: sqrshrn h0, s0, #14 +# CHECK: sqrshrn s0, d0, #29 +# CHECK: sqrshrun b0, h0, #7 +# CHECK: sqrshrun h0, s0, #14 +# CHECK: sqrshrun s0, d0, #29 +# CHECK: sqshlu b0, b0, #1 +# CHECK: sqshlu h0, h0, #2 +# CHECK: sqshlu s0, s0, #3 +# CHECK: sqshlu d0, d0, #4 +# CHECK: sqshl b0, b0, #1 +# CHECK: sqshl h0, h0, #2 +# CHECK: sqshl s0, s0, #3 +# CHECK: sqshl d0, d0, #4 +# CHECK: sqshrn b0, h0, #7 +# CHECK: sqshrn h0, s0, #14 +# CHECK: sqshrn s0, d0, #29 +# CHECK: sqshrun b0, h0, #7 +# CHECK: sqshrun h0, s0, #14 +# CHECK: sqshrun s0, d0, #29 +# CHECK: sri d0, d0, #63 +# CHECK: srshr d0, d0, #63 +# CHECK: srsra d0, d0, #63 +# CHECK: sshr d0, d0, #63 +# CHECK: ucvtf s0, s0, #31 +# CHECK: ucvtf d0, d0, #62 +# CHECK: uqrshrn b0, h0, #7 +# CHECK: uqrshrn h0, s0, #14 +# CHECK: uqrshrn s0, d0, #29 +# CHECK: uqshl b0, b0, #1 +# CHECK: uqshl h0, h0, #2 +# CHECK: uqshl s0, s0, #3 +# CHECK: uqshl d0, d0, #4 +# CHECK: uqshrn b0, h0, #7 +# CHECK: uqshrn h0, s0, #14 +# CHECK: uqshrn s0, d0, #29 +# CHECK: urshr d0, d0, #63 +# CHECK: ursra d0, d0, #63 +# CHECK: ushr d0, d0, #63 +# CHECK: usra d0, d0, #63 + +#===-------------------------------------------------------------------------=== +# AdvSIMD vector + shift instructions +#===-------------------------------------------------------------------------=== + + 0x00 0xfc 0x21 0x0f + 0x00 0xfc 0x22 0x4f + 0x00 0xfc 0x43 0x4f + 0x00 0xfc 0x21 0x2f + 0x00 0xfc 0x22 0x6f + 0x00 0xfc 0x43 0x6f + 0x00 0x8c 0x09 0x0f + 0x00 0x8c 0x0a 0x4f + 0x00 0x8c 0x13 0x0f + 0x00 0x8c 0x14 0x4f + 0x00 0x8c 0x25 0x0f + 0x00 0x8c 0x26 0x4f + 0x00 0xe4 0x21 0x0f + 0x00 0xe4 0x22 0x4f + 0x00 0xe4 0x43 0x4f + 0x00 0x54 0x09 0x0f + 0x00 0x54 0x0a 0x4f + 0x00 0x54 0x13 0x0f + 0x00 0x54 0x14 0x4f + 0x00 0x54 0x25 0x0f + 0x00 0x54 0x26 0x4f + 0x00 0x54 0x47 0x4f + 0x00 0x84 0x09 0x0f + 0x00 0x84 0x0a 0x4f + 0x00 0x84 0x13 0x0f + 0x00 0x84 0x14 0x4f + 0x00 0x84 0x25 0x0f + 0x00 0x84 0x26 0x4f + 0x00 0x54 0x09 0x2f + 0x00 0x54 0x0a 0x6f + 0x00 0x54 0x13 0x2f + 0x00 0x54 0x14 0x6f + 0x00 0x54 0x25 0x2f + 0x00 0x54 0x26 0x6f + 0x00 0x54 0x47 0x6f + 0x00 0x9c 0x09 0x0f + 0x00 0x9c 0x0a 0x4f + 0x00 0x9c 0x13 0x0f + 0x00 0x9c 0x14 0x4f + 0x00 0x9c 0x25 0x0f + 0x00 0x9c 0x26 0x4f + 0x00 0x8c 0x09 0x2f + 0x00 0x8c 0x0a 0x6f + 0x00 0x8c 0x13 0x2f + 0x00 0x8c 0x14 0x6f + 0x00 0x8c 0x25 0x2f + 0x00 0x8c 0x26 0x6f + 0x00 0x64 0x09 0x2f + 0x00 0x64 0x0a 0x6f + 0x00 0x64 0x13 0x2f + 0x00 0x64 0x14 0x6f + 0x00 0x64 0x25 0x2f + 0x00 0x64 0x26 0x6f + 0x00 0x64 0x47 0x6f + 0x00 0x74 0x09 0x0f + 0x00 0x74 0x0a 0x4f + 0x00 0x74 0x13 0x0f + 0x00 0x74 0x14 0x4f + 0x00 0x74 0x25 0x0f + 0x00 0x74 0x26 0x4f + 0x00 0x74 0x47 0x4f + 0x00 0x94 0x09 0x0f + 0x00 0x94 0x0a 0x4f + 0x00 0x94 0x13 0x0f + 0x00 0x94 0x14 0x4f + 0x00 0x94 0x25 0x0f + 0x00 0x94 0x26 0x4f + 0x00 0x84 0x09 0x2f + 0x00 0x84 0x0a 0x6f + 0x00 0x84 0x13 0x2f + 0x00 0x84 0x14 0x6f + 0x00 0x84 0x25 0x2f + 0x00 0x84 0x26 0x6f + 0x00 0x44 0x09 0x2f + 0x00 0x44 0x0a 0x6f + 0x00 0x44 0x13 0x2f + 0x00 0x44 0x14 0x6f + 0x00 0x44 0x25 0x2f + 0x00 0x44 0x26 0x6f + 0x00 0x44 0x47 0x6f + 0x00 0x24 0x09 0x0f + 0x00 0x24 0x0a 0x4f + 0x00 0x24 0x13 0x0f + 0x00 0x24 0x14 0x4f + 0x00 0x24 0x25 0x0f + 0x00 0x24 0x26 0x4f + 0x00 0x24 0x47 0x4f + 0x00 0x34 0x09 0x0f + 0x00 0x34 0x0a 0x4f + 0x00 0x34 0x13 0x0f + 0x00 0x34 0x14 0x4f + 0x00 0x34 0x25 0x0f + 0x00 0x34 0x26 0x4f + 0x00 0x34 0x47 0x4f + 0x00 0xa4 0x09 0x0f + 0x00 0xa4 0x0a 0x4f + 0x00 0xa4 0x13 0x0f + 0x00 0xa4 0x14 0x4f + 0x00 0xa4 0x25 0x0f + 0x00 0xa4 0x26 0x4f + 0x00 0x04 0x09 0x0f + 0x00 0x04 0x0a 0x4f + 0x00 0x04 0x13 0x0f + 0x00 0x04 0x14 0x4f + 0x00 0x04 0x25 0x0f + 0x00 0x04 0x26 0x4f + 0x00 0x04 0x47 0x4f + 0x00 0x04 0x09 0x0f + 0x00 0x14 0x0a 0x4f + 0x00 0x14 0x13 0x0f + 0x00 0x14 0x14 0x4f + 0x00 0x14 0x25 0x0f + 0x00 0x14 0x26 0x4f + 0x00 0x14 0x47 0x4f + 0x00 0x14 0x40 0x5f + 0x00 0xe4 0x21 0x2f + 0x00 0xe4 0x22 0x6f + 0x00 0xe4 0x43 0x6f + 0x00 0x9c 0x09 0x2f + 0x00 0x9c 0x0a 0x6f + 0x00 0x9c 0x13 0x2f + 0x00 0x9c 0x14 0x6f + 0x00 0x9c 0x25 0x2f + 0x00 0x9c 0x26 0x6f + 0x00 0x74 0x09 0x2f + 0x00 0x74 0x0a 0x6f + 0x00 0x74 0x13 0x2f + 0x00 0x74 0x14 0x6f + 0x00 0x74 0x25 0x2f + 0x00 0x74 0x26 0x6f + 0x00 0x74 0x47 0x6f + 0x00 0x94 0x09 0x2f + 0x00 0x94 0x0a 0x6f + 0x00 0x94 0x13 0x2f + 0x00 0x94 0x14 0x6f + 0x00 0x94 0x25 0x2f + 0x00 0x94 0x26 0x6f + 0x00 0x24 0x09 0x2f + 0x00 0x24 0x0a 0x6f + 0x00 0x24 0x13 0x2f + 0x00 0x24 0x14 0x6f + 0x00 0x24 0x25 0x2f + 0x00 0x24 0x26 0x6f + 0x00 0x24 0x47 0x6f + 0x00 0x34 0x09 0x2f + 0x00 0x34 0x0a 0x6f + 0x00 0x34 0x13 0x2f + 0x00 0x34 0x14 0x6f + 0x00 0x34 0x25 0x2f + 0x00 0x34 0x26 0x6f + 0x00 0x34 0x47 0x6f + 0x00 0xa4 0x09 0x2f + 0x00 0xa4 0x0a 0x6f + 0x00 0xa4 0x13 0x2f + 0x00 0xa4 0x14 0x6f + 0x00 0xa4 0x25 0x2f + 0x00 0xa4 0x26 0x6f + 0x00 0x04 0x09 0x2f + 0x00 0x04 0x0a 0x6f + 0x00 0x04 0x13 0x2f + 0x00 0x04 0x14 0x6f + 0x00 0x04 0x25 0x2f + 0x00 0x04 0x26 0x6f + 0x00 0x04 0x47 0x6f + 0x00 0x14 0x09 0x2f + 0x00 0x14 0x0a 0x6f + 0x00 0x14 0x13 0x2f + 0x00 0x14 0x14 0x6f + 0x00 0x14 0x25 0x2f + 0x00 0x14 0x26 0x6f + 0x00 0x14 0x47 0x6f + +# CHECK: fcvtzs.2s v0, v0, #31 +# CHECK: fcvtzs.4s v0, v0, #30 +# CHECK: fcvtzs.2d v0, v0, #61 +# CHECK: fcvtzu.2s v0, v0, #31 +# CHECK: fcvtzu.4s v0, v0, #30 +# CHECK: fcvtzu.2d v0, v0, #61 +# CHECK: rshrn.8b v0, v0, #7 +# CHECK: rshrn2.16b v0, v0, #6 +# CHECK: rshrn.4h v0, v0, #13 +# CHECK: rshrn2.8h v0, v0, #12 +# CHECK: rshrn.2s v0, v0, #27 +# CHECK: rshrn2.4s v0, v0, #26 +# CHECK: scvtf.2s v0, v0, #31 +# CHECK: scvtf.4s v0, v0, #30 +# CHECK: scvtf.2d v0, v0, #61 +# CHECK: shl.8b v0, v0, #1 +# CHECK: shl.16b v0, v0, #2 +# CHECK: shl.4h v0, v0, #3 +# CHECK: shl.8h v0, v0, #4 +# CHECK: shl.2s v0, v0, #5 +# CHECK: shl.4s v0, v0, #6 +# CHECK: shl.2d v0, v0, #7 +# CHECK: shrn.8b v0, v0, #7 +# CHECK: shrn2.16b v0, v0, #6 +# CHECK: shrn.4h v0, v0, #13 +# CHECK: shrn2.8h v0, v0, #12 +# CHECK: shrn.2s v0, v0, #27 +# CHECK: shrn2.4s v0, v0, #26 +# CHECK: sli.8b v0, v0, #1 +# CHECK: sli.16b v0, v0, #2 +# CHECK: sli.4h v0, v0, #3 +# CHECK: sli.8h v0, v0, #4 +# CHECK: sli.2s v0, v0, #5 +# CHECK: sli.4s v0, v0, #6 +# CHECK: sli.2d v0, v0, #7 +# CHECK: sqrshrn.8b v0, v0, #7 +# CHECK: sqrshrn2.16b v0, v0, #6 +# CHECK: sqrshrn.4h v0, v0, #13 +# CHECK: sqrshrn2.8h v0, v0, #12 +# CHECK: sqrshrn.2s v0, v0, #27 +# CHECK: sqrshrn2.4s v0, v0, #26 +# CHECK: sqrshrun.8b v0, v0, #7 +# CHECK: sqrshrun2.16b v0, v0, #6 +# CHECK: sqrshrun.4h v0, v0, #13 +# CHECK: sqrshrun2.8h v0, v0, #12 +# CHECK: sqrshrun.2s v0, v0, #27 +# CHECK: sqrshrun2.4s v0, v0, #26 +# CHECK: sqshlu.8b v0, v0, #1 +# CHECK: sqshlu.16b v0, v0, #2 +# CHECK: sqshlu.4h v0, v0, #3 +# CHECK: sqshlu.8h v0, v0, #4 +# CHECK: sqshlu.2s v0, v0, #5 +# CHECK: sqshlu.4s v0, v0, #6 +# CHECK: sqshlu.2d v0, v0, #7 +# CHECK: sqshl.8b v0, v0, #1 +# CHECK: sqshl.16b v0, v0, #2 +# CHECK: sqshl.4h v0, v0, #3 +# CHECK: sqshl.8h v0, v0, #4 +# CHECK: sqshl.2s v0, v0, #5 +# CHECK: sqshl.4s v0, v0, #6 +# CHECK: sqshl.2d v0, v0, #7 +# CHECK: sqshrn.8b v0, v0, #7 +# CHECK: sqshrn2.16b v0, v0, #6 +# CHECK: sqshrn.4h v0, v0, #13 +# CHECK: sqshrn2.8h v0, v0, #12 +# CHECK: sqshrn.2s v0, v0, #27 +# CHECK: sqshrn2.4s v0, v0, #26 +# CHECK: sqshrun.8b v0, v0, #7 +# CHECK: sqshrun2.16b v0, v0, #6 +# CHECK: sqshrun.4h v0, v0, #13 +# CHECK: sqshrun2.8h v0, v0, #12 +# CHECK: sqshrun.2s v0, v0, #27 +# CHECK: sqshrun2.4s v0, v0, #26 +# CHECK: sri.8b v0, v0, #7 +# CHECK: sri.16b v0, v0, #6 +# CHECK: sri.4h v0, v0, #13 +# CHECK: sri.8h v0, v0, #12 +# CHECK: sri.2s v0, v0, #27 +# CHECK: sri.4s v0, v0, #26 +# CHECK: sri.2d v0, v0, #57 +# CHECK: srshr.8b v0, v0, #7 +# CHECK: srshr.16b v0, v0, #6 +# CHECK: srshr.4h v0, v0, #13 +# CHECK: srshr.8h v0, v0, #12 +# CHECK: srshr.2s v0, v0, #27 +# CHECK: srshr.4s v0, v0, #26 +# CHECK: srshr.2d v0, v0, #57 +# CHECK: srsra.8b v0, v0, #7 +# CHECK: srsra.16b v0, v0, #6 +# CHECK: srsra.4h v0, v0, #13 +# CHECK: srsra.8h v0, v0, #12 +# CHECK: srsra.2s v0, v0, #27 +# CHECK: srsra.4s v0, v0, #26 +# CHECK: srsra.2d v0, v0, #57 +# CHECK: sshll.8h v0, v0, #1 +# CHECK: sshll2.8h v0, v0, #2 +# CHECK: sshll.4s v0, v0, #3 +# CHECK: sshll2.4s v0, v0, #4 +# CHECK: sshll.2d v0, v0, #5 +# CHECK: sshll2.2d v0, v0, #6 +# CHECK: sshr.8b v0, v0, #7 +# CHECK: sshr.16b v0, v0, #6 +# CHECK: sshr.4h v0, v0, #13 +# CHECK: sshr.8h v0, v0, #12 +# CHECK: sshr.2s v0, v0, #27 +# CHECK: sshr.4s v0, v0, #26 +# CHECK: sshr.2d v0, v0, #57 +# CHECK: sshr.8b v0, v0, #7 +# CHECK: ssra.16b v0, v0, #6 +# CHECK: ssra.4h v0, v0, #13 +# CHECK: ssra.8h v0, v0, #12 +# CHECK: ssra.2s v0, v0, #27 +# CHECK: ssra.4s v0, v0, #26 +# CHECK: ssra.2d v0, v0, #57 +# CHECK: ssra d0, d0, #64 +# CHECK: ucvtf.2s v0, v0, #31 +# CHECK: ucvtf.4s v0, v0, #30 +# CHECK: ucvtf.2d v0, v0, #61 +# CHECK: uqrshrn.8b v0, v0, #7 +# CHECK: uqrshrn2.16b v0, v0, #6 +# CHECK: uqrshrn.4h v0, v0, #13 +# CHECK: uqrshrn2.8h v0, v0, #12 +# CHECK: uqrshrn.2s v0, v0, #27 +# CHECK: uqrshrn2.4s v0, v0, #26 +# CHECK: uqshl.8b v0, v0, #1 +# CHECK: uqshl.16b v0, v0, #2 +# CHECK: uqshl.4h v0, v0, #3 +# CHECK: uqshl.8h v0, v0, #4 +# CHECK: uqshl.2s v0, v0, #5 +# CHECK: uqshl.4s v0, v0, #6 +# CHECK: uqshl.2d v0, v0, #7 +# CHECK: uqshrn.8b v0, v0, #7 +# CHECK: uqshrn2.16b v0, v0, #6 +# CHECK: uqshrn.4h v0, v0, #13 +# CHECK: uqshrn2.8h v0, v0, #12 +# CHECK: uqshrn.2s v0, v0, #27 +# CHECK: uqshrn2.4s v0, v0, #26 +# CHECK: urshr.8b v0, v0, #7 +# CHECK: urshr.16b v0, v0, #6 +# CHECK: urshr.4h v0, v0, #13 +# CHECK: urshr.8h v0, v0, #12 +# CHECK: urshr.2s v0, v0, #27 +# CHECK: urshr.4s v0, v0, #26 +# CHECK: urshr.2d v0, v0, #57 +# CHECK: ursra.8b v0, v0, #7 +# CHECK: ursra.16b v0, v0, #6 +# CHECK: ursra.4h v0, v0, #13 +# CHECK: ursra.8h v0, v0, #12 +# CHECK: ursra.2s v0, v0, #27 +# CHECK: ursra.4s v0, v0, #26 +# CHECK: ursra.2d v0, v0, #57 +# CHECK: ushll.8h v0, v0, #1 +# CHECK: ushll2.8h v0, v0, #2 +# CHECK: ushll.4s v0, v0, #3 +# CHECK: ushll2.4s v0, v0, #4 +# CHECK: ushll.2d v0, v0, #5 +# CHECK: ushll2.2d v0, v0, #6 +# CHECK: ushr.8b v0, v0, #7 +# CHECK: ushr.16b v0, v0, #6 +# CHECK: ushr.4h v0, v0, #13 +# CHECK: ushr.8h v0, v0, #12 +# CHECK: ushr.2s v0, v0, #27 +# CHECK: ushr.4s v0, v0, #26 +# CHECK: ushr.2d v0, v0, #57 +# CHECK: usra.8b v0, v0, #7 +# CHECK: usra.16b v0, v0, #6 +# CHECK: usra.4h v0, v0, #13 +# CHECK: usra.8h v0, v0, #12 +# CHECK: usra.2s v0, v0, #27 +# CHECK: usra.4s v0, v0, #26 +# CHECK: usra.2d v0, v0, #57 + + + 0x00 0xe0 0x20 0x0e + 0x00 0xe0 0x20 0x4e + 0x00 0xe0 0xe0 0x0e + 0x00 0xe0 0xe0 0x4e + +# CHECK: pmull.8h v0, v0, v0 +# CHECK: pmull2.8h v0, v0, v0 +# CHECK: pmull.1q v0, v0, v0 +# CHECK: pmull2.1q v0, v0, v0 + + 0x41 0xd8 0x70 0x7e + 0x83 0xd8 0x30 0x7e +# CHECK: faddp.2d d1, v2 +# CHECK: faddp.2s s3, v4 + + 0x82 0x60 0x01 0x4e + 0x80 0x60 0x01 0x0e + 0xa2 0x00 0x01 0x4e + 0xa0 0x00 0x01 0x0e + 0xa2 0x40 0x01 0x4e + 0xa0 0x40 0x01 0x0e + 0xc2 0x20 0x01 0x4e + 0xc0 0x20 0x01 0x0e + +# CHECK: tbl.16b v2, { v4, v5, v6, v7 }, v1 +# CHECK: tbl.8b v0, { v4, v5, v6, v7 }, v1 +# CHECK: tbl.16b v2, { v5 }, v1 +# CHECK: tbl.8b v0, { v5 }, v1 +# CHECK: tbl.16b v2, { v5, v6, v7 }, v1 +# CHECK: tbl.8b v0, { v5, v6, v7 }, v1 +# CHECK: tbl.16b v2, { v6, v7 }, v1 +# CHECK: tbl.8b v0, { v6, v7 }, v1 +# + 0x82 0x70 0x01 0x4e + 0x80 0x70 0x01 0x0e + 0xa2 0x10 0x01 0x4e + 0xa0 0x10 0x01 0x0e + 0xa2 0x50 0x01 0x4e + 0xa0 0x50 0x01 0x0e + 0xc2 0x30 0x01 0x4e + 0xc0 0x30 0x01 0x0e + +# CHECK: tbx.16b v2, { v4, v5, v6, v7 }, v1 +# CHECK: tbx.8b v0, { v4, v5, v6, v7 }, v1 +# CHECK: tbx.16b v2, { v5 }, v1 +# CHECK: tbx.8b v0, { v5 }, v1 +# CHECK: tbx.16b v2, { v5, v6, v7 }, v1 +# CHECK: tbx.8b v0, { v5, v6, v7 }, v1 +# CHECK: tbx.16b v2, { v6, v7 }, v1 +# CHECK: tbx.8b v0, { v6, v7 }, v1 +# + +0x00 0x80 0x20 0x0e +0x00 0x80 0x20 0x4e +0x00 0x80 0xa0 0x0e +0x00 0x80 0xa0 0x4e + +# CHECK: smlal.8h v0, v0, v0 +# CHECK: smlal2.8h v0, v0, v0 +# CHECK: smlal.2d v0, v0, v0 +# CHECK: smlal2.2d v0, v0, v0 + +0x00 0x80 0x20 0x2e +0x00 0x80 0x20 0x6e +0x00 0x80 0xa0 0x2e +0x00 0x80 0xa0 0x6e + +# CHECK: umlal.8h v0, v0, v0 +# CHECK: umlal2.8h v0, v0, v0 +# CHECK: umlal.2d v0, v0, v0 +# CHECK: umlal2.2d v0, v0, v0 + +0x00 0x90 0x60 0x5e +0x00 0x90 0xa0 0x5e +0x00 0xb0 0x60 0x5e +0x00 0xb0 0xa0 0x5e + +# CHECK: sqdmlal s0, h0, h0 +# CHECK: sqdmlal d0, s0, s0 +# CHECK: sqdmlsl s0, h0, h0 +# CHECK: sqdmlsl d0, s0, s0 + +0xaa 0xc5 0xc7 0x4d +0xaa 0xc9 0xc7 0x4d +0xaa 0xc1 0xc7 0x4d + +# CHECK: ld1r.8h { v10 }, [x13], x7 +# CHECK: ld1r.4s { v10 }, [x13], x7 +# CHECK: ld1r.16b { v10 }, [x13], x7 + +0x00 0xd0 0x60 0x5e +0x00 0xd0 0xa0 0x5e +# CHECK: sqdmull s0, h0, h0 +# CHECK: sqdmull d0, s0, s0 + +0x00 0xd8 0xa1 0x7e +0x00 0xd8 0xe1 0x7e + +# CHECK: frsqrte s0, s0 +# CHECK: frsqrte d0, d0 + +0xca 0xcd 0xc7 0x4d +0xea 0xc9 0xe7 0x4d +0xea 0xe9 0xc7 0x4d +0xea 0xe9 0xe7 0x4d +# CHECK: ld1r.2d { v10 }, [x14], x7 +# CHECK: ld2r.4s { v10, v11 }, [x15], x7 +# CHECK: ld3r.4s { v10, v11, v12 }, [x15], x7 +# CHECK: ld4r.4s { v10, v11, v12, v13 }, [x15], x7 + +#===-------------------------------------------------------------------------=== +# AdvSIMD scalar three same +#===-------------------------------------------------------------------------=== +0x62 0xdc 0x21 0x5e +# CHECK: fmulx s2, s3, s1 +0x62 0xdc 0x61 0x5e +# CHECK: fmulx d2, d3, d1 + + +# rdar://12511369 +0xe8 0x6b 0xdf 0x4c +# CHECK: ld1.4s { v8, v9, v10 }, [sp], #48 diff --git a/test/MC/Disassembler/AArch64/arm64-arithmetic.txt b/test/MC/Disassembler/AArch64/arm64-arithmetic.txt new file mode 100644 index 0000000..bd870ed --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-arithmetic.txt @@ -0,0 +1,526 @@ +# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s + +#==---------------------------------------------------------------------------== +# Add/Subtract with carry/borrow +#==---------------------------------------------------------------------------== + +0x41 0x00 0x03 0x1a +0x41 0x00 0x03 0x9a +0x85 0x00 0x03 0x3a +0x85 0x00 0x03 0xba + +# CHECK: adc w1, w2, w3 +# CHECK: adc x1, x2, x3 +# CHECK: adcs w5, w4, w3 +# CHECK: adcs x5, x4, x3 + +0x41 0x00 0x03 0x5a +0x41 0x00 0x03 0xda +0x41 0x00 0x03 0x7a +0x41 0x00 0x03 0xfa + +# CHECK: sbc w1, w2, w3 +# CHECK: sbc x1, x2, x3 +# CHECK: sbcs w1, w2, w3 +# CHECK: sbcs x1, x2, x3 + +#==---------------------------------------------------------------------------== +# Add/Subtract with (optionally shifted) immediate +#==---------------------------------------------------------------------------== + +0x83 0x00 0x10 0x11 +0x83 0x00 0x10 0x91 + +# CHECK: add w3, w4, #1024 +# CHECK: add x3, x4, #1024 + +0x83 0x00 0x50 0x11 +0x83 0x00 0x40 0x11 +0x83 0x00 0x50 0x91 +0x83 0x00 0x40 0x91 +0xff 0x83 0x00 0x91 + +# CHECK: add w3, w4, #1024, lsl #12 +# CHECK: add x3, x4, #1024, lsl #12 +# CHECK: add x3, x4, #0, lsl #12 +# CHECK: add sp, sp, #32 + +0x83 0x00 0x10 0x31 +0x83 0x00 0x50 0x31 +0x83 0x00 0x10 0xb1 +0x83 0x00 0x50 0xb1 +0xff 0x83 0x00 0xb1 + +# CHECK: adds w3, w4, #1024 +# CHECK: adds w3, w4, #1024, lsl #12 +# CHECK: adds x3, x4, #1024 +# CHECK: adds x3, x4, #1024, lsl #12 +# CHECK: cmn sp, #32 + +0x83 0x00 0x10 0x51 +0x83 0x00 0x50 0x51 +0x83 0x00 0x10 0xd1 +0x83 0x00 0x50 0xd1 +0xff 0x83 0x00 0xd1 + +# CHECK: sub w3, w4, #1024 +# CHECK: sub w3, w4, #1024, lsl #12 +# CHECK: sub x3, x4, #1024 +# CHECK: sub x3, x4, #1024, lsl #12 +# CHECK: sub sp, sp, #32 + +0x83 0x00 0x10 0x71 +0x83 0x00 0x50 0x71 +0x83 0x00 0x10 0xf1 +0x83 0x00 0x50 0xf1 +0xff 0x83 0x00 0xf1 + +# CHECK: subs w3, w4, #1024 +# CHECK: subs w3, w4, #1024, lsl #12 +# CHECK: subs x3, x4, #1024 +# CHECK: subs x3, x4, #1024, lsl #12 +# CHECK: cmp sp, #32 + +#==---------------------------------------------------------------------------== +# Add/Subtract register with (optional) shift +#==---------------------------------------------------------------------------== + +0xac 0x01 0x0e 0x0b +0xac 0x01 0x0e 0x8b +0xac 0x31 0x0e 0x0b +0xac 0x31 0x0e 0x8b +0xac 0x29 0x4e 0x0b +0xac 0x29 0x4e 0x8b +0xac 0x1d 0x8e 0x0b +0xac 0x9d 0x8e 0x8b + +# CHECK: add w12, w13, w14 +# CHECK: add x12, x13, x14 +# CHECK: add w12, w13, w14, lsl #12 +# CHECK: add x12, x13, x14, lsl #12 +# CHECK: add w12, w13, w14, lsr #10 +# CHECK: add x12, x13, x14, lsr #10 +# CHECK: add w12, w13, w14, asr #7 +# CHECK: add x12, x13, x14, asr #39 + +0xac 0x01 0x0e 0x4b +0xac 0x01 0x0e 0xcb +0xac 0x31 0x0e 0x4b +0xac 0x31 0x0e 0xcb +0xac 0x29 0x4e 0x4b +0xac 0x29 0x4e 0xcb +0xac 0x1d 0x8e 0x4b +0xac 0x9d 0x8e 0xcb + +# CHECK: sub w12, w13, w14 +# CHECK: sub x12, x13, x14 +# CHECK: sub w12, w13, w14, lsl #12 +# CHECK: sub x12, x13, x14, lsl #12 +# CHECK: sub w12, w13, w14, lsr #10 +# CHECK: sub x12, x13, x14, lsr #10 +# CHECK: sub w12, w13, w14, asr #7 +# CHECK: sub x12, x13, x14, asr #39 + +0xac 0x01 0x0e 0x2b +0xac 0x01 0x0e 0xab +0xac 0x31 0x0e 0x2b +0xac 0x31 0x0e 0xab +0xac 0x29 0x4e 0x2b +0xac 0x29 0x4e 0xab +0xac 0x1d 0x8e 0x2b +0xac 0x9d 0x8e 0xab + +# CHECK: adds w12, w13, w14 +# CHECK: adds x12, x13, x14 +# CHECK: adds w12, w13, w14, lsl #12 +# CHECK: adds x12, x13, x14, lsl #12 +# CHECK: adds w12, w13, w14, lsr #10 +# CHECK: adds x12, x13, x14, lsr #10 +# CHECK: adds w12, w13, w14, asr #7 +# CHECK: adds x12, x13, x14, asr #39 + +0xac 0x01 0x0e 0x6b +0xac 0x01 0x0e 0xeb +0xac 0x31 0x0e 0x6b +0xac 0x31 0x0e 0xeb +0xac 0x29 0x4e 0x6b +0xac 0x29 0x4e 0xeb +0xac 0x1d 0x8e 0x6b +0xac 0x9d 0x8e 0xeb + +# CHECK: subs w12, w13, w14 +# CHECK: subs x12, x13, x14 +# CHECK: subs w12, w13, w14, lsl #12 +# CHECK: subs x12, x13, x14, lsl #12 +# CHECK: subs w12, w13, w14, lsr #10 +# CHECK: subs x12, x13, x14, lsr #10 +# CHECK: subs w12, w13, w14, asr #7 +# CHECK: subs x12, x13, x14, asr #39 + +#==---------------------------------------------------------------------------== +# Add/Subtract with (optional) extend +#==---------------------------------------------------------------------------== + +0x41 0x00 0x23 0x0b +0x41 0x20 0x23 0x0b +0x41 0x40 0x23 0x0b +0x41 0x60 0x23 0x0b +0x41 0x80 0x23 0x0b +0x41 0xa0 0x23 0x0b +0x41 0xc0 0x23 0x0b +0x41 0xe0 0x23 0x0b + +# CHECK: add w1, w2, w3, uxtb +# CHECK: add w1, w2, w3, uxth +# CHECK: add w1, w2, w3 +# CHECK: add w1, w2, w3, uxtx +# CHECK: add w1, w2, w3, sxtb +# CHECK: add w1, w2, w3, sxth +# CHECK: add w1, w2, w3, sxtw +# CHECK: add w1, w2, w3, sxtx + +0x41 0x00 0x23 0x8b +0x41 0x20 0x23 0x8b +0x41 0x40 0x23 0x8b +0x41 0x80 0x23 0x8b +0x41 0xa0 0x23 0x8b +0x41 0xc0 0x23 0x8b + +# CHECK: add x1, x2, w3, uxtb +# CHECK: add x1, x2, w3, uxth +# CHECK: add x1, x2, w3, uxtw +# CHECK: add x1, x2, w3, sxtb +# CHECK: add x1, x2, w3, sxth +# CHECK: add x1, x2, w3, sxtw + +0xe1 0x43 0x23 0x0b +0xe1 0x43 0x23 0x0b +0x5f 0x60 0x23 0x8b +0x5f 0x60 0x23 0x8b + +# CHECK: add w1, wsp, w3 +# CHECK: add w1, wsp, w3 +# CHECK: add sp, x2, x3 +# CHECK: add sp, x2, x3 + +0x41 0x00 0x23 0x4b +0x41 0x20 0x23 0x4b +0x41 0x40 0x23 0x4b +0x41 0x60 0x23 0x4b +0x41 0x80 0x23 0x4b +0x41 0xa0 0x23 0x4b +0x41 0xc0 0x23 0x4b +0x41 0xe0 0x23 0x4b + +# CHECK: sub w1, w2, w3, uxtb +# CHECK: sub w1, w2, w3, uxth +# CHECK: sub w1, w2, w3 +# CHECK: sub w1, w2, w3, uxtx +# CHECK: sub w1, w2, w3, sxtb +# CHECK: sub w1, w2, w3, sxth +# CHECK: sub w1, w2, w3, sxtw +# CHECK: sub w1, w2, w3, sxtx + +0x41 0x00 0x23 0xcb +0x41 0x20 0x23 0xcb +0x41 0x40 0x23 0xcb +0x41 0x80 0x23 0xcb +0x41 0xa0 0x23 0xcb +0x41 0xc0 0x23 0xcb + +# CHECK: sub x1, x2, w3, uxtb +# CHECK: sub x1, x2, w3, uxth +# CHECK: sub x1, x2, w3, uxtw +# CHECK: sub x1, x2, w3, sxtb +# CHECK: sub x1, x2, w3, sxth +# CHECK: sub x1, x2, w3, sxtw + +0xe1 0x43 0x23 0x4b +0xe1 0x43 0x23 0x4b +0x5f 0x60 0x23 0xcb +0x5f 0x60 0x23 0xcb + +# CHECK: sub w1, wsp, w3 +# CHECK: sub w1, wsp, w3 +# CHECK: sub sp, x2, x3 +# CHECK: sub sp, x2, x3 + +0x41 0x00 0x23 0x2b +0x41 0x20 0x23 0x2b +0x41 0x40 0x23 0x2b +0x41 0x60 0x23 0x2b +0x41 0x80 0x23 0x2b +0x41 0xa0 0x23 0x2b +0x41 0xc0 0x23 0x2b +0x41 0xe0 0x23 0x2b + +# CHECK: adds w1, w2, w3, uxtb +# CHECK: adds w1, w2, w3, uxth +# CHECK: adds w1, w2, w3 +# CHECK: adds w1, w2, w3, uxtx +# CHECK: adds w1, w2, w3, sxtb +# CHECK: adds w1, w2, w3, sxth +# CHECK: adds w1, w2, w3, sxtw +# CHECK: adds w1, w2, w3, sxtx + +0x41 0x00 0x23 0xab +0x41 0x20 0x23 0xab +0x41 0x40 0x23 0xab +0x41 0x80 0x23 0xab +0x41 0xa0 0x23 0xab +0x41 0xc0 0x23 0xab + +# CHECK: adds x1, x2, w3, uxtb +# CHECK: adds x1, x2, w3, uxth +# CHECK: adds x1, x2, w3, uxtw +# CHECK: adds x1, x2, w3, sxtb +# CHECK: adds x1, x2, w3, sxth +# CHECK: adds x1, x2, w3, sxtw + +0xe1 0x43 0x23 0x2b +0xe1 0x43 0x23 0x2b + +# CHECK: adds w1, wsp, w3 +# CHECK: adds w1, wsp, w3 + +0x41 0x00 0x23 0x6b +0x41 0x20 0x23 0x6b +0x41 0x40 0x23 0x6b +0x41 0x60 0x23 0x6b +0x41 0x80 0x23 0x6b +0x41 0xa0 0x23 0x6b +0x41 0xc0 0x23 0x6b +0x41 0xe0 0x23 0x6b + +# CHECK: subs w1, w2, w3, uxtb +# CHECK: subs w1, w2, w3, uxth +# CHECK: subs w1, w2, w3 +# CHECK: subs w1, w2, w3, uxtx +# CHECK: subs w1, w2, w3, sxtb +# CHECK: subs w1, w2, w3, sxth +# CHECK: subs w1, w2, w3, sxtw +# CHECK: subs w1, w2, w3, sxtx + +0x41 0x00 0x23 0xeb +0x41 0x20 0x23 0xeb +0x41 0x40 0x23 0xeb +0x41 0x80 0x23 0xeb +0x41 0xa0 0x23 0xeb +0x41 0xc0 0x23 0xeb + +# CHECK: subs x1, x2, w3, uxtb +# CHECK: subs x1, x2, w3, uxth +# CHECK: subs x1, x2, w3, uxtw +# CHECK: subs x1, x2, w3, sxtb +# CHECK: subs x1, x2, w3, sxth +# CHECK: subs x1, x2, w3, sxtw + +0xe1 0x43 0x23 0x6b +0xe1 0x43 0x23 0x6b + +# CHECK: subs w1, wsp, w3 +# CHECK: subs w1, wsp, w3 + +0x1f 0x41 0x28 0xeb +0x3f 0x41 0x28 0x6b +0xff 0x43 0x28 0x6b +0xff 0x43 0x28 0xeb + +# CHECK: cmp x8, w8, uxtw +# CHECK: cmp w9, w8, uxtw +# CHECK: cmp wsp, w8 +# CHECK: cmp sp, w8 + +0x3f 0x41 0x28 0x4b +0xe1 0x43 0x28 0x4b +0xff 0x43 0x28 0x4b +0x3f 0x41 0x28 0xcb +0xe1 0x43 0x28 0xcb +0xff 0x43 0x28 0xcb +0xe1 0x43 0x28 0x6b +0xe1 0x43 0x28 0xeb + +# CHECK: sub wsp, w9, w8 +# CHECK: sub w1, wsp, w8 +# CHECK: sub wsp, wsp, w8 +# CHECK: sub sp, x9, w8 +# CHECK: sub x1, sp, w8 +# CHECK: sub sp, sp, w8 +# CHECK: subs w1, wsp, w8 +# CHECK: subs x1, sp, w8 + +#==---------------------------------------------------------------------------== +# Signed/Unsigned divide +#==---------------------------------------------------------------------------== + +0x41 0x0c 0xc3 0x1a +0x41 0x0c 0xc3 0x9a +0x41 0x08 0xc3 0x1a +0x41 0x08 0xc3 0x9a + +# CHECK: sdiv w1, w2, w3 +# CHECK: sdiv x1, x2, x3 +# CHECK: udiv w1, w2, w3 +# CHECK: udiv x1, x2, x3 + +#==---------------------------------------------------------------------------== +# Variable shifts +#==---------------------------------------------------------------------------== + + 0x41 0x28 0xc3 0x1a +# CHECK: asr w1, w2, w3 + 0x41 0x28 0xc3 0x9a +# CHECK: asr x1, x2, x3 + 0x41 0x20 0xc3 0x1a +# CHECK: lsl w1, w2, w3 + 0x41 0x20 0xc3 0x9a +# CHECK: lsl x1, x2, x3 + 0x41 0x24 0xc3 0x1a +# CHECK: lsr w1, w2, w3 + 0x41 0x24 0xc3 0x9a +# CHECK: lsr x1, x2, x3 + 0x41 0x2c 0xc3 0x1a +# CHECK: ror w1, w2, w3 + 0x41 0x2c 0xc3 0x9a +# CHECK: ror x1, x2, x3 + +#==---------------------------------------------------------------------------== +# One operand instructions +#==---------------------------------------------------------------------------== + + 0x41 0x14 0xc0 0x5a +# CHECK: cls w1, w2 + 0x41 0x14 0xc0 0xda +# CHECK: cls x1, x2 + 0x41 0x10 0xc0 0x5a +# CHECK: clz w1, w2 + 0x41 0x10 0xc0 0xda +# CHECK: clz x1, x2 + 0x41 0x00 0xc0 0x5a +# CHECK: rbit w1, w2 + 0x41 0x00 0xc0 0xda +# CHECK: rbit x1, x2 + 0x41 0x08 0xc0 0x5a +# CHECK: rev w1, w2 + 0x41 0x0c 0xc0 0xda +# CHECK: rev x1, x2 + 0x41 0x04 0xc0 0x5a +# CHECK: rev16 w1, w2 + 0x41 0x04 0xc0 0xda +# CHECK: rev16 x1, x2 + 0x41 0x08 0xc0 0xda +# CHECK: rev32 x1, x2 + +#==---------------------------------------------------------------------------== +# 6.6.1 Multiply-add instructions +#==---------------------------------------------------------------------------== + +0x41 0x10 0x03 0x1b +0x41 0x10 0x03 0x9b +0x41 0x90 0x03 0x1b +0x41 0x90 0x03 0x9b +0x41 0x10 0x23 0x9b +0x41 0x90 0x23 0x9b +0x41 0x10 0xa3 0x9b +0x41 0x90 0xa3 0x9b + +# CHECK: madd w1, w2, w3, w4 +# CHECK: madd x1, x2, x3, x4 +# CHECK: msub w1, w2, w3, w4 +# CHECK: msub x1, x2, x3, x4 +# CHECK: smaddl x1, w2, w3, x4 +# CHECK: smsubl x1, w2, w3, x4 +# CHECK: umaddl x1, w2, w3, x4 +# CHECK: umsubl x1, w2, w3, x4 + +#==---------------------------------------------------------------------------== +# Multiply-high instructions +#==---------------------------------------------------------------------------== + +0x41 0x7c 0x43 0x9b +0x41 0x7c 0xc3 0x9b + +# CHECK: smulh x1, x2, x3 +# CHECK: umulh x1, x2, x3 + +#==---------------------------------------------------------------------------== +# Move immediate instructions +#==---------------------------------------------------------------------------== + +0x20 0x00 0x80 0x52 +0x20 0x00 0x80 0xd2 +0x20 0x00 0xa0 0x52 +0x20 0x00 0xa0 0xd2 + +# CHECK: movz w0, #0x1 +# CHECK: movz x0, #0x1 +# CHECK: movz w0, #0x1, lsl #16 +# CHECK: movz x0, #0x1, lsl #16 + +0x40 0x00 0x80 0x12 +0x40 0x00 0x80 0x92 +0x40 0x00 0xa0 0x12 +0x40 0x00 0xa0 0x92 + +# CHECK: movn w0, #0x2 +# CHECK: movn x0, #0x2 +# CHECK: movn w0, #0x2, lsl #16 +# CHECK: movn x0, #0x2, lsl #16 + +0x20 0x00 0x80 0x72 +0x20 0x00 0x80 0xf2 +0x20 0x00 0xa0 0x72 +0x20 0x00 0xa0 0xf2 + +# CHECK: movk w0, #0x1 +# CHECK: movk x0, #0x1 +# CHECK: movk w0, #0x1, lsl #16 +# CHECK: movk x0, #0x1, lsl #16 + +#==---------------------------------------------------------------------------== +# Conditionally set flags instructions +#==---------------------------------------------------------------------------== + + 0x1f 0x00 0x00 0x31 +# CHECK: cmn w0, #0 + 0x1f 0xfc 0x03 0xb1 +# CHECK: x0, #255 + + 0x23 0x08 0x42 0x3a +# CHECK: ccmn w1, #2, #3, eq + 0x23 0x08 0x42 0xba +# CHECK: ccmn x1, #2, #3, eq + 0x23 0x08 0x42 0x7a +# CHECK: ccmp w1, #2, #3, eq + 0x23 0x08 0x42 0xfa +# CHECK: ccmp x1, #2, #3, eq + + 0x23 0x00 0x42 0x3a +# CHECK: ccmn w1, w2, #3, eq + 0x23 0x00 0x42 0xba +# CHECK: ccmn x1, x2, #3, eq + 0x23 0x00 0x42 0x7a +# CHECK: ccmp w1, w2, #3, eq + 0x23 0x00 0x42 0xfa +# CHECK: ccmp x1, x2, #3, eq + +#==---------------------------------------------------------------------------== +# Conditional select instructions +#==---------------------------------------------------------------------------== + + 0x41 0x00 0x83 0x1a +# CHECK: csel w1, w2, w3, eq + 0x41 0x00 0x83 0x9a +# CHECK: csel x1, x2, x3, eq + 0x41 0x04 0x83 0x1a +# CHECK: csinc w1, w2, w3, eq + 0x41 0x04 0x83 0x9a +# CHECK: csinc x1, x2, x3, eq + 0x41 0x00 0x83 0x5a +# CHECK: csinv w1, w2, w3, eq + 0x41 0x00 0x83 0xda +# CHECK: csinv x1, x2, x3, eq + 0x41 0x04 0x83 0x5a +# CHECK: csneg w1, w2, w3, eq + 0x41 0x04 0x83 0xda +# CHECK: csneg x1, x2, x3, eq diff --git a/test/MC/Disassembler/AArch64/arm64-basic-a64-undefined.txt b/test/MC/Disassembler/AArch64/arm64-basic-a64-undefined.txt new file mode 100644 index 0000000..0e15af6 --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-basic-a64-undefined.txt @@ -0,0 +1,31 @@ +# These spawn another process so they're rather expensive. Not many. + +# LDR/STR: undefined if option field is 10x or 00x. +# RUN: echo "0x00 0x08 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x88 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s + +# Instructions notionally in the add/sub (extended register) sheet, but with +# invalid shift amount or "opt" field. +# RUN: echo "0x00 0x10 0xa0 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x10 0x60 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x14 0x20 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# MOVK with sf == 0 and hw<1> == 1 is unallocated. +# RUN: echo "0x00 0x00 0xc0 0x72" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'. +# RUN: echo "0x00 0x00 0xc0 0xeb" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x80 0x80 0x6b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# UBFM is undefined when s == 0 and imms<5> or immr<5> is 1. +# RUN: echo "0x00 0x80 0x00 0x53" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# EXT on vectors of i8 must have imm<3> = 0. +# RUN: echo "0x00 0x40 0x00 0x2e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# SCVTF on fixed point W-registers is undefined if scale<5> == 0. +# Same with FCVTZS and FCVTZU. +# RUN: echo "0x00 0x00 0x02 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x00 0x18 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/AArch64/arm64-bitfield.txt b/test/MC/Disassembler/AArch64/arm64-bitfield.txt new file mode 100644 index 0000000..d620cb3 --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-bitfield.txt @@ -0,0 +1,29 @@ +# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s + +#==---------------------------------------------------------------------------== +# 5.4.4 Bitfield Operations +#==---------------------------------------------------------------------------== + +0x41 0x3c 0x01 0x33 +0x41 0x3c 0x41 0xb3 +0x41 0x3c 0x01 0x13 +0x41 0x3c 0x41 0x93 +0x41 0x3c 0x01 0x53 +0x41 0x3c 0x41 0xd3 + +# CHECK: bfxil w1, w2, #1, #15 +# CHECK: bfxil x1, x2, #1, #15 +# CHECK: sbfx w1, w2, #1, #15 +# CHECK: sbfx x1, x2, #1, #15 +# CHECK: ubfx w1, w2, #1, #15 +# CHECK: ubfx x1, x2, #1, #15 + +#==---------------------------------------------------------------------------== +# 5.4.5 Extract (immediate) +#==---------------------------------------------------------------------------== + +0x41 0x3c 0x83 0x13 +0x62 0x04 0xc4 0x93 + +# CHECK: extr w1, w2, w3, #15 +# CHECK: extr x2, x3, x4, #1 diff --git a/test/MC/Disassembler/AArch64/arm64-branch.txt b/test/MC/Disassembler/AArch64/arm64-branch.txt new file mode 100644 index 0000000..6af1ad8 --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-branch.txt @@ -0,0 +1,75 @@ +# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s + +#----------------------------------------------------------------------------- +# Unconditional branch (register) instructions. +#----------------------------------------------------------------------------- + + 0xc0 0x03 0x5f 0xd6 +# CHECK: ret + 0x20 0x00 0x5f 0xd6 +# CHECK: ret x1 + 0xe0 0x03 0xbf 0xd6 +# CHECK: drps + 0xe0 0x03 0x9f 0xd6 +# CHECK: eret + 0xa0 0x00 0x1f 0xd6 +# CHECK: br x5 + 0x20 0x01 0x3f 0xd6 +# CHECK: blr x9 + 0x0B 0x00 0x18 0x37 +# CHECK: tbnz w11, #3, #0 + +#----------------------------------------------------------------------------- +# Exception generation instructions. +#----------------------------------------------------------------------------- + + 0x20 0x00 0x20 0xd4 +# CHECK: brk #0x1 + 0x41 0x00 0xa0 0xd4 +# CHECK: dcps1 #0x2 + 0x62 0x00 0xa0 0xd4 +# CHECK: dcps2 #0x3 + 0x83 0x00 0xa0 0xd4 +# CHECK: dcps3 #0x4 + 0xa0 0x00 0x40 0xd4 +# CHECK: hlt #0x5 + 0xc2 0x00 0x00 0xd4 +# CHECK: hvc #0x6 + 0xe3 0x00 0x00 0xd4 +# CHECK: smc #0x7 + 0x01 0x01 0x00 0xd4 +# CHECK: svc #0x8 + +#----------------------------------------------------------------------------- +# PC-relative branches (both positive and negative displacement) +#----------------------------------------------------------------------------- + + 0x07 0x00 0x00 0x14 +# CHECK: b #28 + 0x06 0x00 0x00 0x94 +# CHECK: bl #24 + 0xa1 0x00 0x00 0x54 +# CHECK: b.ne #20 + 0x80 0x00 0x08 0x36 +# CHECK: tbz w0, #1, #16 + 0xe1 0xff 0xf7 0x36 +# CHECK: tbz w1, #30, #-4 + 0x60 0x00 0x08 0x37 +# CHECK: tbnz w0, #1, #12 + 0x40 0x00 0x00 0xb4 +# CHECK: cbz x0, #8 + 0x20 0x00 0x00 0xb5 +# CHECK: cbnz x0, #4 + 0x1f 0x20 0x03 0xd5 +# CHECK: nop + 0xff 0xff 0xff 0x17 +# CHECK: b #-4 + 0xc1 0xff 0xff 0x54 +# CHECK: b.ne #-8 + 0xa0 0xff 0x0f 0x36 +# CHECK: tbz w0, #1, #-12 + 0x80 0xff 0xff 0xb4 +# CHECK: cbz x0, #-16 + 0x1f 0x20 0x03 0xd5 +# CHECK: nop + diff --git a/test/MC/Disassembler/AArch64/arm64-canonical-form.txt b/test/MC/Disassembler/AArch64/arm64-canonical-form.txt new file mode 100644 index 0000000..1c94b13 --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-canonical-form.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon --disassemble < %s | FileCheck %s + +0x00 0x08 0x00 0xc8 + +# CHECK: stxr w0, x0, [x0] + +0x00 0x00 0x40 0x9b + +# CHECK: smulh x0, x0, x0 + +0x08 0x20 0x21 0x1e + +# CHECK: fcmp s0, #0.0 + +0x1f 0x00 0x00 0x11 + +# CHECK: mov wsp, w0 + +0x00 0x7c 0x00 0x13 + +# CHECK: asr w0, w0, #0 diff --git a/test/MC/Disassembler/AArch64/arm64-crc32.txt b/test/MC/Disassembler/AArch64/arm64-crc32.txt new file mode 100644 index 0000000..51717ee --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-crc32.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc -triple=arm64 -mattr=+crc -disassemble < %s | FileCheck %s + +# CHECK: crc32b w5, w7, w20 +# CHECK: crc32h w28, wzr, w30 +# CHECK: crc32w w0, w1, w2 +# CHECK: crc32x w7, w9, x20 +# CHECK: crc32cb w9, w5, w4 +# CHECK: crc32ch w13, w17, w25 +# CHECK: crc32cw wzr, w3, w5 +# CHECK: crc32cx w18, w16, xzr +0xe5 0x40 0xd4 0x1a +0xfc 0x47 0xde 0x1a +0x20 0x48 0xc2 0x1a +0x27 0x4d 0xd4 0x9a +0xa9 0x50 0xc4 0x1a +0x2d 0x56 0xd9 0x1a +0x7f 0x58 0xc5 0x1a +0x12 0x5e 0xdf 0x9a diff --git a/test/MC/Disassembler/AArch64/arm64-crypto.txt b/test/MC/Disassembler/AArch64/arm64-crypto.txt new file mode 100644 index 0000000..b905b92 --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-crypto.txt @@ -0,0 +1,47 @@ +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 --disassemble < %s | FileCheck %s --check-prefix=CHECK-APPLE + + 0x20 0x48 0x28 0x4e + 0x20 0x58 0x28 0x4e + 0x20 0x68 0x28 0x4e + 0x20 0x78 0x28 0x4e + 0x20 0x00 0x02 0x5e + 0x20 0x10 0x02 0x5e + 0x20 0x20 0x02 0x5e + 0x20 0x30 0x02 0x5e + 0x20 0x40 0x02 0x5e + 0x20 0x50 0x02 0x5e + 0x20 0x60 0x02 0x5e + 0x20 0x08 0x28 0x5e + 0x20 0x18 0x28 0x5e + 0x20 0x28 0x28 0x5e + +# CHECK: aese v0.16b, v1.16b +# CHECK: aesd v0.16b, v1.16b +# CHECK: aesmc v0.16b, v1.16b +# CHECK: aesimc v0.16b, v1.16b +# CHECK: sha1c q0, s1, v2.4s +# CHECK: sha1p q0, s1, v2.4s +# CHECK: sha1m q0, s1, v2.4s +# CHECK: sha1su0 v0.4s, v1.4s, v2 +# CHECK: sha256h q0, q1, v2.4s +# CHECK: sha256h2 q0, q1, v2.4s +# CHECK: sha256su1 v0.4s, v1.4s, v2.4s +# CHECK: sha1h s0, s1 +# CHECK: sha1su1 v0.4s, v1.4s +# CHECK: sha256su0 v0.4s, v1.4s + +# CHECK-APPLE: aese.16b v0, v1 +# CHECK-APPLE: aesd.16b v0, v1 +# CHECK-APPLE: aesmc.16b v0, v1 +# CHECK-APPLE: aesimc.16b v0, v1 +# CHECK-APPLE: sha1c.4s q0, s1, v2 +# CHECK-APPLE: sha1p.4s q0, s1, v2 +# CHECK-APPLE: sha1m.4s q0, s1, v2 +# CHECK-APPLE: sha1su0.4s v0, v1, v2 +# CHECK-APPLE: sha256h.4s q0, q1, v2 +# CHECK-APPLE: sha256h2.4s q0, q1, v2 +# CHECK-APPLE: sha256su1.4s v0, v1, v2 +# CHECK-APPLE: sha1h s0, s1 +# CHECK-APPLE: sha1su1.4s v0, v1 +# CHECK-APPLE: sha256su0.4s v0, v1 diff --git a/test/MC/Disassembler/AArch64/arm64-invalid-logical.txt b/test/MC/Disassembler/AArch64/arm64-invalid-logical.txt new file mode 100644 index 0000000..8a4ecb6 --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-invalid-logical.txt @@ -0,0 +1,6 @@ +# RUN: llvm-mc -triple arm64-apple-darwin -disassemble < %s 2>&1 | FileCheck %s + +# rdar://15226511 +0x7b 0xbf 0x25 0x72 +# CHECK: invalid instruction encoding +# CHECK-NEXT: 0x7b 0xbf 0x25 0x72 diff --git a/test/MC/Disassembler/AArch64/arm64-logical.txt b/test/MC/Disassembler/AArch64/arm64-logical.txt new file mode 100644 index 0000000..e3cb3eb --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-logical.txt @@ -0,0 +1,223 @@ +# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s + +#==---------------------------------------------------------------------------== +# 5.4.2 Logical (immediate) +#==---------------------------------------------------------------------------== + +0x00 0x00 0x00 0x12 +0x00 0x00 0x40 0x92 +0x41 0x0c 0x00 0x12 +0x41 0x0c 0x40 0x92 +0xbf 0xec 0x7c 0x92 +0x00 0x00 0x00 0x72 +0x00 0x00 0x40 0xf2 +0x41 0x0c 0x00 0x72 +0x41 0x0c 0x40 0xf2 +0x5f 0x0c 0x40 0xf2 + +# CHECK: and w0, w0, #0x1 +# CHECK: and x0, x0, #0x1 +# CHECK: and w1, w2, #0xf +# CHECK: and x1, x2, #0xf +# CHECK: and sp, x5, #0xfffffffffffffff0 +# CHECK: ands w0, w0, #0x1 +# CHECK: ands x0, x0, #0x1 +# CHECK: ands w1, w2, #0xf +# CHECK: ands x1, x2, #0xf +# CHECK: tst x2, #0xf + +0x41 0x00 0x12 0x52 +0x41 0x00 0x71 0xd2 +0x5f 0x00 0x71 0xd2 + +# CHECK: eor w1, w2, #0x4000 +# CHECK: eor x1, x2, #0x8000 +# CHECK: eor sp, x2, #0x8000 + +0x41 0x00 0x12 0x32 +0x41 0x00 0x71 0xb2 +0x5f 0x00 0x71 0xb2 + +# CHECK: orr w1, w2, #0x4000 +# CHECK: orr x1, x2, #0x8000 +# CHECK: orr sp, x2, #0x8000 + +#==---------------------------------------------------------------------------== +# 5.5.3 Logical (shifted register) +#==---------------------------------------------------------------------------== + +0x41 0x00 0x03 0x0a +0x41 0x00 0x03 0x8a +0x41 0x08 0x03 0x0a +0x41 0x08 0x03 0x8a +0x41 0x08 0x43 0x0a +0x41 0x08 0x43 0x8a +0x41 0x08 0x83 0x0a +0x41 0x08 0x83 0x8a +0x41 0x08 0xc3 0x0a +0x41 0x08 0xc3 0x8a + +# CHECK: and w1, w2, w3 +# CHECK: and x1, x2, x3 +# CHECK: and w1, w2, w3, lsl #2 +# CHECK: and x1, x2, x3, lsl #2 +# CHECK: and w1, w2, w3, lsr #2 +# CHECK: and x1, x2, x3, lsr #2 +# CHECK: and w1, w2, w3, asr #2 +# CHECK: and x1, x2, x3, asr #2 +# CHECK: and w1, w2, w3, ror #2 +# CHECK: and x1, x2, x3, ror #2 + +0x41 0x00 0x03 0x6a +0x41 0x00 0x03 0xea +0x41 0x08 0x03 0x6a +0x41 0x08 0x03 0xea +0x41 0x08 0x43 0x6a +0x41 0x08 0x43 0xea +0x41 0x08 0x83 0x6a +0x41 0x08 0x83 0xea +0x41 0x08 0xc3 0x6a +0x41 0x08 0xc3 0xea + +# CHECK: ands w1, w2, w3 +# CHECK: ands x1, x2, x3 +# CHECK: ands w1, w2, w3, lsl #2 +# CHECK: ands x1, x2, x3, lsl #2 +# CHECK: ands w1, w2, w3, lsr #2 +# CHECK: ands x1, x2, x3, lsr #2 +# CHECK: ands w1, w2, w3, asr #2 +# CHECK: ands x1, x2, x3, asr #2 +# CHECK: ands w1, w2, w3, ror #2 +# CHECK: ands x1, x2, x3, ror #2 + +0x41 0x00 0x23 0x0a +0x41 0x00 0x23 0x8a +0x41 0x0c 0x23 0x0a +0x41 0x0c 0x23 0x8a +0x41 0x0c 0x63 0x0a +0x41 0x0c 0x63 0x8a +0x41 0x0c 0xa3 0x0a +0x41 0x0c 0xa3 0x8a +0x41 0x0c 0xe3 0x0a +0x41 0x0c 0xe3 0x8a + +# CHECK: bic w1, w2, w3 +# CHECK: bic x1, x2, x3 +# CHECK: bic w1, w2, w3, lsl #3 +# CHECK: bic x1, x2, x3, lsl #3 +# CHECK: bic w1, w2, w3, lsr #3 +# CHECK: bic x1, x2, x3, lsr #3 +# CHECK: bic w1, w2, w3, asr #3 +# CHECK: bic x1, x2, x3, asr #3 +# CHECK: bic w1, w2, w3, ror #3 +# CHECK: bic x1, x2, x3, ror #3 + +0x41 0x00 0x23 0x6a +0x41 0x00 0x23 0xea +0x41 0x0c 0x23 0x6a +0x41 0x0c 0x23 0xea +0x41 0x0c 0x63 0x6a +0x41 0x0c 0x63 0xea +0x41 0x0c 0xa3 0x6a +0x41 0x0c 0xa3 0xea +0x41 0x0c 0xe3 0x6a +0x41 0x0c 0xe3 0xea + +# CHECK: bics w1, w2, w3 +# CHECK: bics x1, x2, x3 +# CHECK: bics w1, w2, w3, lsl #3 +# CHECK: bics x1, x2, x3, lsl #3 +# CHECK: bics w1, w2, w3, lsr #3 +# CHECK: bics x1, x2, x3, lsr #3 +# CHECK: bics w1, w2, w3, asr #3 +# CHECK: bics x1, x2, x3, asr #3 +# CHECK: bics w1, w2, w3, ror #3 +# CHECK: bics x1, x2, x3, ror #3 + +0x41 0x00 0x23 0x4a +0x41 0x00 0x23 0xca +0x41 0x10 0x23 0x4a +0x41 0x10 0x23 0xca +0x41 0x10 0x63 0x4a +0x41 0x10 0x63 0xca +0x41 0x10 0xa3 0x4a +0x41 0x10 0xa3 0xca +0x41 0x10 0xe3 0x4a +0x41 0x10 0xe3 0xca + +# CHECK: eon w1, w2, w3 +# CHECK: eon x1, x2, x3 +# CHECK: eon w1, w2, w3, lsl #4 +# CHECK: eon x1, x2, x3, lsl #4 +# CHECK: eon w1, w2, w3, lsr #4 +# CHECK: eon x1, x2, x3, lsr #4 +# CHECK: eon w1, w2, w3, asr #4 +# CHECK: eon x1, x2, x3, asr #4 +# CHECK: eon w1, w2, w3, ror #4 +# CHECK: eon x1, x2, x3, ror #4 + +0x41 0x00 0x03 0x4a +0x41 0x00 0x03 0xca +0x41 0x14 0x03 0x4a +0x41 0x14 0x03 0xca +0x41 0x14 0x43 0x4a +0x41 0x14 0x43 0xca +0x41 0x14 0x83 0x4a +0x41 0x14 0x83 0xca +0x41 0x14 0xc3 0x4a +0x41 0x14 0xc3 0xca + +# CHECK: eor w1, w2, w3 +# CHECK: eor x1, x2, x3 +# CHECK: eor w1, w2, w3, lsl #5 +# CHECK: eor x1, x2, x3, lsl #5 +# CHECK: eor w1, w2, w3, lsr #5 +# CHECK: eor x1, x2, x3, lsr #5 +# CHECK: eor w1, w2, w3, asr #5 +# CHECK: eor x1, x2, x3, asr #5 +# CHECK: eor w1, w2, w3, ror #5 +# CHECK: eor x1, x2, x3, ror #5 + +0x41 0x00 0x03 0x2a +0x41 0x00 0x03 0xaa +0x41 0x18 0x03 0x2a +0x41 0x18 0x03 0xaa +0x41 0x18 0x43 0x2a +0x41 0x18 0x43 0xaa +0x41 0x18 0x83 0x2a +0x41 0x18 0x83 0xaa +0x41 0x18 0xc3 0x2a +0x41 0x18 0xc3 0xaa + +# CHECK: orr w1, w2, w3 +# CHECK: orr x1, x2, x3 +# CHECK: orr w1, w2, w3, lsl #6 +# CHECK: orr x1, x2, x3, lsl #6 +# CHECK: orr w1, w2, w3, lsr #6 +# CHECK: orr x1, x2, x3, lsr #6 +# CHECK: orr w1, w2, w3, asr #6 +# CHECK: orr x1, x2, x3, asr #6 +# CHECK: orr w1, w2, w3, ror #6 +# CHECK: orr x1, x2, x3, ror #6 + +0x41 0x00 0x23 0x2a +0x41 0x00 0x23 0xaa +0x41 0x1c 0x23 0x2a +0x41 0x1c 0x23 0xaa +0x41 0x1c 0x63 0x2a +0x41 0x1c 0x63 0xaa +0x41 0x1c 0xa3 0x2a +0x41 0x1c 0xa3 0xaa +0x41 0x1c 0xe3 0x2a +0x41 0x1c 0xe3 0xaa + +# CHECK: orn w1, w2, w3 +# CHECK: orn x1, x2, x3 +# CHECK: orn w1, w2, w3, lsl #7 +# CHECK: orn x1, x2, x3, lsl #7 +# CHECK: orn w1, w2, w3, lsr #7 +# CHECK: orn x1, x2, x3, lsr #7 +# CHECK: orn w1, w2, w3, asr #7 +# CHECK: orn x1, x2, x3, asr #7 +# CHECK: orn w1, w2, w3, ror #7 +# CHECK: orn x1, x2, x3, ror #7 diff --git a/test/MC/Disassembler/AArch64/arm64-memory.txt b/test/MC/Disassembler/AArch64/arm64-memory.txt new file mode 100644 index 0000000..54556a1 --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-memory.txt @@ -0,0 +1,564 @@ +# RUN: llvm-mc --disassemble -triple arm64-apple-darwin < %s | FileCheck %s + +#----------------------------------------------------------------------------- +# Indexed loads +#----------------------------------------------------------------------------- + + 0x85 0x14 0x40 0xb9 + 0x64 0x00 0x40 0xf9 + 0xe2 0x13 0x40 0xf9 + 0xe5 0x07 0x40 0x3d + 0xe6 0x07 0x40 0x7d + 0xe7 0x07 0x40 0xbd + 0xe8 0x07 0x40 0xfd + 0xe9 0x07 0xc0 0x3d + 0x64 0x00 0x40 0x39 + 0x20 0x78 0xa0 0xb8 + 0x85 0x50 0x40 0x39 + +# CHECK: ldr w5, [x4, #20] +# CHECK: ldr x4, [x3] +# CHECK: ldr x2, [sp, #32] +# CHECK: ldr b5, [sp, #1] +# CHECK: ldr h6, [sp, #2] +# CHECK: ldr s7, [sp, #4] +# CHECK: ldr d8, [sp, #8] +# CHECK: ldr q9, [sp, #16] +# CHECK: ldrb w4, [x3] +# CHECK: ldrsw x0, [x1, x0, lsl #2] +# CHECK: ldrb w5, [x4, #20] +# CHECK: ldrsb w9, [x3] +# CHECK: ldrsb x2, [sp, #128] +# CHECK: ldrh w2, [sp, #32] +# CHECK: ldrsh w3, [sp, #32] +# CHECK: ldrsh x5, [x9, #24] +# CHECK: ldrsw x9, [sp, #512] +# CHECK: prfm pldl3strm, [sp, #32] + + 0x69 0x00 0xc0 0x39 + 0xe2 0x03 0x82 0x39 + 0xe2 0x43 0x40 0x79 + 0xe3 0x43 0xc0 0x79 + 0x25 0x31 0x80 0x79 + 0xe9 0x03 0x82 0xb9 + 0xe5 0x13 0x80 0xf9 + 0x40 0x00 0x80 0xf9 + 0x41 0x00 0x80 0xf9 + 0x42 0x00 0x80 0xf9 + 0x43 0x00 0x80 0xf9 + 0x44 0x00 0x80 0xf9 + 0x45 0x00 0x80 0xf9 + 0x50 0x00 0x80 0xf9 + 0x51 0x00 0x80 0xf9 + 0x52 0x00 0x80 0xf9 + 0x53 0x00 0x80 0xf9 + 0x54 0x00 0x80 0xf9 + 0x55 0x00 0x80 0xf9 + +# CHECK: prfm pldl1keep, [x2] +# CHECK: prfm pldl1strm, [x2] +# CHECK: prfm pldl2keep, [x2] +# CHECK: prfm pldl2strm, [x2] +# CHECK: prfm pldl3keep, [x2] +# CHECK: prfm pldl3strm, [x2] +# CHECK: prfm pstl1keep, [x2] +# CHECK: prfm pstl1strm, [x2] +# CHECK: prfm pstl2keep, [x2] +# CHECK: prfm pstl2strm, [x2] +# CHECK: prfm pstl3keep, [x2] +# CHECK: prfm pstl3strm, [x2] + +#----------------------------------------------------------------------------- +# Indexed stores +#----------------------------------------------------------------------------- + + 0x64 0x00 0x00 0xf9 + 0xe2 0x13 0x00 0xf9 + 0x85 0x14 0x00 0xb9 + 0xe5 0x07 0x00 0x3d + 0xe6 0x07 0x00 0x7d + 0xe7 0x07 0x00 0xbd + 0xe8 0x07 0x00 0xfd + 0xe9 0x07 0x80 0x3d + 0x64 0x00 0x00 0x39 + 0x85 0x50 0x00 0x39 + 0xe2 0x43 0x00 0x79 + 0x00 0xe8 0x20 0x38 + 0x00 0x48 0x20 0x38 + +# CHECK: str x4, [x3] +# CHECK: str x2, [sp, #32] +# CHECK: str w5, [x4, #20] +# CHECK: str b5, [sp, #1] +# CHECK: str h6, [sp, #2] +# CHECK: str s7, [sp, #4] +# CHECK: str d8, [sp, #8] +# CHECK: str q9, [sp, #16] +# CHECK: strb w4, [x3] +# CHECK: strb w5, [x4, #20] +# CHECK: strh w2, [sp, #32] +# CHECK: strb w0, [x0, x0, sxtx] +# CHECK: strb w0, [x0, w0, uxtw] + +#----------------------------------------------------------------------------- +# Unscaled immediate loads and stores +#----------------------------------------------------------------------------- + + 0x62 0x00 0x40 0xb8 + 0xe2 0x83 0x41 0xb8 + 0x62 0x00 0x40 0xf8 + 0xe2 0x83 0x41 0xf8 + 0xe5 0x13 0x40 0x3c + 0xe6 0x23 0x40 0x7c + 0xe7 0x43 0x40 0xbc + 0xe8 0x83 0x40 0xfc + 0xe9 0x03 0xc1 0x3c + 0x69 0x00 0xc0 0x38 + 0xe2 0x03 0x88 0x38 + 0xe3 0x03 0xc2 0x78 + 0x25 0x81 0x81 0x78 + 0xe9 0x03 0x98 0xb8 + +# CHECK: ldur w2, [x3] +# CHECK: ldur w2, [sp, #24] +# CHECK: ldur x2, [x3] +# CHECK: ldur x2, [sp, #24] +# CHECK: ldur b5, [sp, #1] +# CHECK: ldur h6, [sp, #2] +# CHECK: ldur s7, [sp, #4] +# CHECK: ldur d8, [sp, #8] +# CHECK: ldur q9, [sp, #16] +# CHECK: ldursb w9, [x3] +# CHECK: ldursb x2, [sp, #128] +# CHECK: ldursh w3, [sp, #32] +# CHECK: ldursh x5, [x9, #24] +# CHECK: ldursw x9, [sp, #-128] + + 0x64 0x00 0x00 0xb8 + 0xe2 0x03 0x02 0xb8 + 0x64 0x00 0x00 0xf8 + 0xe2 0x03 0x02 0xf8 + 0x85 0x40 0x01 0xb8 + 0xe5 0x13 0x00 0x3c + 0xe6 0x23 0x00 0x7c + 0xe7 0x43 0x00 0xbc + 0xe8 0x83 0x00 0xfc + 0xe9 0x03 0x81 0x3c + 0x64 0x00 0x00 0x38 + 0x85 0x40 0x01 0x38 + 0xe2 0x03 0x02 0x78 + 0xe5 0x03 0x82 0xf8 + +# CHECK: stur w4, [x3] +# CHECK: stur w2, [sp, #32] +# CHECK: stur x4, [x3] +# CHECK: stur x2, [sp, #32] +# CHECK: stur w5, [x4, #20] +# CHECK: stur b5, [sp, #1] +# CHECK: stur h6, [sp, #2] +# CHECK: stur s7, [sp, #4] +# CHECK: stur d8, [sp, #8] +# CHECK: stur q9, [sp, #16] +# CHECK: sturb w4, [x3] +# CHECK: sturb w5, [x4, #20] +# CHECK: sturh w2, [sp, #32] +# CHECK: prfum pldl3strm, [sp, #32] + +#----------------------------------------------------------------------------- +# Unprivileged loads and stores +#----------------------------------------------------------------------------- + + 0x83 0x08 0x41 0xb8 + 0x83 0x08 0x41 0xf8 + 0x83 0x08 0x41 0x38 + 0x69 0x08 0xc0 0x38 + 0xe2 0x0b 0x88 0x38 + 0x83 0x08 0x41 0x78 + 0xe3 0x0b 0xc2 0x78 + 0x25 0x89 0x81 0x78 + 0xe9 0x0b 0x98 0xb8 + +# CHECK: ldtr w3, [x4, #16] +# CHECK: ldtr x3, [x4, #16] +# CHECK: ldtrb w3, [x4, #16] +# CHECK: ldtrsb w9, [x3] +# CHECK: ldtrsb x2, [sp, #128] +# CHECK: ldtrh w3, [x4, #16] +# CHECK: ldtrsh w3, [sp, #32] +# CHECK: ldtrsh x5, [x9, #24] +# CHECK: ldtrsw x9, [sp, #-128] + + 0x85 0x48 0x01 0xb8 + 0x64 0x08 0x00 0xf8 + 0xe2 0x0b 0x02 0xf8 + 0x64 0x08 0x00 0x38 + 0x85 0x48 0x01 0x38 + 0xe2 0x0b 0x02 0x78 + +# CHECK: sttr w5, [x4, #20] +# CHECK: sttr x4, [x3] +# CHECK: sttr x2, [sp, #32] +# CHECK: sttrb w4, [x3] +# CHECK: sttrb w5, [x4, #20] +# CHECK: sttrh w2, [sp, #32] + +#----------------------------------------------------------------------------- +# Pre-indexed loads and stores +#----------------------------------------------------------------------------- + + 0xfd 0x8c 0x40 0xf8 + 0xfe 0x8c 0x40 0xf8 + 0x05 0x1c 0x40 0x3c + 0x06 0x2c 0x40 0x7c + 0x07 0x4c 0x40 0xbc + 0x08 0x8c 0x40 0xfc + 0x09 0x0c 0xc1 0x3c + +# CHECK: ldr x29, [x7, #8]! +# CHECK: ldr x30, [x7, #8]! +# CHECK: ldr b5, [x0, #1]! +# CHECK: ldr h6, [x0, #2]! +# CHECK: ldr s7, [x0, #4]! +# CHECK: ldr d8, [x0, #8]! +# CHECK: ldr q9, [x0, #16]! + + 0xfe 0x8c 0x1f 0xf8 + 0xfd 0x8c 0x1f 0xf8 + 0x05 0xfc 0x1f 0x3c + 0x06 0xec 0x1f 0x7c + 0x07 0xcc 0x1f 0xbc + 0x08 0x8c 0x1f 0xfc + 0x09 0x0c 0x9f 0x3c + +# CHECK: str x30, [x7, #-8]! +# CHECK: str x29, [x7, #-8]! +# CHECK: str b5, [x0, #-1]! +# CHECK: str h6, [x0, #-2]! +# CHECK: str s7, [x0, #-4]! +# CHECK: str d8, [x0, #-8]! +# CHECK: str q9, [x0, #-16]! + +#----------------------------------------------------------------------------- +# post-indexed loads and stores +#----------------------------------------------------------------------------- + + 0xfe 0x84 0x1f 0xf8 + 0xfd 0x84 0x1f 0xf8 + 0x05 0xf4 0x1f 0x3c + 0x06 0xe4 0x1f 0x7c + 0x07 0xc4 0x1f 0xbc + 0x08 0x84 0x1f 0xfc + 0x09 0x04 0x9f 0x3c + +# CHECK: str x30, [x7], #-8 +# CHECK: str x29, [x7], #-8 +# CHECK: str b5, [x0], #-1 +# CHECK: str h6, [x0], #-2 +# CHECK: str s7, [x0], #-4 +# CHECK: str d8, [x0], #-8 +# CHECK: str q9, [x0], #-16 + + 0xfd 0x84 0x40 0xf8 + 0xfe 0x84 0x40 0xf8 + 0x05 0x14 0x40 0x3c + 0x06 0x24 0x40 0x7c + 0x07 0x44 0x40 0xbc + 0x08 0x84 0x40 0xfc + 0x09 0x04 0xc1 0x3c + +# CHECK: ldr x29, [x7], #8 +# CHECK: ldr x30, [x7], #8 +# CHECK: ldr b5, [x0], #1 +# CHECK: ldr h6, [x0], #2 +# CHECK: ldr s7, [x0], #4 +# CHECK: ldr d8, [x0], #8 +# CHECK: ldr q9, [x0], #16 + +#----------------------------------------------------------------------------- +# Load/Store pair (indexed offset) +#----------------------------------------------------------------------------- + + 0xe3 0x09 0x42 0x29 + 0xe4 0x27 0x7f 0xa9 + 0xc2 0x0d 0x42 0x69 + 0xe2 0x0f 0x7e 0x69 + 0x4a 0x04 0x48 0x2d + 0x4a 0x04 0x40 0x6d + +# CHECK: ldp w3, w2, [x15, #16] +# CHECK: ldp x4, x9, [sp, #-16] +# CHECK: ldpsw x2, x3, [x14, #16] +# CHECK: ldpsw x2, x3, [sp, #-16] +# CHECK: ldp s10, s1, [x2, #64] +# CHECK: ldp d10, d1, [x2] + + 0xe3 0x09 0x02 0x29 + 0xe4 0x27 0x3f 0xa9 + 0x4a 0x04 0x08 0x2d + 0x4a 0x04 0x00 0x6d + +# CHECK: stp w3, w2, [x15, #16] +# CHECK: stp x4, x9, [sp, #-16] +# CHECK: stp s10, s1, [x2, #64] +# CHECK: stp d10, d1, [x2] + +#----------------------------------------------------------------------------- +# Load/Store pair (pre-indexed) +#----------------------------------------------------------------------------- + + 0xe3 0x09 0xc2 0x29 + 0xe4 0x27 0xff 0xa9 + 0xc2 0x0d 0xc2 0x69 + 0xe2 0x0f 0xfe 0x69 + 0x4a 0x04 0xc8 0x2d + 0x4a 0x04 0xc1 0x6d + +# CHECK: ldp w3, w2, [x15, #16]! +# CHECK: ldp x4, x9, [sp, #-16]! +# CHECK: ldpsw x2, x3, [x14, #16]! +# CHECK: ldpsw x2, x3, [sp, #-16]! +# CHECK: ldp s10, s1, [x2, #64]! +# CHECK: ldp d10, d1, [x2, #16]! + + 0xe3 0x09 0x82 0x29 + 0xe4 0x27 0xbf 0xa9 + 0x4a 0x04 0x88 0x2d + 0x4a 0x04 0x81 0x6d + +# CHECK: stp w3, w2, [x15, #16]! +# CHECK: stp x4, x9, [sp, #-16]! +# CHECK: stp s10, s1, [x2, #64]! +# CHECK: stp d10, d1, [x2, #16]! + +#----------------------------------------------------------------------------- +# Load/Store pair (post-indexed) +#----------------------------------------------------------------------------- + + 0xe3 0x09 0xc2 0x28 + 0xe4 0x27 0xff 0xa8 + 0xc2 0x0d 0xc2 0x68 + 0xe2 0x0f 0xfe 0x68 + 0x4a 0x04 0xc8 0x2c + 0x4a 0x04 0xc1 0x6c + +# CHECK: ldp w3, w2, [x15], #16 +# CHECK: ldp x4, x9, [sp], #-16 +# CHECK: ldpsw x2, x3, [x14], #16 +# CHECK: ldpsw x2, x3, [sp], #-16 +# CHECK: ldp s10, s1, [x2], #64 +# CHECK: ldp d10, d1, [x2], #16 + + 0xe3 0x09 0x82 0x28 + 0xe4 0x27 0xbf 0xa8 + 0x4a 0x04 0x88 0x2c + 0x4a 0x04 0x81 0x6c + +# CHECK: stp w3, w2, [x15], #16 +# CHECK: stp x4, x9, [sp], #-16 +# CHECK: stp s10, s1, [x2], #64 +# CHECK: stp d10, d1, [x2], #16 + +#----------------------------------------------------------------------------- +# Load/Store pair (no-allocate) +#----------------------------------------------------------------------------- + + 0xe3 0x09 0x42 0x28 + 0xe4 0x27 0x7f 0xa8 + 0x4a 0x04 0x48 0x2c + 0x4a 0x04 0x40 0x6c + +# CHECK: ldnp w3, w2, [x15, #16] +# CHECK: ldnp x4, x9, [sp, #-16] +# CHECK: ldnp s10, s1, [x2, #64] +# CHECK: ldnp d10, d1, [x2] + + 0xe3 0x09 0x02 0x28 + 0xe4 0x27 0x3f 0xa8 + 0x4a 0x04 0x08 0x2c + 0x4a 0x04 0x00 0x6c + +# CHECK: stnp w3, w2, [x15, #16] +# CHECK: stnp x4, x9, [sp, #-16] +# CHECK: stnp s10, s1, [x2, #64] +# CHECK: stnp d10, d1, [x2] + +#----------------------------------------------------------------------------- +# Load/Store register offset +#----------------------------------------------------------------------------- + + 0x00 0x68 0x60 0xb8 + 0x00 0x78 0x60 0xb8 + 0x00 0x68 0x60 0xf8 + 0x00 0x78 0x60 0xf8 + 0x00 0xe8 0x60 0xf8 + +# CHECK: ldr w0, [x0, x0] +# CHECK: ldr w0, [x0, x0, lsl #2] +# CHECK: ldr x0, [x0, x0] +# CHECK: ldr x0, [x0, x0, lsl #3] +# CHECK: ldr x0, [x0, x0, sxtx] + + 0x21 0x68 0x62 0x3c + 0x21 0x78 0x62 0x3c + 0x21 0x68 0x62 0x7c + 0x21 0x78 0x62 0x7c + 0x21 0x68 0x62 0xbc + 0x21 0x78 0x62 0xbc + 0x21 0x68 0x62 0xfc + 0x21 0x78 0x62 0xfc + 0x21 0x68 0xe2 0x3c + 0x21 0x78 0xe2 0x3c + +# CHECK: ldr b1, [x1, x2] +# CHECK: ldr b1, [x1, x2, lsl #0] +# CHECK: ldr h1, [x1, x2] +# CHECK: ldr h1, [x1, x2, lsl #1] +# CHECK: ldr s1, [x1, x2] +# CHECK: ldr s1, [x1, x2, lsl #2] +# CHECK: ldr d1, [x1, x2] +# CHECK: ldr d1, [x1, x2, lsl #3] +# CHECK: ldr q1, [x1, x2] +# CHECK: ldr q1, [x1, x2, lsl #4] + + 0x00 0x48 0x20 0x7c + 0xe1 0x6b 0x23 0xfc + 0xe1 0x5b 0x23 0xfc + 0xe1 0x6b 0xa3 0x3c + 0xe1 0x5b 0xa3 0x3c + +# CHECK: str h0, [x0, w0, uxtw] +# CHECK: str d1, [sp, x3] +# CHECK: str d1, [sp, w3, uxtw #3] +# CHECK: str q1, [sp, x3] +# CHECK: str q1, [sp, w3, uxtw #4] + +#----------------------------------------------------------------------------- +# Load/Store exclusive +#----------------------------------------------------------------------------- + + 0x26 0x7c 0x5f 0x08 + 0x26 0x7c 0x5f 0x48 + 0x27 0x0d 0x7f 0x88 + 0x27 0x0d 0x7f 0xc8 + +# CHECK: ldxrb w6, [x1] +# CHECK: ldxrh w6, [x1] +# CHECK: ldxp w7, w3, [x9] +# CHECK: ldxp x7, x3, [x9] + + 0x64 0x7c 0x01 0xc8 + 0x64 0x7c 0x01 0x88 + 0x64 0x7c 0x01 0x08 + 0x64 0x7c 0x01 0x48 + 0x22 0x18 0x21 0xc8 + 0x22 0x18 0x21 0x88 + +# CHECK: stxr w1, x4, [x3] +# CHECK: stxr w1, w4, [x3] +# CHECK: stxrb w1, w4, [x3] +# CHECK: stxrh w1, w4, [x3] +# CHECK: stxp w1, x2, x6, [x1] +# CHECK: stxp w1, w2, w6, [x1] + +#----------------------------------------------------------------------------- +# Load-acquire/Store-release non-exclusive +#----------------------------------------------------------------------------- + + 0xe4 0xff 0xdf 0x88 + 0xe4 0xff 0xdf 0xc8 + 0xe4 0xff 0xdf 0x08 + 0xe4 0xff 0xdf 0x48 + +# CHECK: ldar w4, [sp] +# CHECK: ldar x4, [sp] +# CHECK: ldarb w4, [sp] +# CHECK: ldarh w4, [sp] + + 0xc3 0xfc 0x9f 0x88 + 0xc3 0xfc 0x9f 0xc8 + 0xc3 0xfc 0x9f 0x08 + 0xc3 0xfc 0x9f 0x48 + +# CHECK: stlr w3, [x6] +# CHECK: stlr x3, [x6] +# CHECK: stlrb w3, [x6] +# CHECK: stlrh w3, [x6] + +#----------------------------------------------------------------------------- +# Load-acquire/Store-release exclusive +#----------------------------------------------------------------------------- + + 0x82 0xfc 0x5f 0x88 + 0x82 0xfc 0x5f 0xc8 + 0x82 0xfc 0x5f 0x08 + 0x82 0xfc 0x5f 0x48 + 0x22 0x98 0x7f 0x88 + 0x22 0x98 0x7f 0xc8 + +# CHECK: ldaxr w2, [x4] +# CHECK: ldaxr x2, [x4] +# CHECK: ldaxrb w2, [x4] +# CHECK: ldaxrh w2, [x4] +# CHECK: ldaxp w2, w6, [x1] +# CHECK: ldaxp x2, x6, [x1] + + 0x27 0xfc 0x08 0xc8 + 0x27 0xfc 0x08 0x88 + 0x27 0xfc 0x08 0x08 + 0x27 0xfc 0x08 0x48 + 0x22 0x98 0x21 0xc8 + 0x22 0x98 0x21 0x88 + +# CHECK: stlxr w8, x7, [x1] +# CHECK: stlxr w8, w7, [x1] +# CHECK: stlxrb w8, w7, [x1] +# CHECK: stlxrh w8, w7, [x1] +# CHECK: stlxp w1, x2, x6, [x1] +# CHECK: stlxp w1, w2, w6, [x1] + +#----------------------------------------------------------------------------- +# Load/Store with explicit LSL values +#----------------------------------------------------------------------------- + 0x20 0x78 0xa0 0xb8 + 0x20 0x78 0x60 0xf8 + 0x20 0x78 0x20 0xf8 + 0x20 0x78 0x60 0xb8 + 0x20 0x78 0x20 0xb8 + 0x20 0x78 0xe0 0x3c + 0x20 0x78 0xa0 0x3c + 0x20 0x78 0x60 0xfc + 0x20 0x78 0x20 0xfc + 0x20 0x78 0x60 0xbc + 0x20 0x78 0x20 0xbc + 0x20 0x78 0x60 0x7c + 0x20 0x78 0x60 0x3c + 0x20 0x78 0x60 0x38 + 0x20 0x78 0x20 0x38 + 0x20 0x78 0xe0 0x38 + 0x20 0x78 0x60 0x78 + 0x20 0x78 0x20 0x78 + 0x20 0x78 0xe0 0x78 + 0x20 0x78 0xa0 0x38 + 0x20 0x78 0xa0 0x78 + +# CHECK: ldrsw x0, [x1, x0, lsl #2] +# CHECK: ldr x0, [x1, x0, lsl #3] +# CHECK: str x0, [x1, x0, lsl #3] +# CHECK: ldr w0, [x1, x0, lsl #2] +# CHECK: str w0, [x1, x0, lsl #2] +# CHECK: ldr q0, [x1, x0, lsl #4] +# CHECK: str q0, [x1, x0, lsl #4] +# CHECK: ldr d0, [x1, x0, lsl #3] +# CHECK: str d0, [x1, x0, lsl #3] +# CHECK: ldr s0, [x1, x0, lsl #2] +# CHECK: str s0, [x1, x0, lsl #2] +# CHECK: ldr h0, [x1, x0, lsl #1] +# CHECK: ldr b0, [x1, x0, lsl #0] +# CHECK: ldrb w0, [x1, x0, lsl #0] +# CHECK: strb w0, [x1, x0, lsl #0] +# CHECK: ldrsb w0, [x1, x0, lsl #0] +# CHECK: ldrh w0, [x1, x0, lsl #1] +# CHECK: strh w0, [x1, x0, lsl #1] +# CHECK: ldrsh w0, [x1, x0, lsl #1] +# CHECK: ldrsb x0, [x1, x0, lsl #0] +# CHECK: ldrsh x0, [x1, x0, lsl #1] diff --git a/test/MC/Disassembler/AArch64/arm64-non-apple-fmov.txt b/test/MC/Disassembler/AArch64/arm64-non-apple-fmov.txt new file mode 100644 index 0000000..75cb95c --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-non-apple-fmov.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc -triple arm64 -mattr=neon -disassemble < %s | FileCheck %s + +0x00 0x00 0xae 0x9e +0x00 0x00 0xaf 0x9e + +# CHECK: fmov x0, v0.d[1] +# CHECK: fmov v0.d[1], x0 diff --git a/test/MC/Disassembler/AArch64/arm64-scalar-fp.txt b/test/MC/Disassembler/AArch64/arm64-scalar-fp.txt new file mode 100644 index 0000000..f139700 --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-scalar-fp.txt @@ -0,0 +1,255 @@ +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon --disassemble -output-asm-variant=1 < %s | FileCheck %s + +#----------------------------------------------------------------------------- +# Floating-point arithmetic +#----------------------------------------------------------------------------- + +0x41 0xc0 0x20 0x1e +0x41 0xc0 0x60 0x1e + +# CHECK: fabs s1, s2 +# CHECK: fabs d1, d2 + +0x41 0x28 0x23 0x1e +0x41 0x28 0x63 0x1e + +# CHECK: fadd s1, s2, s3 +# CHECK: fadd d1, d2, d3 + +0x41 0x18 0x23 0x1e +0x41 0x18 0x63 0x1e + +# CHECK: fdiv s1, s2, s3 +# CHECK: fdiv d1, d2, d3 + +0x41 0x10 0x03 0x1f +0x41 0x10 0x43 0x1f + +# CHECK: fmadd s1, s2, s3, s4 +# CHECK: fmadd d1, d2, d3, d4 + +0x41 0x48 0x23 0x1e +0x41 0x48 0x63 0x1e +0x41 0x68 0x23 0x1e +0x41 0x68 0x63 0x1e + +# CHECK: fmax s1, s2, s3 +# CHECK: fmax d1, d2, d3 +# CHECK: fmaxnm s1, s2, s3 +# CHECK: fmaxnm d1, d2, d3 + +0x41 0x58 0x23 0x1e +0x41 0x58 0x63 0x1e +0x41 0x78 0x23 0x1e +0x41 0x78 0x63 0x1e + +# CHECK: fmin s1, s2, s3 +# CHECK: fmin d1, d2, d3 +# CHECK: fminnm s1, s2, s3 +# CHECK: fminnm d1, d2, d3 + +0x41 0x90 0x03 0x1f +0x41 0x90 0x43 0x1f + +# CHECK: fmsub s1, s2, s3, s4 +# CHECK: fmsub d1, d2, d3, d4 + +0x41 0x08 0x23 0x1e +0x41 0x08 0x63 0x1e + +# CHECK: fmul s1, s2, s3 +# CHECK: fmul d1, d2, d3 + +0x41 0x40 0x21 0x1e +0x41 0x40 0x61 0x1e + +# CHECK: fneg s1, s2 +# CHECK: fneg d1, d2 + +0x41 0x10 0x23 0x1f +0x41 0x10 0x63 0x1f + +# CHECK: fnmadd s1, s2, s3, s4 +# CHECK: fnmadd d1, d2, d3, d4 + +0x41 0x90 0x23 0x1f +0x41 0x90 0x63 0x1f + +# CHECK: fnmsub s1, s2, s3, s4 +# CHECK: fnmsub d1, d2, d3, d4 + +0x41 0x88 0x23 0x1e +0x41 0x88 0x63 0x1e + +# CHECK: fnmul s1, s2, s3 +# CHECK: fnmul d1, d2, d3 + +0x41 0xc0 0x21 0x1e +0x41 0xc0 0x61 0x1e + +# CHECK: fsqrt s1, s2 +# CHECK: fsqrt d1, d2 + +0x41 0x38 0x23 0x1e +0x41 0x38 0x63 0x1e + +# CHECK: fsub s1, s2, s3 +# CHECK: fsub d1, d2, d3 + +#----------------------------------------------------------------------------- +# Floating-point comparison +#----------------------------------------------------------------------------- + +0x20 0x04 0x22 0x1e +0x20 0x04 0x62 0x1e +0x30 0x04 0x22 0x1e +0x30 0x04 0x62 0x1e + +# CHECK: fccmp s1, s2, #0, eq +# CHECK: fccmp d1, d2, #0, eq +# CHECK: fccmpe s1, s2, #0, eq +# CHECK: fccmpe d1, d2, #0, eq + +0x20 0x20 0x22 0x1e +0x20 0x20 0x62 0x1e +0x28 0x20 0x20 0x1e +0x28 0x20 0x60 0x1e +0x30 0x20 0x22 0x1e +0x30 0x20 0x62 0x1e +0x38 0x20 0x20 0x1e +0x38 0x20 0x60 0x1e + +# CHECK: fcmp s1, s2 +# CHECK: fcmp d1, d2 +# CHECK: fcmp s1, #0.0 +# CHECK: fcmp d1, #0.0 +# CHECK: fcmpe s1, s2 +# CHECK: fcmpe d1, d2 +# CHECK: fcmpe s1, #0.0 +# CHECK: fcmpe d1, #0.0 + +#----------------------------------------------------------------------------- +# Floating-point conditional select +#----------------------------------------------------------------------------- + +0x41 0x0c 0x23 0x1e +0x41 0x0c 0x63 0x1e + +# CHECK: fcsel s1, s2, s3, eq +# CHECK: fcsel d1, d2, d3, eq + +#----------------------------------------------------------------------------- +# Floating-point convert +#----------------------------------------------------------------------------- + +0x41 0xc0 0x63 0x1e +0x41 0x40 0x62 0x1e +0x41 0xc0 0xe2 0x1e +0x41 0x40 0xe2 0x1e +0x41 0xc0 0x22 0x1e +0x41 0xc0 0x23 0x1e + +# CHECK: fcvt h1, d2 +# CHECK: fcvt s1, d2 +# CHECK: fcvt d1, h2 +# CHECK: fcvt s1, h2 +# CHECK: fcvt d1, s2 +# CHECK: fcvt h1, s2 + +0x41 0x00 0x44 0x1e +0x41 0x04 0x44 0x1e +0x41 0x00 0x44 0x9e +0x41 0x04 0x44 0x9e +0x41 0x00 0x04 0x1e +0x41 0x04 0x04 0x1e +0x41 0x00 0x04 0x9e +0x41 0x04 0x04 0x9e + +#----------------------------------------------------------------------------- +# Floating-point move +#----------------------------------------------------------------------------- + +0x41 0x00 0x27 0x1e +0x41 0x00 0x26 0x1e +0x41 0x00 0x67 0x9e +0x41 0x00 0x66 0x9e + +# CHECK: fmov s1, w2 +# CHECK: fmov w1, s2 +# CHECK: fmov d1, x2 +# CHECK: fmov x1, d2 + +0x01 0x10 0x28 0x1e +0x01 0x10 0x68 0x1e +0x01 0xf0 0x7b 0x1e +0x01 0xf0 0x6b 0x1e + +# CHECK: fmov s1, #0.12500000 +# CHECK: fmov d1, #0.12500000 +# CHECK: fmov d1, #-0.48437500 +# CHECK: fmov d1, #0.48437500 + +0x41 0x40 0x20 0x1e +0x41 0x40 0x60 0x1e + +# CHECK: fmov s1, s2 +# CHECK: fmov d1, d2 + +#----------------------------------------------------------------------------- +# Floating-point round to integral +#----------------------------------------------------------------------------- + +0x41 0x40 0x26 0x1e +0x41 0x40 0x66 0x1e + +# CHECK: frinta s1, s2 +# CHECK: frinta d1, d2 + +0x41 0xc0 0x27 0x1e +0x41 0xc0 0x67 0x1e + +# CHECK: frinti s1, s2 +# CHECK: frinti d1, d2 + +0x41 0x40 0x25 0x1e +0x41 0x40 0x65 0x1e + +# CHECK: frintm s1, s2 +# CHECK: frintm d1, d2 + +0x41 0x40 0x24 0x1e +0x41 0x40 0x64 0x1e + +# CHECK: frintn s1, s2 +# CHECK: frintn d1, d2 + +0x41 0xc0 0x24 0x1e +0x41 0xc0 0x64 0x1e + +# CHECK: frintp s1, s2 +# CHECK: frintp d1, d2 + +0x41 0x40 0x27 0x1e +0x41 0x40 0x67 0x1e + +# CHECK: frintx s1, s2 +# CHECK: frintx d1, d2 + +0x41 0xc0 0x25 0x1e +0x41 0xc0 0x65 0x1e + +# CHECK: frintz s1, s2 +# CHECK: frintz d1, d2 + + 0x00 0x3c 0xe0 0x7e + 0x00 0x8c 0xe0 0x5e + +# CHECK: cmhs d0, d0, d0 +# CHECK: cmtst d0, d0, d0 + +0x00 0x00 0xaf 0x9e +0x00 0x00 0xae 0x9e + +# CHECK: fmov.d v0[1], x0 +# CHECK: fmov.d x0, v0[1] + diff --git a/test/MC/Disassembler/AArch64/arm64-system.txt b/test/MC/Disassembler/AArch64/arm64-system.txt new file mode 100644 index 0000000..9027a60 --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-system.txt @@ -0,0 +1,62 @@ +# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s + + +#----------------------------------------------------------------------------- +# Hint encodings +#----------------------------------------------------------------------------- + + 0x1f 0x20 0x03 0xd5 +# CHECK: nop + 0x9f 0x20 0x03 0xd5 +# CHECK: sev + 0xbf 0x20 0x03 0xd5 +# CHECK: sevl + 0x5f 0x20 0x03 0xd5 +# CHECK: wfe + 0x7f 0x20 0x03 0xd5 +# CHECK: wfi + 0x3f 0x20 0x03 0xd5 +# CHECK: yield + +#----------------------------------------------------------------------------- +# Single-immediate operand instructions +#----------------------------------------------------------------------------- + + 0x5f 0x3a 0x03 0xd5 +# CHECK: clrex #10 + 0xdf 0x3f 0x03 0xd5 +# CHECK: isb{{$}} + 0xdf 0x31 0x03 0xd5 +# CHECK: isb #1 + 0xbf 0x33 0x03 0xd5 +# CHECK: dmb osh + 0x9f 0x37 0x03 0xd5 +# CHECK: dsb nsh + 0x3f 0x76 0x08 0xd5 +# CHECK: dc ivac + +#----------------------------------------------------------------------------- +# Generic system instructions +#----------------------------------------------------------------------------- + 0xff 0x05 0x0a 0xd5 + 0xe7 0x6a 0x0f 0xd5 + 0xf4 0x3f 0x2e 0xd5 + 0xbf 0x40 0x00 0xd5 + 0x00 0xb0 0x18 0xd5 + 0x00 0xb0 0x38 0xd5 + +# CHECK: sys #2, c0, c5, #7 +# CHECK: sys #7, c6, c10, #7, x7 +# CHECK: sysl x20, #6, c3, c15, #7 +# CHECK: msr SPSEL, #0 +# CHECK: msr S3_0_C11_C0_0, x0 +# CHECK: mrs x0, S3_0_C11_C0_0 + + 0x40 0xc0 0x1e 0xd5 + 0x40 0xc0 0x1c 0xd5 + 0x40 0xc0 0x18 0xd5 + +# CHECK: msr RMR_EL3, x0 +# CHECK: msr RMR_EL2, x0 +# CHECK: msr RMR_EL1, x0 + diff --git a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt index 40926b1..397a39e 100644 --- a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # Add/sub (immediate) @@ -187,7 +188,7 @@ # CHECK: sub w3, w5, w7 # CHECK: sub wzr, w3, w5 -# CHECK: sub w20, wzr, w4 +# CHECK: {{sub w20, wzr, w4|neg w20, w4}} # CHECK: sub w4, w6, wzr # CHECK: sub w11, w13, w15 # CHECK: sub w9, w3, wzr, lsl #10 @@ -214,7 +215,7 @@ # CHECK: sub x3, x5, x7 # CHECK: sub xzr, x3, x5 -# CHECK: sub x20, xzr, x4 +# CHECK: {{sub x20, xzr, x4|neg x20, x4}} # CHECK: sub x4, x6, xzr # CHECK: sub x11, x13, x15 # CHECK: sub x9, x3, xzr, lsl #10 @@ -241,7 +242,7 @@ # CHECK: subs w3, w5, w7 # CHECK: cmp w3, w5 -# CHECK: subs w20, wzr, w4 +# CHECK: {{subs w20, wzr, w4|negs w20, w4}} # CHECK: subs w4, w6, wzr # CHECK: subs w11, w13, w15 # CHECK: subs w9, w3, wzr, lsl #10 @@ -268,7 +269,7 @@ # CHECK: subs x3, x5, x7 # CHECK: cmp x3, x5 -# CHECK: subs x20, xzr, x4 +# CHECK: {{subs x20, xzr, x4|negs x20, x4}} # CHECK: subs x4, x6, xzr # CHECK: subs x11, x13, x15 # CHECK: subs x9, x3, xzr, lsl #10 @@ -393,18 +394,18 @@ 0x9f 0xde 0x95 0xeb 0xdf 0xfe 0x97 0xeb -# CHECK: sub w29, wzr, w30 -# CHECK: sub w30, wzr, wzr -# CHECK: sub wzr, wzr, w0 -# CHECK: sub w28, wzr, w27 -# CHECK: sub w26, wzr, w25, lsl #29 -# CHECK: sub w24, wzr, w23, lsl #31 -# CHECK: sub w22, wzr, w21, lsr #0 -# CHECK: sub w20, wzr, w19, lsr #1 -# CHECK: sub w18, wzr, w17, lsr #31 -# CHECK: sub w16, wzr, w15, asr #0 -# CHECK: sub w14, wzr, w13, asr #12 -# CHECK: sub w12, wzr, w11, asr #31 +# CHECK: {{sub w29, wzr|neg w29}}, w30 +# CHECK: {{sub w30, wzr|neg w30}}, wzr +# CHECK: {{sub wzr, wzr|neg wzr}}, w0 +# CHECK: {{sub w28, wzr|neg w28}}, w27 +# CHECK: {{sub w26, wzr|neg w26}}, w25, lsl #29 +# CHECK: {{sub w24, wzr|neg w24}}, w23, lsl #31 +# CHECK: {{sub w22, wzr|neg w22}}, w21, lsr #0 +# CHECK: {{sub w20, wzr|neg w20}}, w19, lsr #1 +# CHECK: {{sub w18, wzr|neg w18}}, w17, lsr #31 +# CHECK: {{sub w16, wzr|neg w16}}, w15, asr #0 +# CHECK: {{sub w14, wzr|neg w14}}, w13, asr #12 +# CHECK: {{sub w12, wzr|neg w12}}, w11, asr #31 0xfd 0x3 0x1e 0x4b 0xfe 0x3 0x1f 0x4b 0xff 0x3 0x0 0x4b @@ -418,18 +419,18 @@ 0xee 0x33 0x8d 0x4b 0xec 0x7f 0x8b 0x4b -# CHECK: sub x29, xzr, x30 -# CHECK: sub x30, xzr, xzr -# CHECK: sub xzr, xzr, x0 -# CHECK: sub x28, xzr, x27 -# CHECK: sub x26, xzr, x25, lsl #29 -# CHECK: sub x24, xzr, x23, lsl #31 -# CHECK: sub x22, xzr, x21, lsr #0 -# CHECK: sub x20, xzr, x19, lsr #1 -# CHECK: sub x18, xzr, x17, lsr #31 -# CHECK: sub x16, xzr, x15, asr #0 -# CHECK: sub x14, xzr, x13, asr #12 -# CHECK: sub x12, xzr, x11, asr #31 +# CHECK: {{sub x29, xzr|neg x29}}, x30 +# CHECK: {{sub x30, xzr|neg x30}}, xzr +# CHECK: {{sub xzr, xzr|neg xzr}}, x0 +# CHECK: {{sub x28, xzr|neg x28}}, x27 +# CHECK: {{sub x26, xzr|neg x26}}, x25, lsl #29 +# CHECK: {{sub x24, xzr|neg x24}}, x23, lsl #31 +# CHECK: {{sub x22, xzr|neg x22}}, x21, lsr #0 +# CHECK: {{sub x20, xzr|neg x20}}, x19, lsr #1 +# CHECK: {{sub x18, xzr|neg x18}}, x17, lsr #31 +# CHECK: {{sub x16, xzr|neg x16}}, x15, asr #0 +# CHECK: {{sub x14, xzr|neg x14}}, x13, asr #12 +# CHECK: {{sub x12, xzr|neg x12}}, x11, asr #31 0xfd 0x3 0x1e 0xcb 0xfe 0x3 0x1f 0xcb 0xff 0x3 0x0 0xcb @@ -443,18 +444,18 @@ 0xee 0x33 0x8d 0xcb 0xec 0x7f 0x8b 0xcb -# CHECK: subs w29, wzr, w30 -# CHECK: subs w30, wzr, wzr +# CHECK: {{subs w29, wzr|negs w29}}, w30 +# CHECK: {{subs w30, wzr|negs w30}}, wzr # CHECK: cmp wzr, w0 -# CHECK: subs w28, wzr, w27 -# CHECK: subs w26, wzr, w25, lsl #29 -# CHECK: subs w24, wzr, w23, lsl #31 -# CHECK: subs w22, wzr, w21, lsr #0 -# CHECK: subs w20, wzr, w19, lsr #1 -# CHECK: subs w18, wzr, w17, lsr #31 -# CHECK: subs w16, wzr, w15, asr #0 -# CHECK: subs w14, wzr, w13, asr #12 -# CHECK: subs w12, wzr, w11, asr #31 +# CHECK: {{subs w28, wzr|negs w28}}, w27 +# CHECK: {{subs w26, wzr|negs w26}}, w25, lsl #29 +# CHECK: {{subs w24, wzr|negs w24}}, w23, lsl #31 +# CHECK: {{subs w22, wzr|negs w22}}, w21, lsr #0 +# CHECK: {{subs w20, wzr|negs w20}}, w19, lsr #1 +# CHECK: {{subs w18, wzr|negs w18}}, w17, lsr #31 +# CHECK: {{subs w16, wzr|negs w16}}, w15, asr #0 +# CHECK: {{subs w14, wzr|negs w14}}, w13, asr #12 +# CHECK: {{subs w12, wzr|negs w12}}, w11, asr #31 0xfd 0x3 0x1e 0x6b 0xfe 0x3 0x1f 0x6b 0xff 0x3 0x0 0x6b @@ -468,18 +469,18 @@ 0xee 0x33 0x8d 0x6b 0xec 0x7f 0x8b 0x6b -# CHECK: subs x29, xzr, x30 -# CHECK: subs x30, xzr, xzr +# CHECK: {{subs x29, xzr|negs x29}}, x30 +# CHECK: {{subs x30, xzr|negs x30}}, xzr # CHECK: cmp xzr, x0 -# CHECK: subs x28, xzr, x27 -# CHECK: subs x26, xzr, x25, lsl #29 -# CHECK: subs x24, xzr, x23, lsl #31 -# CHECK: subs x22, xzr, x21, lsr #0 -# CHECK: subs x20, xzr, x19, lsr #1 -# CHECK: subs x18, xzr, x17, lsr #31 -# CHECK: subs x16, xzr, x15, asr #0 -# CHECK: subs x14, xzr, x13, asr #12 -# CHECK: subs x12, xzr, x11, asr #31 +# CHECK: {{subs x28, xzr|negs x28}}, x27 +# CHECK: {{subs x26, xzr|negs x26}}, x25, lsl #29 +# CHECK: {{subs x24, xzr|negs x24}}, x23, lsl #31 +# CHECK: {{subs x22, xzr|negs x22}}, x21, lsr #0 +# CHECK: {{subs x20, xzr|negs x20}}, x19, lsr #1 +# CHECK: {{subs x18, xzr|negs x18}}, x17, lsr #31 +# CHECK: {{subs x16, xzr|negs x16}}, x15, asr #0 +# CHECK: {{subs x14, xzr|negs x14}}, x13, asr #12 +# CHECK: {{subs x12, xzr|negs x12}}, x11, asr #31 0xfd 0x3 0x1e 0xeb 0xfe 0x3 0x1f 0xeb 0xff 0x3 0x0 0xeb @@ -940,21 +941,21 @@ 0xe5 0x27 0x86 0xda 0x7 0x35 0x9f 0xda -# CHECK: csinc w3, wzr, wzr, ne -# CHECK: csinc x9, xzr, xzr, mi -# CHECK: csinv w20, wzr, wzr, eq -# CHECK: csinv x30, xzr, xzr, lt +# CHECK: cset w3, eq +# CHECK: cset x9, pl +# CHECK: csetm w20, ne +# CHECK: csetm x30, ge 0xe3 0x17 0x9f 0x1a 0xe9 0x47 0x9f 0x9a 0xf4 0x3 0x9f 0x5a 0xfe 0xb3 0x9f 0xda -# CHECK: csinc w3, w5, w5, le -# CHECK: csinc wzr, w4, w4, gt -# CHECK: csinc w9, wzr, wzr, ge -# CHECK: csinc x3, x5, x5, le -# CHECK: csinc xzr, x4, x4, gt -# CHECK: csinc x9, xzr, xzr, ge +# CHECK: cinc w3, w5, gt +# CHECK: cinc wzr, w4, le +# CHECK: cset w9, lt +# CHECK: cinc x3, x5, gt +# CHECK: cinc xzr, x4, le +# CHECK: cset x9, lt 0xa3 0xd4 0x85 0x1a 0x9f 0xc4 0x84 0x1a 0xe9 0xa7 0x9f 0x1a @@ -962,12 +963,12 @@ 0x9f 0xc4 0x84 0x9a 0xe9 0xa7 0x9f 0x9a -# CHECK: csinv w3, w5, w5, le -# CHECK: csinv wzr, w4, w4, gt -# CHECK: csinv w9, wzr, wzr, ge -# CHECK: csinv x3, x5, x5, le -# CHECK: csinv xzr, x4, x4, gt -# CHECK: csinv x9, xzr, xzr, ge +# CHECK: cinv w3, w5, gt +# CHECK: cinv wzr, w4, le +# CHECK: csetm w9, lt +# CHECK: cinv x3, x5, gt +# CHECK: cinv xzr, x4, le +# CHECK: csetm x9, lt 0xa3 0xd0 0x85 0x5a 0x9f 0xc0 0x84 0x5a 0xe9 0xa3 0x9f 0x5a @@ -975,12 +976,12 @@ 0x9f 0xc0 0x84 0xda 0xe9 0xa3 0x9f 0xda -# CHECK: csneg w3, w5, w5, le -# CHECK: csneg wzr, w4, w4, gt -# CHECK: csneg w9, wzr, wzr, ge -# CHECK: csneg x3, x5, x5, le -# CHECK: csneg xzr, x4, x4, gt -# CHECK: csneg x9, xzr, xzr, ge +# CHECK: cneg w3, w5, gt +# CHECK: cneg wzr, w4, le +# CHECK: cneg w9, wzr, lt +# CHECK: cneg x3, x5, gt +# CHECK: cneg xzr, x4, le +# CHECK: cneg x9, xzr, lt 0xa3 0xd4 0x85 0x5a 0x9f 0xc4 0x84 0x5a 0xe9 0xa7 0x9f 0x5a @@ -1243,22 +1244,22 @@ #------------------------------------------------------------------------------ # CHECK: svc #0 -# CHECK: svc #65535 +# CHECK: svc #{{65535|0xffff}} 0x1 0x0 0x0 0xd4 0xe1 0xff 0x1f 0xd4 -# CHECK: hvc #1 -# CHECK: smc #12000 -# CHECK: brk #12 -# CHECK: hlt #123 +# CHECK: hvc #{{1|0x1}} +# CHECK: smc #{{12000|0x2ee0}} +# CHECK: brk #{{12|0xc}} +# CHECK: hlt #{{123|0x7b}} 0x22 0x0 0x0 0xd4 0x3 0xdc 0x5 0xd4 0x80 0x1 0x20 0xd4 0x60 0xf 0x40 0xd4 -# CHECK: dcps1 #42 -# CHECK: dcps2 #9 -# CHECK: dcps3 #1000 +# CHECK: dcps1 #{{42|0x2a}} +# CHECK: dcps2 #{{9|0x9}} +# CHECK: dcps3 #{{1000|0x3e8}} 0x41 0x5 0xa0 0xd4 0x22 0x1 0xa0 0xd4 0x3 0x7d 0xa0 0xd4 @@ -1284,9 +1285,9 @@ 0xa3 0x3c 0xc7 0x93 0xab 0xfd 0xd1 0x93 -# CHECK: extr x19, x23, x23, #24 -# CHECK: extr x29, xzr, xzr, #63 -# CHECK: extr w9, w13, w13, #31 +# CHECK: ror x19, x23, #24 +# CHECK: ror x29, xzr, #63 +# CHECK: ror w9, w13, #31 0xf3 0x62 0xd7 0x93 0xfd 0xff 0xdf 0x93 0xa9 0x7d 0x8d 0x13 @@ -2353,23 +2354,23 @@ 0xec 0xff 0xbf 0x3d # CHECK: prfm pldl1keep, [sp, #8] -# CHECK: prfm pldl1strm, [x3, #0] +# CHECK: prfm pldl1strm, [x3{{(, #0)?}}] # CHECK: prfm pldl2keep, [x5, #16] -# CHECK: prfm pldl2strm, [x2, #0] -# CHECK: prfm pldl3keep, [x5, #0] -# CHECK: prfm pldl3strm, [x6, #0] +# CHECK: prfm pldl2strm, [x2{{(, #0)?}}] +# CHECK: prfm pldl3keep, [x5{{(, #0)?}}] +# CHECK: prfm pldl3strm, [x6{{(, #0)?}}] # CHECK: prfm plil1keep, [sp, #8] -# CHECK: prfm plil1strm, [x3, #0] +# CHECK: prfm plil1strm, [x3{{(, #0)?}}] # CHECK: prfm plil2keep, [x5, #16] -# CHECK: prfm plil2strm, [x2, #0] -# CHECK: prfm plil3keep, [x5, #0] -# CHECK: prfm plil3strm, [x6, #0] +# CHECK: prfm plil2strm, [x2{{(, #0)?}}] +# CHECK: prfm plil3keep, [x5{{(, #0)?}}] +# CHECK: prfm plil3strm, [x6{{(, #0)?}}] # CHECK: prfm pstl1keep, [sp, #8] -# CHECK: prfm pstl1strm, [x3, #0] +# CHECK: prfm pstl1strm, [x3{{(, #0)?}}] # CHECK: prfm pstl2keep, [x5, #16] -# CHECK: prfm pstl2strm, [x2, #0] -# CHECK: prfm pstl3keep, [x5, #0] -# CHECK: prfm pstl3strm, [x6, #0] +# CHECK: prfm pstl2strm, [x2{{(, #0)?}}] +# CHECK: prfm pstl3keep, [x5{{(, #0)?}}] +# CHECK: prfm pstl3strm, [x6{{(, #0)?}}] 0xe0 0x07 0x80 0xf9 0x61 0x00 0x80 0xf9 0xa2 0x08 0x80 0xf9 @@ -2722,15 +2723,15 @@ 0xff 0xc7 0x0 0x52 0x30 0xc6 0x1 0x52 -# CHECK: ands wzr, w18, #0xcccccccc +# CHECK: {{ands wzr,|tst}} w18, #0xcccccccc # CHECK: ands w19, w20, #0x33333333 # CHECK: ands w21, w22, #0x99999999 0x5f 0xe6 0x2 0x72 0x93 0xe6 0x0 0x72 0xd5 0xe6 0x1 0x72 -# CHECK: ands wzr, w3, #0xaaaaaaaa -# CHECK: ands wzr, wzr, #0x55555555 +# CHECK: {{ands wzr,|tst}} w3, #0xaaaaaaaa +# CHECK: {{ands wzr,|tst}} wzr, #0x55555555 0x7f 0xf0 0x1 0x72 0xff 0xf3 0x0 0x72 @@ -2762,15 +2763,15 @@ 0xff 0xc7 0x0 0xd2 0x30 0xc6 0x1 0xd2 -# CHECK: ands xzr, x18, #0xcccccccccccccccc +# CHECK: {{ands xzr,|tst}} x18, #0xcccccccccccccccc # CHECK: ands x19, x20, #0x3333333333333333 # CHECK: ands x21, x22, #0x9999999999999999 0x5f 0xe6 0x2 0xf2 0x93 0xe6 0x0 0xf2 0xd5 0xe6 0x1 0xf2 -# CHECK: ands xzr, x3, #0xaaaaaaaaaaaaaaaa -# CHECK: ands xzr, xzr, #0x5555555555555555 +# CHECK: {{ands xzr,|tst}} x3, #0xaaaaaaaaaaaaaaaa +# CHECK: {{ands xzr,|tst}} xzr, #0x5555555555555555 0x7f 0xf0 0x1 0xf2 0xff 0xf3 0x0 0xf2 @@ -2858,15 +2859,15 @@ # limitation in InstAlias. Lots of the "mov[nz]" instructions should # be "mov". -# CHECK: movz w1, #65535 +# CHECK: movz w1, #{{65535|0xffff}} # CHECK: movz w2, #0, lsl #16 -# CHECK: movn w2, #1234 +# CHECK: movn w2, #{{1234|0x4d2}} 0xe1 0xff 0x9f 0x52 0x2 0x0 0xa0 0x52 0x42 0x9a 0x80 0x12 -# CHECK: movz x2, #1234, lsl #32 -# CHECK: movk xzr, #4321, lsl #48 +# CHECK: movz x2, #{{1234|0x4d2}}, lsl #32 +# CHECK: movk xzr, #{{4321|0x10e1}}, lsl #48 0x42 0x9a 0xc0 0xd2 0x3f 0x1c 0xe2 0xf2 @@ -2906,7 +2907,7 @@ #------------------------------------------------------------------------------ # CHECK: nop -# CHECK: hint #127 +# CHECK: hint #{{127|0x7f}} # CHECK: nop # CHECK: yield # CHECK: wfe @@ -2998,9 +2999,9 @@ 0xdf 0x3f 0x3 0xd5 0xdf 0x3c 0x3 0xd5 -# CHECK: msr spsel, #0 -# CHECK: msr daifset, #15 -# CHECK: msr daifclr, #12 +# CHECK: msr {{spsel|SPSEL}}, #0 +# CHECK: msr {{daifset|DAIFSET}}, #15 +# CHECK: msr {{daifclr|DAIFCLR}}, #12 0xbf 0x40 0x0 0xd5 0xdf 0x4f 0x3 0xd5 0xff 0x4c 0x3 0xd5 @@ -3014,21 +3015,21 @@ 0xe9 0x59 0x2f 0xd5 0x41 0xff 0x28 0xd5 -# CHECK: sys #0, c7, c1, #0, xzr -# CHECK: sys #0, c7, c5, #0, xzr -# CHECK: sys #3, c7, c5, #1, x9 +# CHECK: {{sys #0, c7, c1, #0|ic ialluis}} +# CHECK: {{sys #0, c7, c5, #0|ic iallu}} +# CHECK: {{sys #3, c7, c5, #1|ic ivau}}, x9 0x1f 0x71 0x8 0xd5 0x1f 0x75 0x8 0xd5 0x29 0x75 0xb 0xd5 -# CHECK: sys #3, c7, c4, #1, x12 -# CHECK: sys #0, c7, c6, #1, xzr -# CHECK: sys #0, c7, c6, #2, x2 -# CHECK: sys #3, c7, c10, #1, x9 -# CHECK: sys #0, c7, c10, #2, x10 -# CHECK: sys #3, c7, c11, #1, x0 -# CHECK: sys #3, c7, c14, #1, x3 -# CHECK: sys #0, c7, c14, #2, x30 +# CHECK: {{sys #3, c7, c4, #1|dc zva}}, x12 +# CHECK: {{sys #0, c7, c6, #1|dc ivac}} +# CHECK: {{sys #0, c7, c6, #2|dc isw}}, x2 +# CHECK: {{sys #3, c7, c10, #1|dc cvac}}, x9 +# CHECK: {{sys #0, c7, c10, #2|dc csw}}, x10 +# CHECK: {{sys #3, c7, c11, #1|dc cvau}}, x0 +# CHECK: {{sys #3, c7, c14, #1|dc civac}}, x3 +# CHECK: {{sys #0, c7, c14, #2|dc cisw}}, x30 0x2c 0x74 0xb 0xd5 0x3f 0x76 0x8 0xd5 0x42 0x76 0x8 0xd5 @@ -3039,559 +3040,559 @@ 0x5e 0x7e 0x8 0xd5 -# CHECK: msr teecr32_el1, x12 -# CHECK: msr osdtrrx_el1, x12 -# CHECK: msr mdccint_el1, x12 -# CHECK: msr mdscr_el1, x12 -# CHECK: msr osdtrtx_el1, x12 -# CHECK: msr dbgdtr_el0, x12 -# CHECK: msr dbgdtrtx_el0, x12 -# CHECK: msr oseccr_el1, x12 -# CHECK: msr dbgvcr32_el2, x12 -# CHECK: msr dbgbvr0_el1, x12 -# CHECK: msr dbgbvr1_el1, x12 -# CHECK: msr dbgbvr2_el1, x12 -# CHECK: msr dbgbvr3_el1, x12 -# CHECK: msr dbgbvr4_el1, x12 -# CHECK: msr dbgbvr5_el1, x12 -# CHECK: msr dbgbvr6_el1, x12 -# CHECK: msr dbgbvr7_el1, x12 -# CHECK: msr dbgbvr8_el1, x12 -# CHECK: msr dbgbvr9_el1, x12 -# CHECK: msr dbgbvr10_el1, x12 -# CHECK: msr dbgbvr11_el1, x12 -# CHECK: msr dbgbvr12_el1, x12 -# CHECK: msr dbgbvr13_el1, x12 -# CHECK: msr dbgbvr14_el1, x12 -# CHECK: msr dbgbvr15_el1, x12 -# CHECK: msr dbgbcr0_el1, x12 -# CHECK: msr dbgbcr1_el1, x12 -# CHECK: msr dbgbcr2_el1, x12 -# CHECK: msr dbgbcr3_el1, x12 -# CHECK: msr dbgbcr4_el1, x12 -# CHECK: msr dbgbcr5_el1, x12 -# CHECK: msr dbgbcr6_el1, x12 -# CHECK: msr dbgbcr7_el1, x12 -# CHECK: msr dbgbcr8_el1, x12 -# CHECK: msr dbgbcr9_el1, x12 -# CHECK: msr dbgbcr10_el1, x12 -# CHECK: msr dbgbcr11_el1, x12 -# CHECK: msr dbgbcr12_el1, x12 -# CHECK: msr dbgbcr13_el1, x12 -# CHECK: msr dbgbcr14_el1, x12 -# CHECK: msr dbgbcr15_el1, x12 -# CHECK: msr dbgwvr0_el1, x12 -# CHECK: msr dbgwvr1_el1, x12 -# CHECK: msr dbgwvr2_el1, x12 -# CHECK: msr dbgwvr3_el1, x12 -# CHECK: msr dbgwvr4_el1, x12 -# CHECK: msr dbgwvr5_el1, x12 -# CHECK: msr dbgwvr6_el1, x12 -# CHECK: msr dbgwvr7_el1, x12 -# CHECK: msr dbgwvr8_el1, x12 -# CHECK: msr dbgwvr9_el1, x12 -# CHECK: msr dbgwvr10_el1, x12 -# CHECK: msr dbgwvr11_el1, x12 -# CHECK: msr dbgwvr12_el1, x12 -# CHECK: msr dbgwvr13_el1, x12 -# CHECK: msr dbgwvr14_el1, x12 -# CHECK: msr dbgwvr15_el1, x12 -# CHECK: msr dbgwcr0_el1, x12 -# CHECK: msr dbgwcr1_el1, x12 -# CHECK: msr dbgwcr2_el1, x12 -# CHECK: msr dbgwcr3_el1, x12 -# CHECK: msr dbgwcr4_el1, x12 -# CHECK: msr dbgwcr5_el1, x12 -# CHECK: msr dbgwcr6_el1, x12 -# CHECK: msr dbgwcr7_el1, x12 -# CHECK: msr dbgwcr8_el1, x12 -# CHECK: msr dbgwcr9_el1, x12 -# CHECK: msr dbgwcr10_el1, x12 -# CHECK: msr dbgwcr11_el1, x12 -# CHECK: msr dbgwcr12_el1, x12 -# CHECK: msr dbgwcr13_el1, x12 -# CHECK: msr dbgwcr14_el1, x12 -# CHECK: msr dbgwcr15_el1, x12 -# CHECK: msr teehbr32_el1, x12 -# CHECK: msr oslar_el1, x12 -# CHECK: msr osdlr_el1, x12 -# CHECK: msr dbgprcr_el1, x12 -# CHECK: msr dbgclaimset_el1, x12 -# CHECK: msr dbgclaimclr_el1, x12 -# CHECK: msr csselr_el1, x12 -# CHECK: msr vpidr_el2, x12 -# CHECK: msr vmpidr_el2, x12 -# CHECK: msr sctlr_el1, x12 -# CHECK: msr sctlr_el2, x12 -# CHECK: msr sctlr_el3, x12 -# CHECK: msr actlr_el1, x12 -# CHECK: msr actlr_el2, x12 -# CHECK: msr actlr_el3, x12 -# CHECK: msr cpacr_el1, x12 -# CHECK: msr hcr_el2, x12 -# CHECK: msr scr_el3, x12 -# CHECK: msr mdcr_el2, x12 -# CHECK: msr sder32_el3, x12 -# CHECK: msr cptr_el2, x12 -# CHECK: msr cptr_el3, x12 -# CHECK: msr hstr_el2, x12 -# CHECK: msr hacr_el2, x12 -# CHECK: msr mdcr_el3, x12 -# CHECK: msr ttbr0_el1, x12 -# CHECK: msr ttbr0_el2, x12 -# CHECK: msr ttbr0_el3, x12 -# CHECK: msr ttbr1_el1, x12 -# CHECK: msr tcr_el1, x12 -# CHECK: msr tcr_el2, x12 -# CHECK: msr tcr_el3, x12 -# CHECK: msr vttbr_el2, x12 -# CHECK: msr vtcr_el2, x12 -# CHECK: msr dacr32_el2, x12 -# CHECK: msr spsr_el1, x12 -# CHECK: msr spsr_el2, x12 -# CHECK: msr spsr_el3, x12 -# CHECK: msr elr_el1, x12 -# CHECK: msr elr_el2, x12 -# CHECK: msr elr_el3, x12 -# CHECK: msr sp_el0, x12 -# CHECK: msr sp_el1, x12 -# CHECK: msr sp_el2, x12 -# CHECK: msr spsel, x12 -# CHECK: msr nzcv, x12 -# CHECK: msr daif, x12 -# CHECK: msr currentel, x12 -# CHECK: msr spsr_irq, x12 -# CHECK: msr spsr_abt, x12 -# CHECK: msr spsr_und, x12 -# CHECK: msr spsr_fiq, x12 -# CHECK: msr fpcr, x12 -# CHECK: msr fpsr, x12 -# CHECK: msr dspsr_el0, x12 -# CHECK: msr dlr_el0, x12 -# CHECK: msr ifsr32_el2, x12 -# CHECK: msr afsr0_el1, x12 -# CHECK: msr afsr0_el2, x12 -# CHECK: msr afsr0_el3, x12 -# CHECK: msr afsr1_el1, x12 -# CHECK: msr afsr1_el2, x12 -# CHECK: msr afsr1_el3, x12 -# CHECK: msr esr_el1, x12 -# CHECK: msr esr_el2, x12 -# CHECK: msr esr_el3, x12 -# CHECK: msr fpexc32_el2, x12 -# CHECK: msr far_el1, x12 -# CHECK: msr far_el2, x12 -# CHECK: msr far_el3, x12 -# CHECK: msr hpfar_el2, x12 -# CHECK: msr par_el1, x12 -# CHECK: msr pmcr_el0, x12 -# CHECK: msr pmcntenset_el0, x12 -# CHECK: msr pmcntenclr_el0, x12 -# CHECK: msr pmovsclr_el0, x12 -# CHECK: msr pmselr_el0, x12 -# CHECK: msr pmccntr_el0, x12 -# CHECK: msr pmxevtyper_el0, x12 -# CHECK: msr pmxevcntr_el0, x12 -# CHECK: msr pmuserenr_el0, x12 -# CHECK: msr pmintenset_el1, x12 -# CHECK: msr pmintenclr_el1, x12 -# CHECK: msr pmovsset_el0, x12 -# CHECK: msr mair_el1, x12 -# CHECK: msr mair_el2, x12 -# CHECK: msr mair_el3, x12 -# CHECK: msr amair_el1, x12 -# CHECK: msr amair_el2, x12 -# CHECK: msr amair_el3, x12 -# CHECK: msr vbar_el1, x12 -# CHECK: msr vbar_el2, x12 -# CHECK: msr vbar_el3, x12 -# CHECK: msr rmr_el1, x12 -# CHECK: msr rmr_el2, x12 -# CHECK: msr rmr_el3, x12 -# CHECK: msr tpidr_el0, x12 -# CHECK: msr tpidr_el2, x12 -# CHECK: msr tpidr_el3, x12 -# CHECK: msr tpidrro_el0, x12 -# CHECK: msr tpidr_el1, x12 -# CHECK: msr cntfrq_el0, x12 -# CHECK: msr cntvoff_el2, x12 -# CHECK: msr cntkctl_el1, x12 -# CHECK: msr cnthctl_el2, x12 -# CHECK: msr cntp_tval_el0, x12 -# CHECK: msr cnthp_tval_el2, x12 -# CHECK: msr cntps_tval_el1, x12 -# CHECK: msr cntp_ctl_el0, x12 -# CHECK: msr cnthp_ctl_el2, x12 -# CHECK: msr cntps_ctl_el1, x12 -# CHECK: msr cntp_cval_el0, x12 -# CHECK: msr cnthp_cval_el2, x12 -# CHECK: msr cntps_cval_el1, x12 -# CHECK: msr cntv_tval_el0, x12 -# CHECK: msr cntv_ctl_el0, x12 -# CHECK: msr cntv_cval_el0, x12 -# CHECK: msr pmevcntr0_el0, x12 -# CHECK: msr pmevcntr1_el0, x12 -# CHECK: msr pmevcntr2_el0, x12 -# CHECK: msr pmevcntr3_el0, x12 -# CHECK: msr pmevcntr4_el0, x12 -# CHECK: msr pmevcntr5_el0, x12 -# CHECK: msr pmevcntr6_el0, x12 -# CHECK: msr pmevcntr7_el0, x12 -# CHECK: msr pmevcntr8_el0, x12 -# CHECK: msr pmevcntr9_el0, x12 -# CHECK: msr pmevcntr10_el0, x12 -# CHECK: msr pmevcntr11_el0, x12 -# CHECK: msr pmevcntr12_el0, x12 -# CHECK: msr pmevcntr13_el0, x12 -# CHECK: msr pmevcntr14_el0, x12 -# CHECK: msr pmevcntr15_el0, x12 -# CHECK: msr pmevcntr16_el0, x12 -# CHECK: msr pmevcntr17_el0, x12 -# CHECK: msr pmevcntr18_el0, x12 -# CHECK: msr pmevcntr19_el0, x12 -# CHECK: msr pmevcntr20_el0, x12 -# CHECK: msr pmevcntr21_el0, x12 -# CHECK: msr pmevcntr22_el0, x12 -# CHECK: msr pmevcntr23_el0, x12 -# CHECK: msr pmevcntr24_el0, x12 -# CHECK: msr pmevcntr25_el0, x12 -# CHECK: msr pmevcntr26_el0, x12 -# CHECK: msr pmevcntr27_el0, x12 -# CHECK: msr pmevcntr28_el0, x12 -# CHECK: msr pmevcntr29_el0, x12 -# CHECK: msr pmevcntr30_el0, x12 -# CHECK: msr pmccfiltr_el0, x12 -# CHECK: msr pmevtyper0_el0, x12 -# CHECK: msr pmevtyper1_el0, x12 -# CHECK: msr pmevtyper2_el0, x12 -# CHECK: msr pmevtyper3_el0, x12 -# CHECK: msr pmevtyper4_el0, x12 -# CHECK: msr pmevtyper5_el0, x12 -# CHECK: msr pmevtyper6_el0, x12 -# CHECK: msr pmevtyper7_el0, x12 -# CHECK: msr pmevtyper8_el0, x12 -# CHECK: msr pmevtyper9_el0, x12 -# CHECK: msr pmevtyper10_el0, x12 -# CHECK: msr pmevtyper11_el0, x12 -# CHECK: msr pmevtyper12_el0, x12 -# CHECK: msr pmevtyper13_el0, x12 -# CHECK: msr pmevtyper14_el0, x12 -# CHECK: msr pmevtyper15_el0, x12 -# CHECK: msr pmevtyper16_el0, x12 -# CHECK: msr pmevtyper17_el0, x12 -# CHECK: msr pmevtyper18_el0, x12 -# CHECK: msr pmevtyper19_el0, x12 -# CHECK: msr pmevtyper20_el0, x12 -# CHECK: msr pmevtyper21_el0, x12 -# CHECK: msr pmevtyper22_el0, x12 -# CHECK: msr pmevtyper23_el0, x12 -# CHECK: msr pmevtyper24_el0, x12 -# CHECK: msr pmevtyper25_el0, x12 -# CHECK: msr pmevtyper26_el0, x12 -# CHECK: msr pmevtyper27_el0, x12 -# CHECK: msr pmevtyper28_el0, x12 -# CHECK: msr pmevtyper29_el0, x12 -# CHECK: msr pmevtyper30_el0, x12 -# CHECK: mrs x9, teecr32_el1 -# CHECK: mrs x9, osdtrrx_el1 -# CHECK: mrs x9, mdccsr_el0 -# CHECK: mrs x9, mdccint_el1 -# CHECK: mrs x9, mdscr_el1 -# CHECK: mrs x9, osdtrtx_el1 -# CHECK: mrs x9, dbgdtr_el0 -# CHECK: mrs x9, dbgdtrrx_el0 -# CHECK: mrs x9, oseccr_el1 -# CHECK: mrs x9, dbgvcr32_el2 -# CHECK: mrs x9, dbgbvr0_el1 -# CHECK: mrs x9, dbgbvr1_el1 -# CHECK: mrs x9, dbgbvr2_el1 -# CHECK: mrs x9, dbgbvr3_el1 -# CHECK: mrs x9, dbgbvr4_el1 -# CHECK: mrs x9, dbgbvr5_el1 -# CHECK: mrs x9, dbgbvr6_el1 -# CHECK: mrs x9, dbgbvr7_el1 -# CHECK: mrs x9, dbgbvr8_el1 -# CHECK: mrs x9, dbgbvr9_el1 -# CHECK: mrs x9, dbgbvr10_el1 -# CHECK: mrs x9, dbgbvr11_el1 -# CHECK: mrs x9, dbgbvr12_el1 -# CHECK: mrs x9, dbgbvr13_el1 -# CHECK: mrs x9, dbgbvr14_el1 -# CHECK: mrs x9, dbgbvr15_el1 -# CHECK: mrs x9, dbgbcr0_el1 -# CHECK: mrs x9, dbgbcr1_el1 -# CHECK: mrs x9, dbgbcr2_el1 -# CHECK: mrs x9, dbgbcr3_el1 -# CHECK: mrs x9, dbgbcr4_el1 -# CHECK: mrs x9, dbgbcr5_el1 -# CHECK: mrs x9, dbgbcr6_el1 -# CHECK: mrs x9, dbgbcr7_el1 -# CHECK: mrs x9, dbgbcr8_el1 -# CHECK: mrs x9, dbgbcr9_el1 -# CHECK: mrs x9, dbgbcr10_el1 -# CHECK: mrs x9, dbgbcr11_el1 -# CHECK: mrs x9, dbgbcr12_el1 -# CHECK: mrs x9, dbgbcr13_el1 -# CHECK: mrs x9, dbgbcr14_el1 -# CHECK: mrs x9, dbgbcr15_el1 -# CHECK: mrs x9, dbgwvr0_el1 -# CHECK: mrs x9, dbgwvr1_el1 -# CHECK: mrs x9, dbgwvr2_el1 -# CHECK: mrs x9, dbgwvr3_el1 -# CHECK: mrs x9, dbgwvr4_el1 -# CHECK: mrs x9, dbgwvr5_el1 -# CHECK: mrs x9, dbgwvr6_el1 -# CHECK: mrs x9, dbgwvr7_el1 -# CHECK: mrs x9, dbgwvr8_el1 -# CHECK: mrs x9, dbgwvr9_el1 -# CHECK: mrs x9, dbgwvr10_el1 -# CHECK: mrs x9, dbgwvr11_el1 -# CHECK: mrs x9, dbgwvr12_el1 -# CHECK: mrs x9, dbgwvr13_el1 -# CHECK: mrs x9, dbgwvr14_el1 -# CHECK: mrs x9, dbgwvr15_el1 -# CHECK: mrs x9, dbgwcr0_el1 -# CHECK: mrs x9, dbgwcr1_el1 -# CHECK: mrs x9, dbgwcr2_el1 -# CHECK: mrs x9, dbgwcr3_el1 -# CHECK: mrs x9, dbgwcr4_el1 -# CHECK: mrs x9, dbgwcr5_el1 -# CHECK: mrs x9, dbgwcr6_el1 -# CHECK: mrs x9, dbgwcr7_el1 -# CHECK: mrs x9, dbgwcr8_el1 -# CHECK: mrs x9, dbgwcr9_el1 -# CHECK: mrs x9, dbgwcr10_el1 -# CHECK: mrs x9, dbgwcr11_el1 -# CHECK: mrs x9, dbgwcr12_el1 -# CHECK: mrs x9, dbgwcr13_el1 -# CHECK: mrs x9, dbgwcr14_el1 -# CHECK: mrs x9, dbgwcr15_el1 -# CHECK: mrs x9, mdrar_el1 -# CHECK: mrs x9, teehbr32_el1 -# CHECK: mrs x9, oslsr_el1 -# CHECK: mrs x9, osdlr_el1 -# CHECK: mrs x9, dbgprcr_el1 -# CHECK: mrs x9, dbgclaimset_el1 -# CHECK: mrs x9, dbgclaimclr_el1 -# CHECK: mrs x9, dbgauthstatus_el1 -# CHECK: mrs x9, midr_el1 -# CHECK: mrs x9, ccsidr_el1 -# CHECK: mrs x9, csselr_el1 -# CHECK: mrs x9, vpidr_el2 -# CHECK: mrs x9, clidr_el1 -# CHECK: mrs x9, ctr_el0 -# CHECK: mrs x9, mpidr_el1 -# CHECK: mrs x9, vmpidr_el2 -# CHECK: mrs x9, revidr_el1 -# CHECK: mrs x9, aidr_el1 -# CHECK: mrs x9, dczid_el0 -# CHECK: mrs x9, id_pfr0_el1 -# CHECK: mrs x9, id_pfr1_el1 -# CHECK: mrs x9, id_dfr0_el1 -# CHECK: mrs x9, id_afr0_el1 -# CHECK: mrs x9, id_mmfr0_el1 -# CHECK: mrs x9, id_mmfr1_el1 -# CHECK: mrs x9, id_mmfr2_el1 -# CHECK: mrs x9, id_mmfr3_el1 -# CHECK: mrs x9, id_isar0_el1 -# CHECK: mrs x9, id_isar1_el1 -# CHECK: mrs x9, id_isar2_el1 -# CHECK: mrs x9, id_isar3_el1 -# CHECK: mrs x9, id_isar4_el1 -# CHECK: mrs x9, id_isar5_el1 -# CHECK: mrs x9, mvfr0_el1 -# CHECK: mrs x9, mvfr1_el1 -# CHECK: mrs x9, mvfr2_el1 -# CHECK: mrs x9, id_aa64pfr0_el1 -# CHECK: mrs x9, id_aa64pfr1_el1 -# CHECK: mrs x9, id_aa64dfr0_el1 -# CHECK: mrs x9, id_aa64dfr1_el1 -# CHECK: mrs x9, id_aa64afr0_el1 -# CHECK: mrs x9, id_aa64afr1_el1 -# CHECK: mrs x9, id_aa64isar0_el1 -# CHECK: mrs x9, id_aa64isar1_el1 -# CHECK: mrs x9, id_aa64mmfr0_el1 -# CHECK: mrs x9, id_aa64mmfr1_el1 -# CHECK: mrs x9, sctlr_el1 -# CHECK: mrs x9, sctlr_el2 -# CHECK: mrs x9, sctlr_el3 -# CHECK: mrs x9, actlr_el1 -# CHECK: mrs x9, actlr_el2 -# CHECK: mrs x9, actlr_el3 -# CHECK: mrs x9, cpacr_el1 -# CHECK: mrs x9, hcr_el2 -# CHECK: mrs x9, scr_el3 -# CHECK: mrs x9, mdcr_el2 -# CHECK: mrs x9, sder32_el3 -# CHECK: mrs x9, cptr_el2 -# CHECK: mrs x9, cptr_el3 -# CHECK: mrs x9, hstr_el2 -# CHECK: mrs x9, hacr_el2 -# CHECK: mrs x9, mdcr_el3 -# CHECK: mrs x9, ttbr0_el1 -# CHECK: mrs x9, ttbr0_el2 -# CHECK: mrs x9, ttbr0_el3 -# CHECK: mrs x9, ttbr1_el1 -# CHECK: mrs x9, tcr_el1 -# CHECK: mrs x9, tcr_el2 -# CHECK: mrs x9, tcr_el3 -# CHECK: mrs x9, vttbr_el2 -# CHECK: mrs x9, vtcr_el2 -# CHECK: mrs x9, dacr32_el2 -# CHECK: mrs x9, spsr_el1 -# CHECK: mrs x9, spsr_el2 -# CHECK: mrs x9, spsr_el3 -# CHECK: mrs x9, elr_el1 -# CHECK: mrs x9, elr_el2 -# CHECK: mrs x9, elr_el3 -# CHECK: mrs x9, sp_el0 -# CHECK: mrs x9, sp_el1 -# CHECK: mrs x9, sp_el2 -# CHECK: mrs x9, spsel -# CHECK: mrs x9, nzcv -# CHECK: mrs x9, daif -# CHECK: mrs x9, currentel -# CHECK: mrs x9, spsr_irq -# CHECK: mrs x9, spsr_abt -# CHECK: mrs x9, spsr_und -# CHECK: mrs x9, spsr_fiq -# CHECK: mrs x9, fpcr -# CHECK: mrs x9, fpsr -# CHECK: mrs x9, dspsr_el0 -# CHECK: mrs x9, dlr_el0 -# CHECK: mrs x9, ifsr32_el2 -# CHECK: mrs x9, afsr0_el1 -# CHECK: mrs x9, afsr0_el2 -# CHECK: mrs x9, afsr0_el3 -# CHECK: mrs x9, afsr1_el1 -# CHECK: mrs x9, afsr1_el2 -# CHECK: mrs x9, afsr1_el3 -# CHECK: mrs x9, esr_el1 -# CHECK: mrs x9, esr_el2 -# CHECK: mrs x9, esr_el3 -# CHECK: mrs x9, fpexc32_el2 -# CHECK: mrs x9, far_el1 -# CHECK: mrs x9, far_el2 -# CHECK: mrs x9, far_el3 -# CHECK: mrs x9, hpfar_el2 -# CHECK: mrs x9, par_el1 -# CHECK: mrs x9, pmcr_el0 -# CHECK: mrs x9, pmcntenset_el0 -# CHECK: mrs x9, pmcntenclr_el0 -# CHECK: mrs x9, pmovsclr_el0 -# CHECK: mrs x9, pmselr_el0 -# CHECK: mrs x9, pmceid0_el0 -# CHECK: mrs x9, pmceid1_el0 -# CHECK: mrs x9, pmccntr_el0 -# CHECK: mrs x9, pmxevtyper_el0 -# CHECK: mrs x9, pmxevcntr_el0 -# CHECK: mrs x9, pmuserenr_el0 -# CHECK: mrs x9, pmintenset_el1 -# CHECK: mrs x9, pmintenclr_el1 -# CHECK: mrs x9, pmovsset_el0 -# CHECK: mrs x9, mair_el1 -# CHECK: mrs x9, mair_el2 -# CHECK: mrs x9, mair_el3 -# CHECK: mrs x9, amair_el1 -# CHECK: mrs x9, amair_el2 -# CHECK: mrs x9, amair_el3 -# CHECK: mrs x9, vbar_el1 -# CHECK: mrs x9, vbar_el2 -# CHECK: mrs x9, vbar_el3 -# CHECK: mrs x9, rvbar_el1 -# CHECK: mrs x9, rvbar_el2 -# CHECK: mrs x9, rvbar_el3 -# CHECK: mrs x9, rmr_el1 -# CHECK: mrs x9, rmr_el2 -# CHECK: mrs x9, rmr_el3 -# CHECK: mrs x9, isr_el1 -# CHECK: mrs x9, contextidr_el1 -# CHECK: mrs x9, tpidr_el0 -# CHECK: mrs x9, tpidr_el2 -# CHECK: mrs x9, tpidr_el3 -# CHECK: mrs x9, tpidrro_el0 -# CHECK: mrs x9, tpidr_el1 -# CHECK: mrs x9, cntfrq_el0 -# CHECK: mrs x9, cntpct_el0 -# CHECK: mrs x9, cntvct_el0 -# CHECK: mrs x9, cntvoff_el2 -# CHECK: mrs x9, cntkctl_el1 -# CHECK: mrs x9, cnthctl_el2 -# CHECK: mrs x9, cntp_tval_el0 -# CHECK: mrs x9, cnthp_tval_el2 -# CHECK: mrs x9, cntps_tval_el1 -# CHECK: mrs x9, cntp_ctl_el0 -# CHECK: mrs x9, cnthp_ctl_el2 -# CHECK: mrs x9, cntps_ctl_el1 -# CHECK: mrs x9, cntp_cval_el0 -# CHECK: mrs x9, cnthp_cval_el2 -# CHECK: mrs x9, cntps_cval_el1 -# CHECK: mrs x9, cntv_tval_el0 -# CHECK: mrs x9, cntv_ctl_el0 -# CHECK: mrs x9, cntv_cval_el0 -# CHECK: mrs x9, pmevcntr0_el0 -# CHECK: mrs x9, pmevcntr1_el0 -# CHECK: mrs x9, pmevcntr2_el0 -# CHECK: mrs x9, pmevcntr3_el0 -# CHECK: mrs x9, pmevcntr4_el0 -# CHECK: mrs x9, pmevcntr5_el0 -# CHECK: mrs x9, pmevcntr6_el0 -# CHECK: mrs x9, pmevcntr7_el0 -# CHECK: mrs x9, pmevcntr8_el0 -# CHECK: mrs x9, pmevcntr9_el0 -# CHECK: mrs x9, pmevcntr10_el0 -# CHECK: mrs x9, pmevcntr11_el0 -# CHECK: mrs x9, pmevcntr12_el0 -# CHECK: mrs x9, pmevcntr13_el0 -# CHECK: mrs x9, pmevcntr14_el0 -# CHECK: mrs x9, pmevcntr15_el0 -# CHECK: mrs x9, pmevcntr16_el0 -# CHECK: mrs x9, pmevcntr17_el0 -# CHECK: mrs x9, pmevcntr18_el0 -# CHECK: mrs x9, pmevcntr19_el0 -# CHECK: mrs x9, pmevcntr20_el0 -# CHECK: mrs x9, pmevcntr21_el0 -# CHECK: mrs x9, pmevcntr22_el0 -# CHECK: mrs x9, pmevcntr23_el0 -# CHECK: mrs x9, pmevcntr24_el0 -# CHECK: mrs x9, pmevcntr25_el0 -# CHECK: mrs x9, pmevcntr26_el0 -# CHECK: mrs x9, pmevcntr27_el0 -# CHECK: mrs x9, pmevcntr28_el0 -# CHECK: mrs x9, pmevcntr29_el0 -# CHECK: mrs x9, pmevcntr30_el0 -# CHECK: mrs x9, pmccfiltr_el0 -# CHECK: mrs x9, pmevtyper0_el0 -# CHECK: mrs x9, pmevtyper1_el0 -# CHECK: mrs x9, pmevtyper2_el0 -# CHECK: mrs x9, pmevtyper3_el0 -# CHECK: mrs x9, pmevtyper4_el0 -# CHECK: mrs x9, pmevtyper5_el0 -# CHECK: mrs x9, pmevtyper6_el0 -# CHECK: mrs x9, pmevtyper7_el0 -# CHECK: mrs x9, pmevtyper8_el0 -# CHECK: mrs x9, pmevtyper9_el0 -# CHECK: mrs x9, pmevtyper10_el0 -# CHECK: mrs x9, pmevtyper11_el0 -# CHECK: mrs x9, pmevtyper12_el0 -# CHECK: mrs x9, pmevtyper13_el0 -# CHECK: mrs x9, pmevtyper14_el0 -# CHECK: mrs x9, pmevtyper15_el0 -# CHECK: mrs x9, pmevtyper16_el0 -# CHECK: mrs x9, pmevtyper17_el0 -# CHECK: mrs x9, pmevtyper18_el0 -# CHECK: mrs x9, pmevtyper19_el0 -# CHECK: mrs x9, pmevtyper20_el0 -# CHECK: mrs x9, pmevtyper21_el0 -# CHECK: mrs x9, pmevtyper22_el0 -# CHECK: mrs x9, pmevtyper23_el0 -# CHECK: mrs x9, pmevtyper24_el0 -# CHECK: mrs x9, pmevtyper25_el0 -# CHECK: mrs x9, pmevtyper26_el0 -# CHECK: mrs x9, pmevtyper27_el0 -# CHECK: mrs x9, pmevtyper28_el0 -# CHECK: mrs x9, pmevtyper29_el0 -# CHECK: mrs x9, pmevtyper30_el0 +# CHECK: msr {{teecr32_el1|TEECR32_EL1}}, x12 +# CHECK: msr {{osdtrrx_el1|OSDTRRX_EL1}}, x12 +# CHECK: msr {{mdccint_el1|MDCCINT_EL1}}, x12 +# CHECK: msr {{mdscr_el1|MDSCR_EL1}}, x12 +# CHECK: msr {{osdtrtx_el1|OSDTRTX_EL1}}, x12 +# CHECK: msr {{dbgdtr_el0|DBGDTR_EL0}}, x12 +# CHECK: msr {{dbgdtrtx_el0|DBGDTRTX_EL0}}, x12 +# CHECK: msr {{oseccr_el1|OSECCR_EL1}}, x12 +# CHECK: msr {{dbgvcr32_el2|DBGVCR32_EL2}}, x12 +# CHECK: msr {{dbgbvr0_el1|DBGBVR0_EL1}}, x12 +# CHECK: msr {{dbgbvr1_el1|DBGBVR1_EL1}}, x12 +# CHECK: msr {{dbgbvr2_el1|DBGBVR2_EL1}}, x12 +# CHECK: msr {{dbgbvr3_el1|DBGBVR3_EL1}}, x12 +# CHECK: msr {{dbgbvr4_el1|DBGBVR4_EL1}}, x12 +# CHECK: msr {{dbgbvr5_el1|DBGBVR5_EL1}}, x12 +# CHECK: msr {{dbgbvr6_el1|DBGBVR6_EL1}}, x12 +# CHECK: msr {{dbgbvr7_el1|DBGBVR7_EL1}}, x12 +# CHECK: msr {{dbgbvr8_el1|DBGBVR8_EL1}}, x12 +# CHECK: msr {{dbgbvr9_el1|DBGBVR9_EL1}}, x12 +# CHECK: msr {{dbgbvr10_el1|DBGBVR10_EL1}}, x12 +# CHECK: msr {{dbgbvr11_el1|DBGBVR11_EL1}}, x12 +# CHECK: msr {{dbgbvr12_el1|DBGBVR12_EL1}}, x12 +# CHECK: msr {{dbgbvr13_el1|DBGBVR13_EL1}}, x12 +# CHECK: msr {{dbgbvr14_el1|DBGBVR14_EL1}}, x12 +# CHECK: msr {{dbgbvr15_el1|DBGBVR15_EL1}}, x12 +# CHECK: msr {{dbgbcr0_el1|DBGBCR0_EL1}}, x12 +# CHECK: msr {{dbgbcr1_el1|DBGBCR1_EL1}}, x12 +# CHECK: msr {{dbgbcr2_el1|DBGBCR2_EL1}}, x12 +# CHECK: msr {{dbgbcr3_el1|DBGBCR3_EL1}}, x12 +# CHECK: msr {{dbgbcr4_el1|DBGBCR4_EL1}}, x12 +# CHECK: msr {{dbgbcr5_el1|DBGBCR5_EL1}}, x12 +# CHECK: msr {{dbgbcr6_el1|DBGBCR6_EL1}}, x12 +# CHECK: msr {{dbgbcr7_el1|DBGBCR7_EL1}}, x12 +# CHECK: msr {{dbgbcr8_el1|DBGBCR8_EL1}}, x12 +# CHECK: msr {{dbgbcr9_el1|DBGBCR9_EL1}}, x12 +# CHECK: msr {{dbgbcr10_el1|DBGBCR10_EL1}}, x12 +# CHECK: msr {{dbgbcr11_el1|DBGBCR11_EL1}}, x12 +# CHECK: msr {{dbgbcr12_el1|DBGBCR12_EL1}}, x12 +# CHECK: msr {{dbgbcr13_el1|DBGBCR13_EL1}}, x12 +# CHECK: msr {{dbgbcr14_el1|DBGBCR14_EL1}}, x12 +# CHECK: msr {{dbgbcr15_el1|DBGBCR15_EL1}}, x12 +# CHECK: msr {{dbgwvr0_el1|DBGWVR0_EL1}}, x12 +# CHECK: msr {{dbgwvr1_el1|DBGWVR1_EL1}}, x12 +# CHECK: msr {{dbgwvr2_el1|DBGWVR2_EL1}}, x12 +# CHECK: msr {{dbgwvr3_el1|DBGWVR3_EL1}}, x12 +# CHECK: msr {{dbgwvr4_el1|DBGWVR4_EL1}}, x12 +# CHECK: msr {{dbgwvr5_el1|DBGWVR5_EL1}}, x12 +# CHECK: msr {{dbgwvr6_el1|DBGWVR6_EL1}}, x12 +# CHECK: msr {{dbgwvr7_el1|DBGWVR7_EL1}}, x12 +# CHECK: msr {{dbgwvr8_el1|DBGWVR8_EL1}}, x12 +# CHECK: msr {{dbgwvr9_el1|DBGWVR9_EL1}}, x12 +# CHECK: msr {{dbgwvr10_el1|DBGWVR10_EL1}}, x12 +# CHECK: msr {{dbgwvr11_el1|DBGWVR11_EL1}}, x12 +# CHECK: msr {{dbgwvr12_el1|DBGWVR12_EL1}}, x12 +# CHECK: msr {{dbgwvr13_el1|DBGWVR13_EL1}}, x12 +# CHECK: msr {{dbgwvr14_el1|DBGWVR14_EL1}}, x12 +# CHECK: msr {{dbgwvr15_el1|DBGWVR15_EL1}}, x12 +# CHECK: msr {{dbgwcr0_el1|DBGWCR0_EL1}}, x12 +# CHECK: msr {{dbgwcr1_el1|DBGWCR1_EL1}}, x12 +# CHECK: msr {{dbgwcr2_el1|DBGWCR2_EL1}}, x12 +# CHECK: msr {{dbgwcr3_el1|DBGWCR3_EL1}}, x12 +# CHECK: msr {{dbgwcr4_el1|DBGWCR4_EL1}}, x12 +# CHECK: msr {{dbgwcr5_el1|DBGWCR5_EL1}}, x12 +# CHECK: msr {{dbgwcr6_el1|DBGWCR6_EL1}}, x12 +# CHECK: msr {{dbgwcr7_el1|DBGWCR7_EL1}}, x12 +# CHECK: msr {{dbgwcr8_el1|DBGWCR8_EL1}}, x12 +# CHECK: msr {{dbgwcr9_el1|DBGWCR9_EL1}}, x12 +# CHECK: msr {{dbgwcr10_el1|DBGWCR10_EL1}}, x12 +# CHECK: msr {{dbgwcr11_el1|DBGWCR11_EL1}}, x12 +# CHECK: msr {{dbgwcr12_el1|DBGWCR12_EL1}}, x12 +# CHECK: msr {{dbgwcr13_el1|DBGWCR13_EL1}}, x12 +# CHECK: msr {{dbgwcr14_el1|DBGWCR14_EL1}}, x12 +# CHECK: msr {{dbgwcr15_el1|DBGWCR15_EL1}}, x12 +# CHECK: msr {{teehbr32_el1|TEEHBR32_EL1}}, x12 +# CHECK: msr {{oslar_el1|OSLAR_EL1}}, x12 +# CHECK: msr {{osdlr_el1|OSDLR_EL1}}, x12 +# CHECK: msr {{dbgprcr_el1|DBGPRCR_EL1}}, x12 +# CHECK: msr {{dbgclaimset_el1|DBGCLAIMSET_EL1}}, x12 +# CHECK: msr {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}, x12 +# CHECK: msr {{csselr_el1|CSSELR_EL1}}, x12 +# CHECK: msr {{vpidr_el2|VPIDR_EL2}}, x12 +# CHECK: msr {{vmpidr_el2|VMPIDR_EL2}}, x12 +# CHECK: msr {{sctlr_el1|SCTLR_EL1}}, x12 +# CHECK: msr {{sctlr_el2|SCTLR_EL2}}, x12 +# CHECK: msr {{sctlr_el3|SCTLR_EL3}}, x12 +# CHECK: msr {{actlr_el1|ACTLR_EL1}}, x12 +# CHECK: msr {{actlr_el2|ACTLR_EL2}}, x12 +# CHECK: msr {{actlr_el3|ACTLR_EL3}}, x12 +# CHECK: msr {{cpacr_el1|CPACR_EL1}}, x12 +# CHECK: msr {{hcr_el2|HCR_EL2}}, x12 +# CHECK: msr {{scr_el3|SCR_EL3}}, x12 +# CHECK: msr {{mdcr_el2|MDCR_EL2}}, x12 +# CHECK: msr {{sder32_el3|SDER32_EL3}}, x12 +# CHECK: msr {{cptr_el2|CPTR_EL2}}, x12 +# CHECK: msr {{cptr_el3|CPTR_EL3}}, x12 +# CHECK: msr {{hstr_el2|HSTR_EL2}}, x12 +# CHECK: msr {{hacr_el2|HACR_EL2}}, x12 +# CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12 +# CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12 +# CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12 +# CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12 +# CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12 +# CHECK: msr {{tcr_el1|TCR_EL1}}, x12 +# CHECK: msr {{tcr_el2|TCR_EL2}}, x12 +# CHECK: msr {{tcr_el3|TCR_EL3}}, x12 +# CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12 +# CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12 +# CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12 +# CHECK: msr {{spsr_el1|SPSR_EL1}}, x12 +# CHECK: msr {{spsr_el2|SPSR_EL2}}, x12 +# CHECK: msr {{spsr_el3|SPSR_EL3}}, x12 +# CHECK: msr {{elr_el1|ELR_EL1}}, x12 +# CHECK: msr {{elr_el2|ELR_EL2}}, x12 +# CHECK: msr {{elr_el3|ELR_EL3}}, x12 +# CHECK: msr {{sp_el0|SP_EL0}}, x12 +# CHECK: msr {{sp_el1|SP_EL1}}, x12 +# CHECK: msr {{sp_el2|SP_EL2}}, x12 +# CHECK: msr {{spsel|SPSEL}}, x12 +# CHECK: msr {{nzcv|NZCV}}, x12 +# CHECK: msr {{daif|DAIF}}, x12 +# CHECK: msr {{currentel|CURRENTEL}}, x12 +# CHECK: msr {{spsr_irq|SPSR_IRQ}}, x12 +# CHECK: msr {{spsr_abt|SPSR_ABT}}, x12 +# CHECK: msr {{spsr_und|SPSR_UND}}, x12 +# CHECK: msr {{spsr_fiq|SPSR_FIQ}}, x12 +# CHECK: msr {{fpcr|FPCR}}, x12 +# CHECK: msr {{fpsr|FPSR}}, x12 +# CHECK: msr {{dspsr_el0|DSPSR_EL0}}, x12 +# CHECK: msr {{dlr_el0|DLR_EL0}}, x12 +# CHECK: msr {{ifsr32_el2|IFSR32_EL2}}, x12 +# CHECK: msr {{afsr0_el1|AFSR0_EL1}}, x12 +# CHECK: msr {{afsr0_el2|AFSR0_EL2}}, x12 +# CHECK: msr {{afsr0_el3|AFSR0_EL3}}, x12 +# CHECK: msr {{afsr1_el1|AFSR1_EL1}}, x12 +# CHECK: msr {{afsr1_el2|AFSR1_EL2}}, x12 +# CHECK: msr {{afsr1_el3|AFSR1_EL3}}, x12 +# CHECK: msr {{esr_el1|ESR_EL1}}, x12 +# CHECK: msr {{esr_el2|ESR_EL2}}, x12 +# CHECK: msr {{esr_el3|ESR_EL3}}, x12 +# CHECK: msr {{fpexc32_el2|FPEXC32_EL2}}, x12 +# CHECK: msr {{far_el1|FAR_EL1}}, x12 +# CHECK: msr {{far_el2|FAR_EL2}}, x12 +# CHECK: msr {{far_el3|FAR_EL3}}, x12 +# CHECK: msr {{hpfar_el2|HPFAR_EL2}}, x12 +# CHECK: msr {{par_el1|PAR_EL1}}, x12 +# CHECK: msr {{pmcr_el0|PMCR_EL0}}, x12 +# CHECK: msr {{pmcntenset_el0|PMCNTENSET_EL0}}, x12 +# CHECK: msr {{pmcntenclr_el0|PMCNTENCLR_EL0}}, x12 +# CHECK: msr {{pmovsclr_el0|PMOVSCLR_EL0}}, x12 +# CHECK: msr {{pmselr_el0|PMSELR_EL0}}, x12 +# CHECK: msr {{pmccntr_el0|PMCCNTR_EL0}}, x12 +# CHECK: msr {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12 +# CHECK: msr {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12 +# CHECK: msr {{pmuserenr_el0|PMUSERENR_EL0}}, x12 +# CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12 +# CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12 +# CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12 +# CHECK: msr {{mair_el1|MAIR_EL1}}, x12 +# CHECK: msr {{mair_el2|MAIR_EL2}}, x12 +# CHECK: msr {{mair_el3|MAIR_EL3}}, x12 +# CHECK: msr {{amair_el1|AMAIR_EL1}}, x12 +# CHECK: msr {{amair_el2|AMAIR_EL2}}, x12 +# CHECK: msr {{amair_el3|AMAIR_EL3}}, x12 +# CHECK: msr {{vbar_el1|VBAR_EL1}}, x12 +# CHECK: msr {{vbar_el2|VBAR_EL2}}, x12 +# CHECK: msr {{vbar_el3|VBAR_EL3}}, x12 +# CHECK: msr {{rmr_el1|RMR_EL1}}, x12 +# CHECK: msr {{rmr_el2|RMR_EL2}}, x12 +# CHECK: msr {{rmr_el3|RMR_EL3}}, x12 +# CHECK: msr {{tpidr_el0|TPIDR_EL0}}, x12 +# CHECK: msr {{tpidr_el2|TPIDR_EL2}}, x12 +# CHECK: msr {{tpidr_el3|TPIDR_EL3}}, x12 +# CHECK: msr {{tpidrro_el0|TPIDRRO_EL0}}, x12 +# CHECK: msr {{tpidr_el1|TPIDR_EL1}}, x12 +# CHECK: msr {{cntfrq_el0|CNTFRQ_EL0}}, x12 +# CHECK: msr {{cntvoff_el2|CNTVOFF_EL2}}, x12 +# CHECK: msr {{cntkctl_el1|CNTKCTL_EL1}}, x12 +# CHECK: msr {{cnthctl_el2|CNTHCTL_EL2}}, x12 +# CHECK: msr {{cntp_tval_el0|CNTP_TVAL_EL0}}, x12 +# CHECK: msr {{cnthp_tval_el2|CNTHP_TVAL_EL2}}, x12 +# CHECK: msr {{cntps_tval_el1|CNTPS_TVAL_EL1}}, x12 +# CHECK: msr {{cntp_ctl_el0|CNTP_CTL_EL0}}, x12 +# CHECK: msr {{cnthp_ctl_el2|CNTHP_CTL_EL2}}, x12 +# CHECK: msr {{cntps_ctl_el1|CNTPS_CTL_EL1}}, x12 +# CHECK: msr {{cntp_cval_el0|CNTP_CVAL_EL0}}, x12 +# CHECK: msr {{cnthp_cval_el2|CNTHP_CVAL_EL2}}, x12 +# CHECK: msr {{cntps_cval_el1|CNTPS_CVAL_EL1}}, x12 +# CHECK: msr {{cntv_tval_el0|CNTV_TVAL_EL0}}, x12 +# CHECK: msr {{cntv_ctl_el0|CNTV_CTL_EL0}}, x12 +# CHECK: msr {{cntv_cval_el0|CNTV_CVAL_EL0}}, x12 +# CHECK: msr {{pmevcntr0_el0|PMEVCNTR0_EL0}}, x12 +# CHECK: msr {{pmevcntr1_el0|PMEVCNTR1_EL0}}, x12 +# CHECK: msr {{pmevcntr2_el0|PMEVCNTR2_EL0}}, x12 +# CHECK: msr {{pmevcntr3_el0|PMEVCNTR3_EL0}}, x12 +# CHECK: msr {{pmevcntr4_el0|PMEVCNTR4_EL0}}, x12 +# CHECK: msr {{pmevcntr5_el0|PMEVCNTR5_EL0}}, x12 +# CHECK: msr {{pmevcntr6_el0|PMEVCNTR6_EL0}}, x12 +# CHECK: msr {{pmevcntr7_el0|PMEVCNTR7_EL0}}, x12 +# CHECK: msr {{pmevcntr8_el0|PMEVCNTR8_EL0}}, x12 +# CHECK: msr {{pmevcntr9_el0|PMEVCNTR9_EL0}}, x12 +# CHECK: msr {{pmevcntr10_el0|PMEVCNTR10_EL0}}, x12 +# CHECK: msr {{pmevcntr11_el0|PMEVCNTR11_EL0}}, x12 +# CHECK: msr {{pmevcntr12_el0|PMEVCNTR12_EL0}}, x12 +# CHECK: msr {{pmevcntr13_el0|PMEVCNTR13_EL0}}, x12 +# CHECK: msr {{pmevcntr14_el0|PMEVCNTR14_EL0}}, x12 +# CHECK: msr {{pmevcntr15_el0|PMEVCNTR15_EL0}}, x12 +# CHECK: msr {{pmevcntr16_el0|PMEVCNTR16_EL0}}, x12 +# CHECK: msr {{pmevcntr17_el0|PMEVCNTR17_EL0}}, x12 +# CHECK: msr {{pmevcntr18_el0|PMEVCNTR18_EL0}}, x12 +# CHECK: msr {{pmevcntr19_el0|PMEVCNTR19_EL0}}, x12 +# CHECK: msr {{pmevcntr20_el0|PMEVCNTR20_EL0}}, x12 +# CHECK: msr {{pmevcntr21_el0|PMEVCNTR21_EL0}}, x12 +# CHECK: msr {{pmevcntr22_el0|PMEVCNTR22_EL0}}, x12 +# CHECK: msr {{pmevcntr23_el0|PMEVCNTR23_EL0}}, x12 +# CHECK: msr {{pmevcntr24_el0|PMEVCNTR24_EL0}}, x12 +# CHECK: msr {{pmevcntr25_el0|PMEVCNTR25_EL0}}, x12 +# CHECK: msr {{pmevcntr26_el0|PMEVCNTR26_EL0}}, x12 +# CHECK: msr {{pmevcntr27_el0|PMEVCNTR27_EL0}}, x12 +# CHECK: msr {{pmevcntr28_el0|PMEVCNTR28_EL0}}, x12 +# CHECK: msr {{pmevcntr29_el0|PMEVCNTR29_EL0}}, x12 +# CHECK: msr {{pmevcntr30_el0|PMEVCNTR30_EL0}}, x12 +# CHECK: msr {{pmccfiltr_el0|PMCCFILTR_EL0}}, x12 +# CHECK: msr {{pmevtyper0_el0|PMEVTYPER0_EL0}}, x12 +# CHECK: msr {{pmevtyper1_el0|PMEVTYPER1_EL0}}, x12 +# CHECK: msr {{pmevtyper2_el0|PMEVTYPER2_EL0}}, x12 +# CHECK: msr {{pmevtyper3_el0|PMEVTYPER3_EL0}}, x12 +# CHECK: msr {{pmevtyper4_el0|PMEVTYPER4_EL0}}, x12 +# CHECK: msr {{pmevtyper5_el0|PMEVTYPER5_EL0}}, x12 +# CHECK: msr {{pmevtyper6_el0|PMEVTYPER6_EL0}}, x12 +# CHECK: msr {{pmevtyper7_el0|PMEVTYPER7_EL0}}, x12 +# CHECK: msr {{pmevtyper8_el0|PMEVTYPER8_EL0}}, x12 +# CHECK: msr {{pmevtyper9_el0|PMEVTYPER9_EL0}}, x12 +# CHECK: msr {{pmevtyper10_el0|PMEVTYPER10_EL0}}, x12 +# CHECK: msr {{pmevtyper11_el0|PMEVTYPER11_EL0}}, x12 +# CHECK: msr {{pmevtyper12_el0|PMEVTYPER12_EL0}}, x12 +# CHECK: msr {{pmevtyper13_el0|PMEVTYPER13_EL0}}, x12 +# CHECK: msr {{pmevtyper14_el0|PMEVTYPER14_EL0}}, x12 +# CHECK: msr {{pmevtyper15_el0|PMEVTYPER15_EL0}}, x12 +# CHECK: msr {{pmevtyper16_el0|PMEVTYPER16_EL0}}, x12 +# CHECK: msr {{pmevtyper17_el0|PMEVTYPER17_EL0}}, x12 +# CHECK: msr {{pmevtyper18_el0|PMEVTYPER18_EL0}}, x12 +# CHECK: msr {{pmevtyper19_el0|PMEVTYPER19_EL0}}, x12 +# CHECK: msr {{pmevtyper20_el0|PMEVTYPER20_EL0}}, x12 +# CHECK: msr {{pmevtyper21_el0|PMEVTYPER21_EL0}}, x12 +# CHECK: msr {{pmevtyper22_el0|PMEVTYPER22_EL0}}, x12 +# CHECK: msr {{pmevtyper23_el0|PMEVTYPER23_EL0}}, x12 +# CHECK: msr {{pmevtyper24_el0|PMEVTYPER24_EL0}}, x12 +# CHECK: msr {{pmevtyper25_el0|PMEVTYPER25_EL0}}, x12 +# CHECK: msr {{pmevtyper26_el0|PMEVTYPER26_EL0}}, x12 +# CHECK: msr {{pmevtyper27_el0|PMEVTYPER27_EL0}}, x12 +# CHECK: msr {{pmevtyper28_el0|PMEVTYPER28_EL0}}, x12 +# CHECK: msr {{pmevtyper29_el0|PMEVTYPER29_EL0}}, x12 +# CHECK: msr {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12 +# CHECK: mrs x9, {{teecr32_el1|TEECR32_EL1}} +# CHECK: mrs x9, {{osdtrrx_el1|OSDTRRX_EL1}} +# CHECK: mrs x9, {{mdccsr_el0|MDCCSR_EL0}} +# CHECK: mrs x9, {{mdccint_el1|MDCCINT_EL1}} +# CHECK: mrs x9, {{mdscr_el1|MDSCR_EL1}} +# CHECK: mrs x9, {{osdtrtx_el1|OSDTRTX_EL1}} +# CHECK: mrs x9, {{dbgdtr_el0|DBGDTR_EL0}} +# CHECK: mrs x9, {{dbgdtrrx_el0|DBGDTRRX_EL0}} +# CHECK: mrs x9, {{oseccr_el1|OSECCR_EL1}} +# CHECK: mrs x9, {{dbgvcr32_el2|DBGVCR32_EL2}} +# CHECK: mrs x9, {{dbgbvr0_el1|DBGBVR0_EL1}} +# CHECK: mrs x9, {{dbgbvr1_el1|DBGBVR1_EL1}} +# CHECK: mrs x9, {{dbgbvr2_el1|DBGBVR2_EL1}} +# CHECK: mrs x9, {{dbgbvr3_el1|DBGBVR3_EL1}} +# CHECK: mrs x9, {{dbgbvr4_el1|DBGBVR4_EL1}} +# CHECK: mrs x9, {{dbgbvr5_el1|DBGBVR5_EL1}} +# CHECK: mrs x9, {{dbgbvr6_el1|DBGBVR6_EL1}} +# CHECK: mrs x9, {{dbgbvr7_el1|DBGBVR7_EL1}} +# CHECK: mrs x9, {{dbgbvr8_el1|DBGBVR8_EL1}} +# CHECK: mrs x9, {{dbgbvr9_el1|DBGBVR9_EL1}} +# CHECK: mrs x9, {{dbgbvr10_el1|DBGBVR10_EL1}} +# CHECK: mrs x9, {{dbgbvr11_el1|DBGBVR11_EL1}} +# CHECK: mrs x9, {{dbgbvr12_el1|DBGBVR12_EL1}} +# CHECK: mrs x9, {{dbgbvr13_el1|DBGBVR13_EL1}} +# CHECK: mrs x9, {{dbgbvr14_el1|DBGBVR14_EL1}} +# CHECK: mrs x9, {{dbgbvr15_el1|DBGBVR15_EL1}} +# CHECK: mrs x9, {{dbgbcr0_el1|DBGBCR0_EL1}} +# CHECK: mrs x9, {{dbgbcr1_el1|DBGBCR1_EL1}} +# CHECK: mrs x9, {{dbgbcr2_el1|DBGBCR2_EL1}} +# CHECK: mrs x9, {{dbgbcr3_el1|DBGBCR3_EL1}} +# CHECK: mrs x9, {{dbgbcr4_el1|DBGBCR4_EL1}} +# CHECK: mrs x9, {{dbgbcr5_el1|DBGBCR5_EL1}} +# CHECK: mrs x9, {{dbgbcr6_el1|DBGBCR6_EL1}} +# CHECK: mrs x9, {{dbgbcr7_el1|DBGBCR7_EL1}} +# CHECK: mrs x9, {{dbgbcr8_el1|DBGBCR8_EL1}} +# CHECK: mrs x9, {{dbgbcr9_el1|DBGBCR9_EL1}} +# CHECK: mrs x9, {{dbgbcr10_el1|DBGBCR10_EL1}} +# CHECK: mrs x9, {{dbgbcr11_el1|DBGBCR11_EL1}} +# CHECK: mrs x9, {{dbgbcr12_el1|DBGBCR12_EL1}} +# CHECK: mrs x9, {{dbgbcr13_el1|DBGBCR13_EL1}} +# CHECK: mrs x9, {{dbgbcr14_el1|DBGBCR14_EL1}} +# CHECK: mrs x9, {{dbgbcr15_el1|DBGBCR15_EL1}} +# CHECK: mrs x9, {{dbgwvr0_el1|DBGWVR0_EL1}} +# CHECK: mrs x9, {{dbgwvr1_el1|DBGWVR1_EL1}} +# CHECK: mrs x9, {{dbgwvr2_el1|DBGWVR2_EL1}} +# CHECK: mrs x9, {{dbgwvr3_el1|DBGWVR3_EL1}} +# CHECK: mrs x9, {{dbgwvr4_el1|DBGWVR4_EL1}} +# CHECK: mrs x9, {{dbgwvr5_el1|DBGWVR5_EL1}} +# CHECK: mrs x9, {{dbgwvr6_el1|DBGWVR6_EL1}} +# CHECK: mrs x9, {{dbgwvr7_el1|DBGWVR7_EL1}} +# CHECK: mrs x9, {{dbgwvr8_el1|DBGWVR8_EL1}} +# CHECK: mrs x9, {{dbgwvr9_el1|DBGWVR9_EL1}} +# CHECK: mrs x9, {{dbgwvr10_el1|DBGWVR10_EL1}} +# CHECK: mrs x9, {{dbgwvr11_el1|DBGWVR11_EL1}} +# CHECK: mrs x9, {{dbgwvr12_el1|DBGWVR12_EL1}} +# CHECK: mrs x9, {{dbgwvr13_el1|DBGWVR13_EL1}} +# CHECK: mrs x9, {{dbgwvr14_el1|DBGWVR14_EL1}} +# CHECK: mrs x9, {{dbgwvr15_el1|DBGWVR15_EL1}} +# CHECK: mrs x9, {{dbgwcr0_el1|DBGWCR0_EL1}} +# CHECK: mrs x9, {{dbgwcr1_el1|DBGWCR1_EL1}} +# CHECK: mrs x9, {{dbgwcr2_el1|DBGWCR2_EL1}} +# CHECK: mrs x9, {{dbgwcr3_el1|DBGWCR3_EL1}} +# CHECK: mrs x9, {{dbgwcr4_el1|DBGWCR4_EL1}} +# CHECK: mrs x9, {{dbgwcr5_el1|DBGWCR5_EL1}} +# CHECK: mrs x9, {{dbgwcr6_el1|DBGWCR6_EL1}} +# CHECK: mrs x9, {{dbgwcr7_el1|DBGWCR7_EL1}} +# CHECK: mrs x9, {{dbgwcr8_el1|DBGWCR8_EL1}} +# CHECK: mrs x9, {{dbgwcr9_el1|DBGWCR9_EL1}} +# CHECK: mrs x9, {{dbgwcr10_el1|DBGWCR10_EL1}} +# CHECK: mrs x9, {{dbgwcr11_el1|DBGWCR11_EL1}} +# CHECK: mrs x9, {{dbgwcr12_el1|DBGWCR12_EL1}} +# CHECK: mrs x9, {{dbgwcr13_el1|DBGWCR13_EL1}} +# CHECK: mrs x9, {{dbgwcr14_el1|DBGWCR14_EL1}} +# CHECK: mrs x9, {{dbgwcr15_el1|DBGWCR15_EL1}} +# CHECK: mrs x9, {{mdrar_el1|MDRAR_EL1}} +# CHECK: mrs x9, {{teehbr32_el1|TEEHBR32_EL1}} +# CHECK: mrs x9, {{oslsr_el1|OSLSR_EL1}} +# CHECK: mrs x9, {{osdlr_el1|OSDLR_EL1}} +# CHECK: mrs x9, {{dbgprcr_el1|DBGPRCR_EL1}} +# CHECK: mrs x9, {{dbgclaimset_el1|DBGCLAIMSET_EL1}} +# CHECK: mrs x9, {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}} +# CHECK: mrs x9, {{dbgauthstatus_el1|DBGAUTHSTATUS_EL1}} +# CHECK: mrs x9, {{midr_el1|MIDR_EL1}} +# CHECK: mrs x9, {{ccsidr_el1|CCSIDR_EL1}} +# CHECK: mrs x9, {{csselr_el1|CSSELR_EL1}} +# CHECK: mrs x9, {{vpidr_el2|VPIDR_EL2}} +# CHECK: mrs x9, {{clidr_el1|CLIDR_EL1}} +# CHECK: mrs x9, {{ctr_el0|CTR_EL0}} +# CHECK: mrs x9, {{mpidr_el1|MPIDR_EL1}} +# CHECK: mrs x9, {{vmpidr_el2|VMPIDR_EL2}} +# CHECK: mrs x9, {{revidr_el1|REVIDR_EL1}} +# CHECK: mrs x9, {{aidr_el1|AIDR_EL1}} +# CHECK: mrs x9, {{dczid_el0|DCZID_EL0}} +# CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}} +# CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}} +# CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}} +# CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}} +# CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}} +# CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}} +# CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}} +# CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}} +# CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}} +# CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}} +# CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}} +# CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}} +# CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}} +# CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}} +# CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}} +# CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}} +# CHECK: mrs x9, {{mvfr2_el1|MVFR2_EL1}} +# CHECK: mrs x9, {{id_aa64pfr0_el1|ID_AA64PFR0_EL1}} +# CHECK: mrs x9, {{id_aa64pfr1_el1|ID_AA64PFR1_EL1}} +# CHECK: mrs x9, {{id_aa64dfr0_el1|ID_AA64DFR0_EL1}} +# CHECK: mrs x9, {{id_aa64dfr1_el1|ID_AA64DFR1_EL1}} +# CHECK: mrs x9, {{id_aa64afr0_el1|ID_AA64AFR0_EL1}} +# CHECK: mrs x9, {{id_aa64afr1_el1|ID_AA64AFR1_EL1}} +# CHECK: mrs x9, {{id_aa64isar0_el1|ID_AA64ISAR0_EL1}} +# CHECK: mrs x9, {{id_aa64isar1_el1|ID_AA64ISAR1_EL1}} +# CHECK: mrs x9, {{id_aa64mmfr0_el1|ID_AA64MMFR0_EL1}} +# CHECK: mrs x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}} +# CHECK: mrs x9, {{sctlr_el1|SCTLR_EL1}} +# CHECK: mrs x9, {{sctlr_el2|SCTLR_EL2}} +# CHECK: mrs x9, {{sctlr_el3|SCTLR_EL3}} +# CHECK: mrs x9, {{actlr_el1|ACTLR_EL1}} +# CHECK: mrs x9, {{actlr_el2|ACTLR_EL2}} +# CHECK: mrs x9, {{actlr_el3|ACTLR_EL3}} +# CHECK: mrs x9, {{cpacr_el1|CPACR_EL1}} +# CHECK: mrs x9, {{hcr_el2|HCR_EL2}} +# CHECK: mrs x9, {{scr_el3|SCR_EL3}} +# CHECK: mrs x9, {{mdcr_el2|MDCR_EL2}} +# CHECK: mrs x9, {{sder32_el3|SDER32_EL3}} +# CHECK: mrs x9, {{cptr_el2|CPTR_EL2}} +# CHECK: mrs x9, {{cptr_el3|CPTR_EL3}} +# CHECK: mrs x9, {{hstr_el2|HSTR_EL2}} +# CHECK: mrs x9, {{hacr_el2|HACR_EL2}} +# CHECK: mrs x9, {{mdcr_el3|MDCR_EL3}} +# CHECK: mrs x9, {{ttbr0_el1|TTBR0_EL1}} +# CHECK: mrs x9, {{ttbr0_el2|TTBR0_EL2}} +# CHECK: mrs x9, {{ttbr0_el3|TTBR0_EL3}} +# CHECK: mrs x9, {{ttbr1_el1|TTBR1_EL1}} +# CHECK: mrs x9, {{tcr_el1|TCR_EL1}} +# CHECK: mrs x9, {{tcr_el2|TCR_EL2}} +# CHECK: mrs x9, {{tcr_el3|TCR_EL3}} +# CHECK: mrs x9, {{vttbr_el2|VTTBR_EL2}} +# CHECK: mrs x9, {{vtcr_el2|VTCR_EL2}} +# CHECK: mrs x9, {{dacr32_el2|DACR32_EL2}} +# CHECK: mrs x9, {{spsr_el1|SPSR_EL1}} +# CHECK: mrs x9, {{spsr_el2|SPSR_EL2}} +# CHECK: mrs x9, {{spsr_el3|SPSR_EL3}} +# CHECK: mrs x9, {{elr_el1|ELR_EL1}} +# CHECK: mrs x9, {{elr_el2|ELR_EL2}} +# CHECK: mrs x9, {{elr_el3|ELR_EL3}} +# CHECK: mrs x9, {{sp_el0|SP_EL0}} +# CHECK: mrs x9, {{sp_el1|SP_EL1}} +# CHECK: mrs x9, {{sp_el2|SP_EL2}} +# CHECK: mrs x9, {{spsel|SPSEL}} +# CHECK: mrs x9, {{nzcv|NZCV}} +# CHECK: mrs x9, {{daif|DAIF}} +# CHECK: mrs x9, {{currentel|CURRENTEL}} +# CHECK: mrs x9, {{spsr_irq|SPSR_IRQ}} +# CHECK: mrs x9, {{spsr_abt|SPSR_ABT}} +# CHECK: mrs x9, {{spsr_und|SPSR_UND}} +# CHECK: mrs x9, {{spsr_fiq|SPSR_FIQ}} +# CHECK: mrs x9, {{fpcr|FPCR}} +# CHECK: mrs x9, {{fpsr|FPSR}} +# CHECK: mrs x9, {{dspsr_el0|DSPSR_EL0}} +# CHECK: mrs x9, {{dlr_el0|DLR_EL0}} +# CHECK: mrs x9, {{ifsr32_el2|IFSR32_EL2}} +# CHECK: mrs x9, {{afsr0_el1|AFSR0_EL1}} +# CHECK: mrs x9, {{afsr0_el2|AFSR0_EL2}} +# CHECK: mrs x9, {{afsr0_el3|AFSR0_EL3}} +# CHECK: mrs x9, {{afsr1_el1|AFSR1_EL1}} +# CHECK: mrs x9, {{afsr1_el2|AFSR1_EL2}} +# CHECK: mrs x9, {{afsr1_el3|AFSR1_EL3}} +# CHECK: mrs x9, {{esr_el1|ESR_EL1}} +# CHECK: mrs x9, {{esr_el2|ESR_EL2}} +# CHECK: mrs x9, {{esr_el3|ESR_EL3}} +# CHECK: mrs x9, {{fpexc32_el2|FPEXC32_EL2}} +# CHECK: mrs x9, {{far_el1|FAR_EL1}} +# CHECK: mrs x9, {{far_el2|FAR_EL2}} +# CHECK: mrs x9, {{far_el3|FAR_EL3}} +# CHECK: mrs x9, {{hpfar_el2|HPFAR_EL2}} +# CHECK: mrs x9, {{par_el1|PAR_EL1}} +# CHECK: mrs x9, {{pmcr_el0|PMCR_EL0}} +# CHECK: mrs x9, {{pmcntenset_el0|PMCNTENSET_EL0}} +# CHECK: mrs x9, {{pmcntenclr_el0|PMCNTENCLR_EL0}} +# CHECK: mrs x9, {{pmovsclr_el0|PMOVSCLR_EL0}} +# CHECK: mrs x9, {{pmselr_el0|PMSELR_EL0}} +# CHECK: mrs x9, {{pmceid0_el0|PMCEID0_EL0}} +# CHECK: mrs x9, {{pmceid1_el0|PMCEID1_EL0}} +# CHECK: mrs x9, {{pmccntr_el0|PMCCNTR_EL0}} +# CHECK: mrs x9, {{pmxevtyper_el0|PMXEVTYPER_EL0}} +# CHECK: mrs x9, {{pmxevcntr_el0|PMXEVCNTR_EL0}} +# CHECK: mrs x9, {{pmuserenr_el0|PMUSERENR_EL0}} +# CHECK: mrs x9, {{pmintenset_el1|PMINTENSET_EL1}} +# CHECK: mrs x9, {{pmintenclr_el1|PMINTENCLR_EL1}} +# CHECK: mrs x9, {{pmovsset_el0|PMOVSSET_EL0}} +# CHECK: mrs x9, {{mair_el1|MAIR_EL1}} +# CHECK: mrs x9, {{mair_el2|MAIR_EL2}} +# CHECK: mrs x9, {{mair_el3|MAIR_EL3}} +# CHECK: mrs x9, {{amair_el1|AMAIR_EL1}} +# CHECK: mrs x9, {{amair_el2|AMAIR_EL2}} +# CHECK: mrs x9, {{amair_el3|AMAIR_EL3}} +# CHECK: mrs x9, {{vbar_el1|VBAR_EL1}} +# CHECK: mrs x9, {{vbar_el2|VBAR_EL2}} +# CHECK: mrs x9, {{vbar_el3|VBAR_EL3}} +# CHECK: mrs x9, {{rvbar_el1|RVBAR_EL1}} +# CHECK: mrs x9, {{rvbar_el2|RVBAR_EL2}} +# CHECK: mrs x9, {{rvbar_el3|RVBAR_EL3}} +# CHECK: mrs x9, {{rmr_el1|RMR_EL1}} +# CHECK: mrs x9, {{rmr_el2|RMR_EL2}} +# CHECK: mrs x9, {{rmr_el3|RMR_EL3}} +# CHECK: mrs x9, {{isr_el1|ISR_EL1}} +# CHECK: mrs x9, {{contextidr_el1|CONTEXTIDR_EL1}} +# CHECK: mrs x9, {{tpidr_el0|TPIDR_EL0}} +# CHECK: mrs x9, {{tpidr_el2|TPIDR_EL2}} +# CHECK: mrs x9, {{tpidr_el3|TPIDR_EL3}} +# CHECK: mrs x9, {{tpidrro_el0|TPIDRRO_EL0}} +# CHECK: mrs x9, {{tpidr_el1|TPIDR_EL1}} +# CHECK: mrs x9, {{cntfrq_el0|CNTFRQ_EL0}} +# CHECK: mrs x9, {{cntpct_el0|CNTPCT_EL0}} +# CHECK: mrs x9, {{cntvct_el0|CNTVCT_EL0}} +# CHECK: mrs x9, {{cntvoff_el2|CNTVOFF_EL2}} +# CHECK: mrs x9, {{cntkctl_el1|CNTKCTL_EL1}} +# CHECK: mrs x9, {{cnthctl_el2|CNTHCTL_EL2}} +# CHECK: mrs x9, {{cntp_tval_el0|CNTP_TVAL_EL0}} +# CHECK: mrs x9, {{cnthp_tval_el2|CNTHP_TVAL_EL2}} +# CHECK: mrs x9, {{cntps_tval_el1|CNTPS_TVAL_EL1}} +# CHECK: mrs x9, {{cntp_ctl_el0|CNTP_CTL_EL0}} +# CHECK: mrs x9, {{cnthp_ctl_el2|CNTHP_CTL_EL2}} +# CHECK: mrs x9, {{cntps_ctl_el1|CNTPS_CTL_EL1}} +# CHECK: mrs x9, {{cntp_cval_el0|CNTP_CVAL_EL0}} +# CHECK: mrs x9, {{cnthp_cval_el2|CNTHP_CVAL_EL2}} +# CHECK: mrs x9, {{cntps_cval_el1|CNTPS_CVAL_EL1}} +# CHECK: mrs x9, {{cntv_tval_el0|CNTV_TVAL_EL0}} +# CHECK: mrs x9, {{cntv_ctl_el0|CNTV_CTL_EL0}} +# CHECK: mrs x9, {{cntv_cval_el0|CNTV_CVAL_EL0}} +# CHECK: mrs x9, {{pmevcntr0_el0|PMEVCNTR0_EL0}} +# CHECK: mrs x9, {{pmevcntr1_el0|PMEVCNTR1_EL0}} +# CHECK: mrs x9, {{pmevcntr2_el0|PMEVCNTR2_EL0}} +# CHECK: mrs x9, {{pmevcntr3_el0|PMEVCNTR3_EL0}} +# CHECK: mrs x9, {{pmevcntr4_el0|PMEVCNTR4_EL0}} +# CHECK: mrs x9, {{pmevcntr5_el0|PMEVCNTR5_EL0}} +# CHECK: mrs x9, {{pmevcntr6_el0|PMEVCNTR6_EL0}} +# CHECK: mrs x9, {{pmevcntr7_el0|PMEVCNTR7_EL0}} +# CHECK: mrs x9, {{pmevcntr8_el0|PMEVCNTR8_EL0}} +# CHECK: mrs x9, {{pmevcntr9_el0|PMEVCNTR9_EL0}} +# CHECK: mrs x9, {{pmevcntr10_el0|PMEVCNTR10_EL0}} +# CHECK: mrs x9, {{pmevcntr11_el0|PMEVCNTR11_EL0}} +# CHECK: mrs x9, {{pmevcntr12_el0|PMEVCNTR12_EL0}} +# CHECK: mrs x9, {{pmevcntr13_el0|PMEVCNTR13_EL0}} +# CHECK: mrs x9, {{pmevcntr14_el0|PMEVCNTR14_EL0}} +# CHECK: mrs x9, {{pmevcntr15_el0|PMEVCNTR15_EL0}} +# CHECK: mrs x9, {{pmevcntr16_el0|PMEVCNTR16_EL0}} +# CHECK: mrs x9, {{pmevcntr17_el0|PMEVCNTR17_EL0}} +# CHECK: mrs x9, {{pmevcntr18_el0|PMEVCNTR18_EL0}} +# CHECK: mrs x9, {{pmevcntr19_el0|PMEVCNTR19_EL0}} +# CHECK: mrs x9, {{pmevcntr20_el0|PMEVCNTR20_EL0}} +# CHECK: mrs x9, {{pmevcntr21_el0|PMEVCNTR21_EL0}} +# CHECK: mrs x9, {{pmevcntr22_el0|PMEVCNTR22_EL0}} +# CHECK: mrs x9, {{pmevcntr23_el0|PMEVCNTR23_EL0}} +# CHECK: mrs x9, {{pmevcntr24_el0|PMEVCNTR24_EL0}} +# CHECK: mrs x9, {{pmevcntr25_el0|PMEVCNTR25_EL0}} +# CHECK: mrs x9, {{pmevcntr26_el0|PMEVCNTR26_EL0}} +# CHECK: mrs x9, {{pmevcntr27_el0|PMEVCNTR27_EL0}} +# CHECK: mrs x9, {{pmevcntr28_el0|PMEVCNTR28_EL0}} +# CHECK: mrs x9, {{pmevcntr29_el0|PMEVCNTR29_EL0}} +# CHECK: mrs x9, {{pmevcntr30_el0|PMEVCNTR30_EL0}} +# CHECK: mrs x9, {{pmccfiltr_el0|PMCCFILTR_EL0}} +# CHECK: mrs x9, {{pmevtyper0_el0|PMEVTYPER0_EL0}} +# CHECK: mrs x9, {{pmevtyper1_el0|PMEVTYPER1_EL0}} +# CHECK: mrs x9, {{pmevtyper2_el0|PMEVTYPER2_EL0}} +# CHECK: mrs x9, {{pmevtyper3_el0|PMEVTYPER3_EL0}} +# CHECK: mrs x9, {{pmevtyper4_el0|PMEVTYPER4_EL0}} +# CHECK: mrs x9, {{pmevtyper5_el0|PMEVTYPER5_EL0}} +# CHECK: mrs x9, {{pmevtyper6_el0|PMEVTYPER6_EL0}} +# CHECK: mrs x9, {{pmevtyper7_el0|PMEVTYPER7_EL0}} +# CHECK: mrs x9, {{pmevtyper8_el0|PMEVTYPER8_EL0}} +# CHECK: mrs x9, {{pmevtyper9_el0|PMEVTYPER9_EL0}} +# CHECK: mrs x9, {{pmevtyper10_el0|PMEVTYPER10_EL0}} +# CHECK: mrs x9, {{pmevtyper11_el0|PMEVTYPER11_EL0}} +# CHECK: mrs x9, {{pmevtyper12_el0|PMEVTYPER12_EL0}} +# CHECK: mrs x9, {{pmevtyper13_el0|PMEVTYPER13_EL0}} +# CHECK: mrs x9, {{pmevtyper14_el0|PMEVTYPER14_EL0}} +# CHECK: mrs x9, {{pmevtyper15_el0|PMEVTYPER15_EL0}} +# CHECK: mrs x9, {{pmevtyper16_el0|PMEVTYPER16_EL0}} +# CHECK: mrs x9, {{pmevtyper17_el0|PMEVTYPER17_EL0}} +# CHECK: mrs x9, {{pmevtyper18_el0|PMEVTYPER18_EL0}} +# CHECK: mrs x9, {{pmevtyper19_el0|PMEVTYPER19_EL0}} +# CHECK: mrs x9, {{pmevtyper20_el0|PMEVTYPER20_EL0}} +# CHECK: mrs x9, {{pmevtyper21_el0|PMEVTYPER21_EL0}} +# CHECK: mrs x9, {{pmevtyper22_el0|PMEVTYPER22_EL0}} +# CHECK: mrs x9, {{pmevtyper23_el0|PMEVTYPER23_EL0}} +# CHECK: mrs x9, {{pmevtyper24_el0|PMEVTYPER24_EL0}} +# CHECK: mrs x9, {{pmevtyper25_el0|PMEVTYPER25_EL0}} +# CHECK: mrs x9, {{pmevtyper26_el0|PMEVTYPER26_EL0}} +# CHECK: mrs x9, {{pmevtyper27_el0|PMEVTYPER27_EL0}} +# CHECK: mrs x9, {{pmevtyper28_el0|PMEVTYPER28_EL0}} +# CHECK: mrs x9, {{pmevtyper29_el0|PMEVTYPER29_EL0}} +# CHECK: mrs x9, {{pmevtyper30_el0|PMEVTYPER30_EL0}} 0xc 0x0 0x12 0xd5 0x4c 0x0 0x10 0xd5 @@ -4147,10 +4148,10 @@ 0xa9 0xef 0x3b 0xd5 0xc9 0xef 0x3b 0xd5 -# CHECK: mrs x12, s3_7_c15_c1_5 -# CHECK: mrs x13, s3_2_c11_c15_7 -# CHECK: msr s3_0_c15_c0_0, x12 -# CHECK: msr s3_7_c11_c13_7, x5 +# CHECK: mrs x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}} +# CHECK: mrs x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}} +# CHECK: msr {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12 +# CHECK: msr {{s3_7_c11_c13_7|S3_7_C11_C13_7}}, x5 0xac 0xf1 0x3f 0xd5 0xed 0xbf 0x3a 0xd5 0x0c 0xf0 0x18 0xd5 diff --git a/test/MC/Disassembler/AArch64/basic-a64-undefined.txt b/test/MC/Disassembler/AArch64/basic-a64-undefined.txt index a17579c..968a454 100644 --- a/test/MC/Disassembler/AArch64/basic-a64-undefined.txt +++ b/test/MC/Disassembler/AArch64/basic-a64-undefined.txt @@ -1,43 +1,66 @@ -# These spawn another process so they're rather expensive. Not many. +# RUN: not llvm-mc -disassemble -triple=aarch64 %s 2> %t +# RUN: FileCheck %s < %t +# RUN: not llvm-mc -disassemble -triple=arm64 %s 2> %t +# RUN: FileCheck %s < %t # Instructions notionally in the add/sub (extended register) sheet, but with # invalid shift amount or "opt" field. -# RUN: echo "0x00 0x10 0xa0 0x0b" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x00 0x10 0x60 0x0b" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x00 0x14 0x20 0x0b" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0x00 0x10 0xa0 0x0b] +[0x00 0x10 0x60 0x0b] +[0x00 0x14 0x20 0x0b] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding # Instructions notionally in the add/sub (immediate) sheet, but with # invalid "shift" field. -# RUN: echo "0xdf 0x3 0x80 0x91" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0xed 0x8e 0xc4 0x31" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x62 0xfc 0xbf 0x11" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x3 0xff 0xff 0x91" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0xdf 0x3 0x80 0x91] +[0xed 0x8e 0xc4 0x31] +[0x62 0xfc 0xbf 0x11] +[0x3 0xff 0xff 0x91] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding # Instructions notionally in the load/store (unsigned immediate) sheet. # Only unallocated (int-register) variants are: opc=0b11, size=0b10, 0b11 -# RUN: echo "0xd7 0xfc 0xff 0xb9" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0xd7 0xfc 0xcf 0xf9" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0xd7 0xfc 0xff 0xb9] +[0xd7 0xfc 0xcf 0xf9] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding # Instructions notionally in the floating-point <-> fixed-point conversion # Scale field is 64-<imm> and <imm> should be 1-32 for a 32-bit int register. -# RUN: echo "0x23 0x01 0x18 0x1e" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x23 0x25 0x42 0x1e" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0x23 0x01 0x18 0x1e] +[0x23 0x25 0x42 0x1e] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding # Instructions notionally in the logical (shifted register) sheet, but with out # of range shift: w-registers can only have 0-31. -# RUN: echo "0x00 0x80 0x00 0x0a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0x00 0x80 0x00 0x0a] +# CHECK: invalid instruction encoding # Instructions notionally in the move wide (immediate) sheet, but with out # of range shift: w-registers can only have 0 or 16. -# RUN: echo "0x00 0x00 0xc0 0x12" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x12 0x34 0xe0 0x52" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s - -# Data-processing instructions are undefined when S=1 and for the 0b0000111 value in opcode:sf -# RUN: echo "0x00 0x00 0xc0 0x5f" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x56 0x0c 0xc0 0x5a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0x00 0x00 0xc0 0x12] +[0x12 0x34 0xe0 0x52] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding -# Data-processing instructions (2 source) are undefined for a value of 0001xx:0:x or 0011xx:0:x for opcode:S:sf -# RUN: echo "0x00 0x30 0xc1 0x1a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x00 0x10 0xc1 0x1a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +# Data-processing instructions are undefined when S=1 and for the 0b0000111 +# value in opcode:sf +[0x00 0x00 0xc0 0x5f] +[0x56 0x0c 0xc0 0x5a] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding +# Data-processing instructions (2 source) are undefined for a value of +# 0001xx:0:x or 0011xx:0:x for opcode:S:sf +[0x00 0x30 0xc1 0x1a] +[0x00 0x10 0xc1 0x1a] +# CHECK: invalid instruction encoding # CHECK: invalid instruction encoding + + diff --git a/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt b/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt index 5363863..2fccccb 100644 --- a/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt +++ b/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s #------------------------------------------------------------------------------ # Load-store exclusive diff --git a/test/MC/Disassembler/AArch64/gicv3-regs.txt b/test/MC/Disassembler/AArch64/gicv3-regs.txt index 4351f64..851e83d 100644 --- a/test/MC/Disassembler/AArch64/gicv3-regs.txt +++ b/test/MC/Disassembler/AArch64/gicv3-regs.txt @@ -1,222 +1,223 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-none-linux-gnu -disassemble < %s | FileCheck %s 0x8 0xcc 0x38 0xd5 -# CHECK: mrs x8, icc_iar1_el1 +# CHECK: mrs x8, {{icc_iar1_el1|ICC_IAR1_EL1}} 0x1a 0xc8 0x38 0xd5 -# CHECK: mrs x26, icc_iar0_el1 +# CHECK: mrs x26, {{icc_iar0_el1|ICC_IAR0_EL1}} 0x42 0xcc 0x38 0xd5 -# CHECK: mrs x2, icc_hppir1_el1 +# CHECK: mrs x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}} 0x51 0xc8 0x38 0xd5 -# CHECK: mrs x17, icc_hppir0_el1 +# CHECK: mrs x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}} 0x7d 0xcb 0x38 0xd5 -# CHECK: mrs x29, icc_rpr_el1 +# CHECK: mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}} 0x24 0xcb 0x3c 0xd5 -# CHECK: mrs x4, ich_vtr_el2 +# CHECK: mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}} 0x78 0xcb 0x3c 0xd5 -# CHECK: mrs x24, ich_eisr_el2 +# CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}} 0xa9 0xcb 0x3c 0xd5 -# CHECK: mrs x9, ich_elsr_el2 +# CHECK: mrs x9, {{ich_elsr_el2|ICH_ELSR_EL2}} 0x78 0xcc 0x38 0xd5 -# CHECK: mrs x24, icc_bpr1_el1 +# CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}} 0x6e 0xc8 0x38 0xd5 -# CHECK: mrs x14, icc_bpr0_el1 +# CHECK: mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}} 0x13 0x46 0x38 0xd5 -# CHECK: mrs x19, icc_pmr_el1 +# CHECK: mrs x19, {{icc_pmr_el1|ICC_PMR_EL1}} 0x97 0xcc 0x38 0xd5 -# CHECK: mrs x23, icc_ctlr_el1 +# CHECK: mrs x23, {{icc_ctlr_el1|ICC_CTLR_EL1}} 0x94 0xcc 0x3e 0xd5 -# CHECK: mrs x20, icc_ctlr_el3 +# CHECK: mrs x20, {{icc_ctlr_el3|ICC_CTLR_EL3}} 0xbc 0xcc 0x38 0xd5 -# CHECK: mrs x28, icc_sre_el1 +# CHECK: mrs x28, {{icc_sre_el1|ICC_SRE_EL1}} 0xb9 0xc9 0x3c 0xd5 -# CHECK: mrs x25, icc_sre_el2 +# CHECK: mrs x25, {{icc_sre_el2|ICC_SRE_EL2}} 0xa8 0xcc 0x3e 0xd5 -# CHECK: mrs x8, icc_sre_el3 +# CHECK: mrs x8, {{icc_sre_el3|ICC_SRE_EL3}} 0xd6 0xcc 0x38 0xd5 -# CHECK: mrs x22, icc_igrpen0_el1 +# CHECK: mrs x22, {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}} 0xe5 0xcc 0x38 0xd5 -# CHECK: mrs x5, icc_igrpen1_el1 +# CHECK: mrs x5, {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}} 0xe7 0xcc 0x3e 0xd5 -# CHECK: mrs x7, icc_igrpen1_el3 +# CHECK: mrs x7, {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}} 0x16 0xcd 0x38 0xd5 -# CHECK: mrs x22, icc_seien_el1 +# CHECK: mrs x22, {{icc_seien_el1|ICC_SEIEN_EL1}} 0x84 0xc8 0x38 0xd5 -# CHECK: mrs x4, icc_ap0r0_el1 +# CHECK: mrs x4, {{icc_ap0r0_el1|ICC_AP0R0_EL1}} 0xab 0xc8 0x38 0xd5 -# CHECK: mrs x11, icc_ap0r1_el1 +# CHECK: mrs x11, {{icc_ap0r1_el1|ICC_AP0R1_EL1}} 0xdb 0xc8 0x38 0xd5 -# CHECK: mrs x27, icc_ap0r2_el1 +# CHECK: mrs x27, {{icc_ap0r2_el1|ICC_AP0R2_EL1}} 0xf5 0xc8 0x38 0xd5 -# CHECK: mrs x21, icc_ap0r3_el1 +# CHECK: mrs x21, {{icc_ap0r3_el1|ICC_AP0R3_EL1}} 0x2 0xc9 0x38 0xd5 -# CHECK: mrs x2, icc_ap1r0_el1 +# CHECK: mrs x2, {{icc_ap1r0_el1|ICC_AP1R0_EL1}} 0x35 0xc9 0x38 0xd5 -# CHECK: mrs x21, icc_ap1r1_el1 +# CHECK: mrs x21, {{icc_ap1r1_el1|ICC_AP1R1_EL1}} 0x4a 0xc9 0x38 0xd5 -# CHECK: mrs x10, icc_ap1r2_el1 +# CHECK: mrs x10, {{icc_ap1r2_el1|ICC_AP1R2_EL1}} 0x7b 0xc9 0x38 0xd5 -# CHECK: mrs x27, icc_ap1r3_el1 +# CHECK: mrs x27, {{icc_ap1r3_el1|ICC_AP1R3_EL1}} 0x14 0xc8 0x3c 0xd5 -# CHECK: mrs x20, ich_ap0r0_el2 +# CHECK: mrs x20, {{ich_ap0r0_el2|ICH_AP0R0_EL2}} 0x35 0xc8 0x3c 0xd5 -# CHECK: mrs x21, ich_ap0r1_el2 +# CHECK: mrs x21, {{ich_ap0r1_el2|ICH_AP0R1_EL2}} 0x45 0xc8 0x3c 0xd5 -# CHECK: mrs x5, ich_ap0r2_el2 +# CHECK: mrs x5, {{ich_ap0r2_el2|ICH_AP0R2_EL2}} 0x64 0xc8 0x3c 0xd5 -# CHECK: mrs x4, ich_ap0r3_el2 +# CHECK: mrs x4, {{ich_ap0r3_el2|ICH_AP0R3_EL2}} 0xf 0xc9 0x3c 0xd5 -# CHECK: mrs x15, ich_ap1r0_el2 +# CHECK: mrs x15, {{ich_ap1r0_el2|ICH_AP1R0_EL2}} 0x2c 0xc9 0x3c 0xd5 -# CHECK: mrs x12, ich_ap1r1_el2 +# CHECK: mrs x12, {{ich_ap1r1_el2|ICH_AP1R1_EL2}} 0x5b 0xc9 0x3c 0xd5 -# CHECK: mrs x27, ich_ap1r2_el2 +# CHECK: mrs x27, {{ich_ap1r2_el2|ICH_AP1R2_EL2}} 0x74 0xc9 0x3c 0xd5 -# CHECK: mrs x20, ich_ap1r3_el2 +# CHECK: mrs x20, {{ich_ap1r3_el2|ICH_AP1R3_EL2}} 0xa 0xcb 0x3c 0xd5 -# CHECK: mrs x10, ich_hcr_el2 +# CHECK: mrs x10, {{ich_hcr_el2|ICH_HCR_EL2}} 0x5b 0xcb 0x3c 0xd5 -# CHECK: mrs x27, ich_misr_el2 +# CHECK: mrs x27, {{ich_misr_el2|ICH_MISR_EL2}} 0xe6 0xcb 0x3c 0xd5 -# CHECK: mrs x6, ich_vmcr_el2 +# CHECK: mrs x6, {{ich_vmcr_el2|ICH_VMCR_EL2}} 0x93 0xc9 0x3c 0xd5 -# CHECK: mrs x19, ich_vseir_el2 +# CHECK: mrs x19, {{ich_vseir_el2|ICH_VSEIR_EL2}} 0x3 0xcc 0x3c 0xd5 -# CHECK: mrs x3, ich_lr0_el2 +# CHECK: mrs x3, {{ich_lr0_el2|ICH_LR0_EL2}} 0x21 0xcc 0x3c 0xd5 -# CHECK: mrs x1, ich_lr1_el2 +# CHECK: mrs x1, {{ich_lr1_el2|ICH_LR1_EL2}} 0x56 0xcc 0x3c 0xd5 -# CHECK: mrs x22, ich_lr2_el2 +# CHECK: mrs x22, {{ich_lr2_el2|ICH_LR2_EL2}} 0x75 0xcc 0x3c 0xd5 -# CHECK: mrs x21, ich_lr3_el2 +# CHECK: mrs x21, {{ich_lr3_el2|ICH_LR3_EL2}} 0x86 0xcc 0x3c 0xd5 -# CHECK: mrs x6, ich_lr4_el2 +# CHECK: mrs x6, {{ich_lr4_el2|ICH_LR4_EL2}} 0xaa 0xcc 0x3c 0xd5 -# CHECK: mrs x10, ich_lr5_el2 +# CHECK: mrs x10, {{ich_lr5_el2|ICH_LR5_EL2}} 0xcb 0xcc 0x3c 0xd5 -# CHECK: mrs x11, ich_lr6_el2 +# CHECK: mrs x11, {{ich_lr6_el2|ICH_LR6_EL2}} 0xec 0xcc 0x3c 0xd5 -# CHECK: mrs x12, ich_lr7_el2 +# CHECK: mrs x12, {{ich_lr7_el2|ICH_LR7_EL2}} 0x0 0xcd 0x3c 0xd5 -# CHECK: mrs x0, ich_lr8_el2 +# CHECK: mrs x0, {{ich_lr8_el2|ICH_LR8_EL2}} 0x35 0xcd 0x3c 0xd5 -# CHECK: mrs x21, ich_lr9_el2 +# CHECK: mrs x21, {{ich_lr9_el2|ICH_LR9_EL2}} 0x4d 0xcd 0x3c 0xd5 -# CHECK: mrs x13, ich_lr10_el2 +# CHECK: mrs x13, {{ich_lr10_el2|ICH_LR10_EL2}} 0x7a 0xcd 0x3c 0xd5 -# CHECK: mrs x26, ich_lr11_el2 +# CHECK: mrs x26, {{ich_lr11_el2|ICH_LR11_EL2}} 0x81 0xcd 0x3c 0xd5 -# CHECK: mrs x1, ich_lr12_el2 +# CHECK: mrs x1, {{ich_lr12_el2|ICH_LR12_EL2}} 0xa8 0xcd 0x3c 0xd5 -# CHECK: mrs x8, ich_lr13_el2 +# CHECK: mrs x8, {{ich_lr13_el2|ICH_LR13_EL2}} 0xc2 0xcd 0x3c 0xd5 -# CHECK: mrs x2, ich_lr14_el2 +# CHECK: mrs x2, {{ich_lr14_el2|ICH_LR14_EL2}} 0xe8 0xcd 0x3c 0xd5 -# CHECK: mrs x8, ich_lr15_el2 +# CHECK: mrs x8, {{ich_lr15_el2|ICH_LR15_EL2}} 0x3b 0xcc 0x18 0xd5 -# CHECK: msr icc_eoir1_el1, x27 +# CHECK: msr {{icc_eoir1_el1|ICC_EOIR1_EL1}}, x27 0x25 0xc8 0x18 0xd5 -# CHECK: msr icc_eoir0_el1, x5 +# CHECK: msr {{icc_eoir0_el1|ICC_EOIR0_EL1}}, x5 0x2d 0xcb 0x18 0xd5 -# CHECK: msr icc_dir_el1, x13 +# CHECK: msr {{icc_dir_el1|ICC_DIR_EL1}}, x13 0xb5 0xcb 0x18 0xd5 -# CHECK: msr icc_sgi1r_el1, x21 +# CHECK: msr {{icc_sgi1r_el1|ICC_SGI1R_EL1}}, x21 0xd9 0xcb 0x18 0xd5 -# CHECK: msr icc_asgi1r_el1, x25 +# CHECK: msr {{icc_asgi1r_el1|ICC_ASGI1R_EL1}}, x25 0xfc 0xcb 0x18 0xd5 -# CHECK: msr icc_sgi0r_el1, x28 +# CHECK: msr {{icc_sgi0r_el1|ICC_SGI0R_EL1}}, x28 0x67 0xcc 0x18 0xd5 -# CHECK: msr icc_bpr1_el1, x7 +# CHECK: msr {{icc_bpr1_el1|ICC_BPR1_EL1}}, x7 0x69 0xc8 0x18 0xd5 -# CHECK: msr icc_bpr0_el1, x9 +# CHECK: msr {{icc_bpr0_el1|ICC_BPR0_EL1}}, x9 0x1d 0x46 0x18 0xd5 -# CHECK: msr icc_pmr_el1, x29 +# CHECK: msr {{icc_pmr_el1|ICC_PMR_EL1}}, x29 0x98 0xcc 0x18 0xd5 -# CHECK: msr icc_ctlr_el1, x24 +# CHECK: msr {{icc_ctlr_el1|ICC_CTLR_EL1}}, x24 0x80 0xcc 0x1e 0xd5 -# CHECK: msr icc_ctlr_el3, x0 +# CHECK: msr {{icc_ctlr_el3|ICC_CTLR_EL3}}, x0 0xa2 0xcc 0x18 0xd5 -# CHECK: msr icc_sre_el1, x2 +# CHECK: msr {{icc_sre_el1|ICC_SRE_EL1}}, x2 0xa5 0xc9 0x1c 0xd5 -# CHECK: msr icc_sre_el2, x5 +# CHECK: msr {{icc_sre_el2|ICC_SRE_EL2}}, x5 0xaa 0xcc 0x1e 0xd5 -# CHECK: msr icc_sre_el3, x10 +# CHECK: msr {{icc_sre_el3|ICC_SRE_EL3}}, x10 0xd6 0xcc 0x18 0xd5 -# CHECK: msr icc_igrpen0_el1, x22 +# CHECK: msr {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x22 0xeb 0xcc 0x18 0xd5 -# CHECK: msr icc_igrpen1_el1, x11 +# CHECK: msr {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}, x11 0xe8 0xcc 0x1e 0xd5 -# CHECK: msr icc_igrpen1_el3, x8 +# CHECK: msr {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}, x8 0x4 0xcd 0x18 0xd5 -# CHECK: msr icc_seien_el1, x4 +# CHECK: msr {{icc_seien_el1|ICC_SEIEN_EL1}}, x4 0x9b 0xc8 0x18 0xd5 -# CHECK: msr icc_ap0r0_el1, x27 +# CHECK: msr {{icc_ap0r0_el1|ICC_AP0R0_EL1}}, x27 0xa5 0xc8 0x18 0xd5 -# CHECK: msr icc_ap0r1_el1, x5 +# CHECK: msr {{icc_ap0r1_el1|ICC_AP0R1_EL1}}, x5 0xd4 0xc8 0x18 0xd5 -# CHECK: msr icc_ap0r2_el1, x20 +# CHECK: msr {{icc_ap0r2_el1|ICC_AP0R2_EL1}}, x20 0xe0 0xc8 0x18 0xd5 -# CHECK: msr icc_ap0r3_el1, x0 +# CHECK: msr {{icc_ap0r3_el1|ICC_AP0R3_EL1}}, x0 0x2 0xc9 0x18 0xd5 -# CHECK: msr icc_ap1r0_el1, x2 +# CHECK: msr {{icc_ap1r0_el1|ICC_AP1R0_EL1}}, x2 0x3d 0xc9 0x18 0xd5 -# CHECK: msr icc_ap1r1_el1, x29 +# CHECK: msr {{icc_ap1r1_el1|ICC_AP1R1_EL1}}, x29 0x57 0xc9 0x18 0xd5 -# CHECK: msr icc_ap1r2_el1, x23 +# CHECK: msr {{icc_ap1r2_el1|ICC_AP1R2_EL1}}, x23 0x6b 0xc9 0x18 0xd5 -# CHECK: msr icc_ap1r3_el1, x11 +# CHECK: msr {{icc_ap1r3_el1|ICC_AP1R3_EL1}}, x11 0x2 0xc8 0x1c 0xd5 -# CHECK: msr ich_ap0r0_el2, x2 +# CHECK: msr {{ich_ap0r0_el2|ICH_AP0R0_EL2}}, x2 0x3b 0xc8 0x1c 0xd5 -# CHECK: msr ich_ap0r1_el2, x27 +# CHECK: msr {{ich_ap0r1_el2|ICH_AP0R1_EL2}}, x27 0x47 0xc8 0x1c 0xd5 -# CHECK: msr ich_ap0r2_el2, x7 +# CHECK: msr {{ich_ap0r2_el2|ICH_AP0R2_EL2}}, x7 0x61 0xc8 0x1c 0xd5 -# CHECK: msr ich_ap0r3_el2, x1 +# CHECK: msr {{ich_ap0r3_el2|ICH_AP0R3_EL2}}, x1 0x7 0xc9 0x1c 0xd5 -# CHECK: msr ich_ap1r0_el2, x7 +# CHECK: msr {{ich_ap1r0_el2|ICH_AP1R0_EL2}}, x7 0x2c 0xc9 0x1c 0xd5 -# CHECK: msr ich_ap1r1_el2, x12 +# CHECK: msr {{ich_ap1r1_el2|ICH_AP1R1_EL2}}, x12 0x4e 0xc9 0x1c 0xd5 -# CHECK: msr ich_ap1r2_el2, x14 +# CHECK: msr {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x14 0x6d 0xc9 0x1c 0xd5 -# CHECK: msr ich_ap1r3_el2, x13 +# CHECK: msr {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x13 0x1 0xcb 0x1c 0xd5 -# CHECK: msr ich_hcr_el2, x1 +# CHECK: msr {{ich_hcr_el2|ICH_HCR_EL2}}, x1 0x4a 0xcb 0x1c 0xd5 -# CHECK: msr ich_misr_el2, x10 +# CHECK: msr {{ich_misr_el2|ICH_MISR_EL2}}, x10 0xf8 0xcb 0x1c 0xd5 -# CHECK: msr ich_vmcr_el2, x24 +# CHECK: msr {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24 0x9d 0xc9 0x1c 0xd5 -# CHECK: msr ich_vseir_el2, x29 +# CHECK: msr {{ich_vseir_el2|ICH_VSEIR_EL2}}, x29 0x1a 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr0_el2, x26 +# CHECK: msr {{ich_lr0_el2|ICH_LR0_EL2}}, x26 0x29 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr1_el2, x9 +# CHECK: msr {{ich_lr1_el2|ICH_LR1_EL2}}, x9 0x52 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr2_el2, x18 +# CHECK: msr {{ich_lr2_el2|ICH_LR2_EL2}}, x18 0x7a 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr3_el2, x26 +# CHECK: msr {{ich_lr3_el2|ICH_LR3_EL2}}, x26 0x96 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr4_el2, x22 +# CHECK: msr {{ich_lr4_el2|ICH_LR4_EL2}}, x22 0xba 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr5_el2, x26 +# CHECK: msr {{ich_lr5_el2|ICH_LR5_EL2}}, x26 0xdb 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr6_el2, x27 +# CHECK: msr {{ich_lr6_el2|ICH_LR6_EL2}}, x27 0xe8 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr7_el2, x8 +# CHECK: msr {{ich_lr7_el2|ICH_LR7_EL2}}, x8 0x11 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr8_el2, x17 +# CHECK: msr {{ich_lr8_el2|ICH_LR8_EL2}}, x17 0x33 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr9_el2, x19 +# CHECK: msr {{ich_lr9_el2|ICH_LR9_EL2}}, x19 0x51 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr10_el2, x17 +# CHECK: msr {{ich_lr10_el2|ICH_LR10_EL2}}, x17 0x65 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr11_el2, x5 +# CHECK: msr {{ich_lr11_el2|ICH_LR11_EL2}}, x5 0x9d 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr12_el2, x29 +# CHECK: msr {{ich_lr12_el2|ICH_LR12_EL2}}, x29 0xa2 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr13_el2, x2 +# CHECK: msr {{ich_lr13_el2|ICH_LR13_EL2}}, x2 0xcd 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr14_el2, x13 +# CHECK: msr {{ich_lr14_el2|ICH_LR14_EL2}}, x13 0xfb 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr15_el2, x27 +# CHECK: msr {{ich_lr15_el2|ICH_LR15_EL2}}, x27 diff --git a/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt b/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt index 7ff495f..3c443a9 100644 --- a/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt +++ b/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=arm64 -disassemble < %s 2>&1 | FileCheck %s # Stores are OK. 0xe0 0x83 0x00 0xa9 diff --git a/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt b/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt index 637ebdb..6ba33ad 100644 --- a/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt +++ b/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s # None of these instructions should be classified as unpredictable: diff --git a/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt b/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt index f52d37f..1915340 100644 --- a/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt +++ b/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s # None of these instructions should be classified as unpredictable: diff --git a/test/MC/Disassembler/AArch64/lit.local.cfg b/test/MC/Disassembler/AArch64/lit.local.cfg index 9a66a00..2c423d1 100644 --- a/test/MC/Disassembler/AArch64/lit.local.cfg +++ b/test/MC/Disassembler/AArch64/lit.local.cfg @@ -1,4 +1,4 @@ targets = set(config.root.targets_to_build.split()) -if not 'AArch64' in targets: +if 'AArch64' not in targets: config.unsupported = True diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt index 863730a..3590668 100644 --- a/test/MC/Disassembler/AArch64/neon-instructions.txt +++ b/test/MC/Disassembler/AArch64/neon-instructions.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # Vector Integer Add/Sub @@ -87,7 +88,7 @@ # Vector Bitwise OR - immedidate #------------------------------------------------------------------------------ # CHECK: movi v31.4s, #0xff, lsl #24 -# CHECK: mvni v0.2s, #0x0 +# CHECK: mvni v0.2s, #{{0x0|0}} # CHECK: bic v15.4h, #0xf, lsl #8 # CHECK: orr v16.8h, #0x1f 0xff 0x67 0x07 0x4f @@ -132,10 +133,8 @@ # Vector Move - register #------------------------------------------------------------------------------ -# FIXME: these should print as "mov", but TableGen can't handle it. - -# CHECK: orr v1.16b, v15.16b, v15.16b -# CHECK: orr v25.8b, v4.8b, v4.8b +# CHECK: mov v1.16b, v15.16b +# CHECK: mov v25.8b, v4.8b 0xe1 0x1d 0xaf 0x4e 0x99 0x1c 0xa4 0x0e @@ -246,31 +245,31 @@ #---------------------------------------------------------------------- # Vector Compare Mask Equal to Zero (Integer) #---------------------------------------------------------------------- -# CHECK: cmeq v31.16b, v15.16b, #0x0 +# CHECK: cmeq v31.16b, v15.16b, #{{0x0|0}} 0xff 0x99 0x20 0x4e #---------------------------------------------------------------------- # Vector Compare Mask Greater Than or Equal to Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmge v3.8b, v15.8b, #0x0 +# CHECK: cmge v3.8b, v15.8b, #{{0x0|0}} 0xe3 0x89 0x20 0x2e #---------------------------------------------------------------------- # Vector Compare Mask Greater Than Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmgt v22.2s, v9.2s, #0x0 +# CHECK: cmgt v22.2s, v9.2s, #{{0x0|0}} 0x36 0x89 0xa0 0x0e #---------------------------------------------------------------------- # Vector Compare Mask Less Than or Equal To Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmle v5.2d, v14.2d, #0x0 +# CHECK: cmle v5.2d, v14.2d, #{{0x0|0}} 0xc5 0x99 0xe0 0x6e #---------------------------------------------------------------------- # Vector Compare Mask Less Than Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmlt v13.8h, v11.8h, #0x0 +# CHECK: cmlt v13.8h, v11.8h, #{{0x0|0}} 0x6d 0xa9 0x60 0x4e #---------------------------------------------------------------------- @@ -1559,7 +1558,7 @@ #---------------------------------------------------------------------- # Scalar Compare Bitwise Equal To Zero #---------------------------------------------------------------------- -# CHECK: cmeq d20, d21, #0x0 +# CHECK: cmeq d20, d21, #{{0x0|0}} 0xb4,0x9a,0xe0,0x5e #---------------------------------------------------------------------- @@ -1578,7 +1577,7 @@ #---------------------------------------------------------------------- # Scalar Compare Signed Greather Than Or Equal To Zero #---------------------------------------------------------------------- -# CHECK: cmge d20, d21, #0x0 +# CHECK: cmge d20, d21, #{{0x0|0}} 0xb4,0x8a,0xe0,0x7e #---------------------------------------------------------------------- @@ -1596,19 +1595,19 @@ #---------------------------------------------------------------------- # Scalar Compare Signed Greater Than Zero #---------------------------------------------------------------------- -# CHECK: cmgt d20, d21, #0x0 +# CHECK: cmgt d20, d21, #{{0x0|0}} 0xb4,0x8a,0xe0,0x5e #---------------------------------------------------------------------- # Scalar Compare Signed Less Than Or Equal To Zero #---------------------------------------------------------------------- -# CHECK: cmle d20, d21, #0x0 +# CHECK: cmle d20, d21, #{{0x0|0}} 0xb4,0x9a,0xe0,0x7e #---------------------------------------------------------------------- # Scalar Compare Less Than Zero #---------------------------------------------------------------------- -# CHECK: cmlt d20, d21, #0x0 +# CHECK: cmlt d20, d21, #{{0x0|0}} 0xb4,0xaa,0xe0,0x5e #---------------------------------------------------------------------- @@ -2008,34 +2007,34 @@ #---------------------------------------------------------------------- # Vector load/store multiple N-element structure #---------------------------------------------------------------------- -# CHECK: ld1 {v0.16b}, [x0] -# CHECK: ld1 {v15.8h, v16.8h}, [x15] -# CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp] -# CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +# CHECK: ld1 { v0.16b }, [x0] +# CHECK: ld1 { v15.8h, v16.8h }, [x15] +# CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp] +# CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] 0x00,0x70,0x40,0x4c 0xef,0xa5,0x40,0x4c 0xff,0x6b,0x40,0x4c 0x00,0x2c,0x40,0x4c -# CHECK: ld2 {v0.8b, v1.8b}, [x0] -# CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15] -# CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +# CHECK: ld2 { v0.8b, v1.8b }, [x0] +# CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15] +# CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] 0x00,0x80,0x40,0x0c 0xef,0x45,0x40,0x0c 0xff,0x0b,0x40,0x0c -# CHECK: st1 {v0.16b}, [x0] -# CHECK: st1 {v15.8h, v16.8h}, [x15] -# CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp] -# CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +# CHECK: st1 { v0.16b }, [x0] +# CHECK: st1 { v15.8h, v16.8h }, [x15] +# CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp] +# CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] 0x00,0x70,0x00,0x4c 0xef,0xa5,0x00,0x4c 0xff,0x6b,0x00,0x4c 0x00,0x2c,0x00,0x4c -# CHECK: st2 {v0.8b, v1.8b}, [x0] -# CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15] -# CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +# CHECK: st2 { v0.8b, v1.8b }, [x0] +# CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15] +# CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] 0x00,0x80,0x00,0x0c 0xef,0x45,0x00,0x0c 0xff,0x0b,0x00,0x0c @@ -2043,35 +2042,35 @@ #---------------------------------------------------------------------- # Vector load/store multiple N-element structure (post-index) #---------------------------------------------------------------------- -# CHECK: ld1 {v15.8h}, [x15], x2 -# CHECK: ld1 {v31.4s, v0.4s}, [sp], #32 -# CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 -# CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +# CHECK: ld1 { v15.8h }, [x15], x2 +# CHECK: ld1 { v31.4s, v0.4s }, [sp], #32 +# CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +# CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 0xef,0x75,0xc2,0x4c 0xff,0xab,0xdf,0x4c 0x00,0x6c,0xdf,0x4c 0x00,0x20,0xc3,0x0c -# CHECK: ld2 {v0.16b, v1.16b}, [x0], x1 -# CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 -# CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +# CHECK: ld2 { v0.16b, v1.16b }, [x0], x1 +# CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2 +# CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 0x00,0x80,0xc1,0x4c 0xef,0x45,0xc2,0x4c 0xff,0x0b,0xdf,0x4c -# CHECK: st1 {v15.8h}, [x15], x2 -# CHECK: st1 {v31.4s, v0.4s}, [sp], #32 -# CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 -# CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +# CHECK: st1 { v15.8h }, [x15], x2 +# CHECK: st1 { v31.4s, v0.4s }, [sp], #32 +# CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +# CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 0xef,0x75,0x82,0x4c 0xff,0xab,0x9f,0x4c 0x00,0x6c,0x9f,0x4c 0x00,0x20,0x83,0x0c -# CHECK: st2 {v0.16b, v1.16b}, [x0], x1 -# CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 -# CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +# CHECK: st2 { v0.16b, v1.16b }, [x0], x1 +# CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15], x2 +# CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 0x00,0x80,0x81,0x4c 0xef,0x45,0x82,0x4c 0xff,0x0b,0x9f,0x4c @@ -2080,14 +2079,14 @@ # Vector load single N-element structure to all lane of N # consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1r {v0.16b}, [x0] -# CHECK: ld1r {v15.8h}, [x15] -# CHECK: ld2r {v31.4s, v0.4s}, [sp] -# CHECK: ld2r {v0.2d, v1.2d}, [x0] -# CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0] -# CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15] -# CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] -# CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp] +# CHECK: ld1r { v0.16b }, [x0] +# CHECK: ld1r { v15.8h }, [x15] +# CHECK: ld2r { v31.4s, v0.4s }, [sp] +# CHECK: ld2r { v0.2d, v1.2d }, [x0] +# CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0] +# CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15] +# CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] +# CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp] 0x00,0xc0,0x40,0x4d 0xef,0xc5,0x40,0x4d 0xff,0xcb,0x60,0x4d @@ -2101,14 +2100,14 @@ # Vector load/store single N-element structure to/from one lane of N # consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1 {v0.b}[9], [x0] -# CHECK: ld2 {v15.h, v16.h}[7], [x15] -# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp] -# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] -# CHECK: st1 {v0.d}[1], [x0] -# CHECK: st2 {v31.s, v0.s}[3], [sp] -# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15] -# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] +# CHECK: ld1 { v0.b }[9], [x0] +# CHECK: ld2 { v15.h, v16.h }[7], [x15] +# CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp] +# CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] +# CHECK: st1 { v0.d }[1], [x0] +# CHECK: st2 { v31.s, v0.s }[3], [sp] +# CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15] +# CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] 0x00,0x04,0x40,0x4d 0xef,0x59,0x60,0x4d 0xff,0xb3,0x40,0x4d @@ -2122,14 +2121,14 @@ # Post-index of vector load single N-element structure to all lane of N # consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1r {v0.16b}, [x0], #1 -# CHECK: ld1r {v15.8h}, [x15], #2 -# CHECK: ld2r {v31.4s, v0.4s}, [sp], #8 -# CHECK: ld2r {v0.2d, v1.2d}, [x0], #16 -# CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3 -# CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6 -# CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30 -# CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7 +# CHECK: ld1r { v0.16b }, [x0], #1 +# CHECK: ld1r { v15.8h }, [x15], #2 +# CHECK: ld2r { v31.4s, v0.4s }, [sp], #8 +# CHECK: ld2r { v0.2d, v1.2d }, [x0], #16 +# CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3 +# CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6 +# CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30 +# CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7 0x00,0xc0,0xdf,0x4d 0xef,0xc5,0xdf,0x4d 0xff,0xcb,0xff,0x4d @@ -2143,15 +2142,15 @@ # Post-index of vector load/store single N-element structure to/from # one lane of N consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1 {v0.b}[9], [x0], #1 -# CHECK: ld2 {v15.h, v16.h}[7], [x15], #4 -# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3 -# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 -# CHECK: ld4 {v0.h, v1.h, v2.h, v3.h}[7], [x0], x0 -# CHECK: st1 {v0.d}[1], [x0], #8 -# CHECK: st2 {v31.s, v0.s}[3], [sp], #8 -# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6 -# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 +# CHECK: ld1 { v0.b }[9], [x0], #1 +# CHECK: ld2 { v15.h, v16.h }[7], [x15], #4 +# CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp], x3 +# CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 +# CHECK: ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0 +# CHECK: st1 { v0.d }[1], [x0], #8 +# CHECK: st2 { v31.s, v0.s }[3], [sp], #8 +# CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15], #6 +# CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 0x00,0x04,0xdf,0x4d 0xef,0x59,0xff,0x4d 0xff,0xb3,0xc3,0x4d @@ -2167,8 +2166,8 @@ #---------------------------------------------------------------------- 0x20,0x18,0x02,0x2e 0x20,0x18,0x02,0x6e -# CHECK: ext v0.8b, v1.8b, v2.8b, #0x3 -# CHECK: ext v0.16b, v1.16b, v2.16b, #0x3 +# CHECK: ext v0.8b, v1.8b, v2.8b, #{{0x3|3}} +# CHECK: ext v0.16b, v1.16b, v2.16b, #{{0x3|3}} #---------------------------------------------------------------------- # unzip with 3 same vectors to get primary result @@ -2481,10 +2480,10 @@ #---------------------------------------------------------------------- #Duplicate element (scalar) #---------------------------------------------------------------------- -# CHECK: dup b0, v0.b[15] -# CHECK: dup h2, v31.h[5] -# CHECK: dup s17, v2.s[2] -# CHECK: dup d6, v12.d[1] +# CHECK: {{dup|mov}} b0, v0.b[15] +# CHECK: {{dup|mov}} h2, v31.h[5] +# CHECK: {{dup|mov}} s17, v2.s[2] +# CHECK: {{dup|mov}} d6, v12.d[1] 0x00 0x04 0x1f 0x5e 0xe2 0x07 0x16 0x5e 0x51 0x04 0x14 0x5e @@ -2497,37 +2496,37 @@ 0xf0,0x23,0x02,0x0e 0x20,0x40,0x02,0x0e 0xf0,0x62,0x02,0x0e -# CHECK: tbl v0.8b, {v1.16b}, v2.8b -# CHECK: tbl v16.8b, {v31.16b, v0.16b}, v2.8b -# CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b -# CHECK: tbl v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b +# CHECK: tbl v0.8b, { v1.16b }, v2.8b +# CHECK: tbl v16.8b, { v31.16b, v0.16b }, v2.8b +# CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b +# CHECK: tbl v16.8b, { v23.16b, v24.16b, v25.16b, v26.16b }, v2.8b 0x20,0x00,0x02,0x4e 0xf0,0x23,0x02,0x4e 0x20,0x40,0x02,0x4e 0xe0,0x63,0x02,0x4e -# CHECK: tbl v0.16b, {v1.16b}, v2.16b -# CHECK: tbl v16.16b, {v31.16b, v0.16b}, v2.16b -# CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b -# CHECK: tbl v0.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b +# CHECK: tbl v0.16b, { v1.16b }, v2.16b +# CHECK: tbl v16.16b, { v31.16b, v0.16b }, v2.16b +# CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b +# CHECK: tbl v0.16b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.16b 0x20,0x10,0x02,0x0e 0xf0,0x33,0x02,0x0e 0x20,0x50,0x02,0x0e 0xf0,0x72,0x02,0x0e -# CHECK: tbx v0.8b, {v1.16b}, v2.8b -# CHECK: tbx v16.8b, {v31.16b, v0.16b}, v2.8b -# CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b -# CHECK: tbx v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b +# CHECK: tbx v0.8b, { v1.16b }, v2.8b +# CHECK: tbx v16.8b, { v31.16b, v0.16b }, v2.8b +# CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b +# CHECK: tbx v16.8b, { v23.16b, v24.16b, v25.16b, v26.16b }, v2.8b 0x20,0x10,0x02,0x4e 0xf0,0x33,0x02,0x4e 0x20,0x50,0x02,0x4e 0xf0,0x73,0x02,0x4e -# CHECK: tbx v0.16b, {v1.16b}, v2.16b -# CHECK: tbx v16.16b, {v31.16b, v0.16b}, v2.16b -# CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b -# CHECK: tbx v16.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b +# CHECK: tbx v0.16b, { v1.16b }, v2.16b +# CHECK: tbx v16.16b, { v31.16b, v0.16b }, v2.16b +# CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b +# CHECK: tbx v16.16b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.16b #---------------------------------------------------------------------- # Scalar Floating-point Convert To Lower Precision Narrow, Rounding To diff --git a/test/MC/Disassembler/AArch64/trace-regs.txt b/test/MC/Disassembler/AArch64/trace-regs.txt index 10c5937..43171e3 100644 --- a/test/MC/Disassembler/AArch64/trace-regs.txt +++ b/test/MC/Disassembler/AArch64/trace-regs.txt @@ -1,736 +1,737 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-none-linux-gnu -disassemble < %s | FileCheck %s 0x8 0x3 0x31 0xd5 -# CHECK: mrs x8, trcstatr +# CHECK: mrs x8, {{trcstatr|TRCSTATR}} 0xc9 0x0 0x31 0xd5 -# CHECK: mrs x9, trcidr8 +# CHECK: mrs x9, {{trcidr8|TRCIDR8}} 0xcb 0x1 0x31 0xd5 -# CHECK: mrs x11, trcidr9 +# CHECK: mrs x11, {{trcidr9|TRCIDR9}} 0xd9 0x2 0x31 0xd5 -# CHECK: mrs x25, trcidr10 +# CHECK: mrs x25, {{trcidr10|TRCIDR10}} 0xc7 0x3 0x31 0xd5 -# CHECK: mrs x7, trcidr11 +# CHECK: mrs x7, {{trcidr11|TRCIDR11}} 0xc7 0x4 0x31 0xd5 -# CHECK: mrs x7, trcidr12 +# CHECK: mrs x7, {{trcidr12|TRCIDR12}} 0xc6 0x5 0x31 0xd5 -# CHECK: mrs x6, trcidr13 +# CHECK: mrs x6, {{trcidr13|TRCIDR13}} 0xfb 0x8 0x31 0xd5 -# CHECK: mrs x27, trcidr0 +# CHECK: mrs x27, {{trcidr0|TRCIDR0}} 0xfd 0x9 0x31 0xd5 -# CHECK: mrs x29, trcidr1 +# CHECK: mrs x29, {{trcidr1|TRCIDR1}} 0xe4 0xa 0x31 0xd5 -# CHECK: mrs x4, trcidr2 +# CHECK: mrs x4, {{trcidr2|TRCIDR2}} 0xe8 0xb 0x31 0xd5 -# CHECK: mrs x8, trcidr3 +# CHECK: mrs x8, {{trcidr3|TRCIDR3}} 0xef 0xc 0x31 0xd5 -# CHECK: mrs x15, trcidr4 +# CHECK: mrs x15, {{trcidr4|TRCIDR4}} 0xf4 0xd 0x31 0xd5 -# CHECK: mrs x20, trcidr5 +# CHECK: mrs x20, {{trcidr5|TRCIDR5}} 0xe6 0xe 0x31 0xd5 -# CHECK: mrs x6, trcidr6 +# CHECK: mrs x6, {{trcidr6|TRCIDR6}} 0xe6 0xf 0x31 0xd5 -# CHECK: mrs x6, trcidr7 +# CHECK: mrs x6, {{trcidr7|TRCIDR7}} 0x98 0x11 0x31 0xd5 -# CHECK: mrs x24, trcoslsr +# CHECK: mrs x24, {{trcoslsr|TRCOSLSR}} 0x92 0x15 0x31 0xd5 -# CHECK: mrs x18, trcpdsr +# CHECK: mrs x18, {{trcpdsr|TRCPDSR}} 0xdc 0x7a 0x31 0xd5 -# CHECK: mrs x28, trcdevaff0 +# CHECK: mrs x28, {{trcdevaff0|TRCDEVAFF0}} 0xc5 0x7b 0x31 0xd5 -# CHECK: mrs x5, trcdevaff1 +# CHECK: mrs x5, {{trcdevaff1|TRCDEVAFF1}} 0xc5 0x7d 0x31 0xd5 -# CHECK: mrs x5, trclsr +# CHECK: mrs x5, {{trclsr|TRCLSR}} 0xcb 0x7e 0x31 0xd5 -# CHECK: mrs x11, trcauthstatus +# CHECK: mrs x11, {{trcauthstatus|TRCAUTHSTATUS}} 0xcd 0x7f 0x31 0xd5 -# CHECK: mrs x13, trcdevarch +# CHECK: mrs x13, {{trcdevarch|TRCDEVARCH}} 0xf2 0x72 0x31 0xd5 -# CHECK: mrs x18, trcdevid +# CHECK: mrs x18, {{trcdevid|TRCDEVID}} 0xf6 0x73 0x31 0xd5 -# CHECK: mrs x22, trcdevtype +# CHECK: mrs x22, {{trcdevtype|TRCDEVTYPE}} 0xee 0x74 0x31 0xd5 -# CHECK: mrs x14, trcpidr4 +# CHECK: mrs x14, {{trcpidr4|TRCPIDR4}} 0xe5 0x75 0x31 0xd5 -# CHECK: mrs x5, trcpidr5 +# CHECK: mrs x5, {{trcpidr5|TRCPIDR5}} 0xe5 0x76 0x31 0xd5 -# CHECK: mrs x5, trcpidr6 +# CHECK: mrs x5, {{trcpidr6|TRCPIDR6}} 0xe9 0x77 0x31 0xd5 -# CHECK: mrs x9, trcpidr7 +# CHECK: mrs x9, {{trcpidr7|TRCPIDR7}} 0xef 0x78 0x31 0xd5 -# CHECK: mrs x15, trcpidr0 +# CHECK: mrs x15, {{trcpidr0|TRCPIDR0}} 0xe6 0x79 0x31 0xd5 -# CHECK: mrs x6, trcpidr1 +# CHECK: mrs x6, {{trcpidr1|TRCPIDR1}} 0xeb 0x7a 0x31 0xd5 -# CHECK: mrs x11, trcpidr2 +# CHECK: mrs x11, {{trcpidr2|TRCPIDR2}} 0xf4 0x7b 0x31 0xd5 -# CHECK: mrs x20, trcpidr3 +# CHECK: mrs x20, {{trcpidr3|TRCPIDR3}} 0xf1 0x7c 0x31 0xd5 -# CHECK: mrs x17, trccidr0 +# CHECK: mrs x17, {{trccidr0|TRCCIDR0}} 0xe2 0x7d 0x31 0xd5 -# CHECK: mrs x2, trccidr1 +# CHECK: mrs x2, {{trccidr1|TRCCIDR1}} 0xf4 0x7e 0x31 0xd5 -# CHECK: mrs x20, trccidr2 +# CHECK: mrs x20, {{trccidr2|TRCCIDR2}} 0xe4 0x7f 0x31 0xd5 -# CHECK: mrs x4, trccidr3 +# CHECK: mrs x4, {{trccidr3|TRCCIDR3}} 0xb 0x1 0x31 0xd5 -# CHECK: mrs x11, trcprgctlr +# CHECK: mrs x11, {{trcprgctlr|TRCPRGCTLR}} 0x17 0x2 0x31 0xd5 -# CHECK: mrs x23, trcprocselr +# CHECK: mrs x23, {{trcprocselr|TRCPROCSELR}} 0xd 0x4 0x31 0xd5 -# CHECK: mrs x13, trcconfigr +# CHECK: mrs x13, {{trcconfigr|TRCCONFIGR}} 0x17 0x6 0x31 0xd5 -# CHECK: mrs x23, trcauxctlr +# CHECK: mrs x23, {{trcauxctlr|TRCAUXCTLR}} 0x9 0x8 0x31 0xd5 -# CHECK: mrs x9, trceventctl0r +# CHECK: mrs x9, {{trceventctl0r|TRCEVENTCTL0R}} 0x10 0x9 0x31 0xd5 -# CHECK: mrs x16, trceventctl1r +# CHECK: mrs x16, {{trceventctl1r|TRCEVENTCTL1R}} 0x4 0xb 0x31 0xd5 -# CHECK: mrs x4, trcstallctlr +# CHECK: mrs x4, {{trcstallctlr|TRCSTALLCTLR}} 0xe 0xc 0x31 0xd5 -# CHECK: mrs x14, trctsctlr +# CHECK: mrs x14, {{trctsctlr|TRCTSCTLR}} 0x18 0xd 0x31 0xd5 -# CHECK: mrs x24, trcsyncpr +# CHECK: mrs x24, {{trcsyncpr|TRCSYNCPR}} 0x1c 0xe 0x31 0xd5 -# CHECK: mrs x28, trcccctlr +# CHECK: mrs x28, {{trcccctlr|TRCCCCTLR}} 0xf 0xf 0x31 0xd5 -# CHECK: mrs x15, trcbbctlr +# CHECK: mrs x15, {{trcbbctlr|TRCBBCTLR}} 0x21 0x0 0x31 0xd5 -# CHECK: mrs x1, trctraceidr +# CHECK: mrs x1, {{trctraceidr|TRCTRACEIDR}} 0x34 0x1 0x31 0xd5 -# CHECK: mrs x20, trcqctlr +# CHECK: mrs x20, {{trcqctlr|TRCQCTLR}} 0x42 0x0 0x31 0xd5 -# CHECK: mrs x2, trcvictlr +# CHECK: mrs x2, {{trcvictlr|TRCVICTLR}} 0x4c 0x1 0x31 0xd5 -# CHECK: mrs x12, trcviiectlr +# CHECK: mrs x12, {{trcviiectlr|TRCVIIECTLR}} 0x50 0x2 0x31 0xd5 -# CHECK: mrs x16, trcvissctlr +# CHECK: mrs x16, {{trcvissctlr|TRCVISSCTLR}} 0x48 0x3 0x31 0xd5 -# CHECK: mrs x8, trcvipcssctlr +# CHECK: mrs x8, {{trcvipcssctlr|TRCVIPCSSCTLR}} 0x5b 0x8 0x31 0xd5 -# CHECK: mrs x27, trcvdctlr +# CHECK: mrs x27, {{trcvdctlr|TRCVDCTLR}} 0x49 0x9 0x31 0xd5 -# CHECK: mrs x9, trcvdsacctlr +# CHECK: mrs x9, {{trcvdsacctlr|TRCVDSACCTLR}} 0x40 0xa 0x31 0xd5 -# CHECK: mrs x0, trcvdarcctlr +# CHECK: mrs x0, {{trcvdarcctlr|TRCVDARCCTLR}} 0x8d 0x0 0x31 0xd5 -# CHECK: mrs x13, trcseqevr0 +# CHECK: mrs x13, {{trcseqevr0|TRCSEQEVR0}} 0x8b 0x1 0x31 0xd5 -# CHECK: mrs x11, trcseqevr1 +# CHECK: mrs x11, {{trcseqevr1|TRCSEQEVR1}} 0x9a 0x2 0x31 0xd5 -# CHECK: mrs x26, trcseqevr2 +# CHECK: mrs x26, {{trcseqevr2|TRCSEQEVR2}} 0x8e 0x6 0x31 0xd5 -# CHECK: mrs x14, trcseqrstevr +# CHECK: mrs x14, {{trcseqrstevr|TRCSEQRSTEVR}} 0x84 0x7 0x31 0xd5 -# CHECK: mrs x4, trcseqstr +# CHECK: mrs x4, {{trcseqstr|TRCSEQSTR}} 0x91 0x8 0x31 0xd5 -# CHECK: mrs x17, trcextinselr +# CHECK: mrs x17, {{trcextinselr|TRCEXTINSELR}} 0xb5 0x0 0x31 0xd5 -# CHECK: mrs x21, trccntrldvr0 +# CHECK: mrs x21, {{trccntrldvr0|TRCCNTRLDVR0}} 0xaa 0x1 0x31 0xd5 -# CHECK: mrs x10, trccntrldvr1 +# CHECK: mrs x10, {{trccntrldvr1|TRCCNTRLDVR1}} 0xb4 0x2 0x31 0xd5 -# CHECK: mrs x20, trccntrldvr2 +# CHECK: mrs x20, {{trccntrldvr2|TRCCNTRLDVR2}} 0xa5 0x3 0x31 0xd5 -# CHECK: mrs x5, trccntrldvr3 +# CHECK: mrs x5, {{trccntrldvr3|TRCCNTRLDVR3}} 0xb1 0x4 0x31 0xd5 -# CHECK: mrs x17, trccntctlr0 +# CHECK: mrs x17, {{trccntctlr0|TRCCNTCTLR0}} 0xa1 0x5 0x31 0xd5 -# CHECK: mrs x1, trccntctlr1 +# CHECK: mrs x1, {{trccntctlr1|TRCCNTCTLR1}} 0xb1 0x6 0x31 0xd5 -# CHECK: mrs x17, trccntctlr2 +# CHECK: mrs x17, {{trccntctlr2|TRCCNTCTLR2}} 0xa6 0x7 0x31 0xd5 -# CHECK: mrs x6, trccntctlr3 +# CHECK: mrs x6, {{trccntctlr3|TRCCNTCTLR3}} 0xbc 0x8 0x31 0xd5 -# CHECK: mrs x28, trccntvr0 +# CHECK: mrs x28, {{trccntvr0|TRCCNTVR0}} 0xb7 0x9 0x31 0xd5 -# CHECK: mrs x23, trccntvr1 +# CHECK: mrs x23, {{trccntvr1|TRCCNTVR1}} 0xa9 0xa 0x31 0xd5 -# CHECK: mrs x9, trccntvr2 +# CHECK: mrs x9, {{trccntvr2|TRCCNTVR2}} 0xa6 0xb 0x31 0xd5 -# CHECK: mrs x6, trccntvr3 +# CHECK: mrs x6, {{trccntvr3|TRCCNTVR3}} 0xf8 0x0 0x31 0xd5 -# CHECK: mrs x24, trcimspec0 +# CHECK: mrs x24, {{trcimspec0|TRCIMSPEC0}} 0xf8 0x1 0x31 0xd5 -# CHECK: mrs x24, trcimspec1 +# CHECK: mrs x24, {{trcimspec1|TRCIMSPEC1}} 0xef 0x2 0x31 0xd5 -# CHECK: mrs x15, trcimspec2 +# CHECK: mrs x15, {{trcimspec2|TRCIMSPEC2}} 0xea 0x3 0x31 0xd5 -# CHECK: mrs x10, trcimspec3 +# CHECK: mrs x10, {{trcimspec3|TRCIMSPEC3}} 0xfd 0x4 0x31 0xd5 -# CHECK: mrs x29, trcimspec4 +# CHECK: mrs x29, {{trcimspec4|TRCIMSPEC4}} 0xf2 0x5 0x31 0xd5 -# CHECK: mrs x18, trcimspec5 +# CHECK: mrs x18, {{trcimspec5|TRCIMSPEC5}} 0xfd 0x6 0x31 0xd5 -# CHECK: mrs x29, trcimspec6 +# CHECK: mrs x29, {{trcimspec6|TRCIMSPEC6}} 0xe2 0x7 0x31 0xd5 -# CHECK: mrs x2, trcimspec7 +# CHECK: mrs x2, {{trcimspec7|TRCIMSPEC7}} 0x8 0x12 0x31 0xd5 -# CHECK: mrs x8, trcrsctlr2 +# CHECK: mrs x8, {{trcrsctlr2|TRCRSCTLR2}} 0x0 0x13 0x31 0xd5 -# CHECK: mrs x0, trcrsctlr3 +# CHECK: mrs x0, {{trcrsctlr3|TRCRSCTLR3}} 0xc 0x14 0x31 0xd5 -# CHECK: mrs x12, trcrsctlr4 +# CHECK: mrs x12, {{trcrsctlr4|TRCRSCTLR4}} 0x1a 0x15 0x31 0xd5 -# CHECK: mrs x26, trcrsctlr5 +# CHECK: mrs x26, {{trcrsctlr5|TRCRSCTLR5}} 0x1d 0x16 0x31 0xd5 -# CHECK: mrs x29, trcrsctlr6 +# CHECK: mrs x29, {{trcrsctlr6|TRCRSCTLR6}} 0x11 0x17 0x31 0xd5 -# CHECK: mrs x17, trcrsctlr7 +# CHECK: mrs x17, {{trcrsctlr7|TRCRSCTLR7}} 0x0 0x18 0x31 0xd5 -# CHECK: mrs x0, trcrsctlr8 +# CHECK: mrs x0, {{trcrsctlr8|TRCRSCTLR8}} 0x1 0x19 0x31 0xd5 -# CHECK: mrs x1, trcrsctlr9 +# CHECK: mrs x1, {{trcrsctlr9|TRCRSCTLR9}} 0x11 0x1a 0x31 0xd5 -# CHECK: mrs x17, trcrsctlr10 +# CHECK: mrs x17, {{trcrsctlr10|TRCRSCTLR10}} 0x15 0x1b 0x31 0xd5 -# CHECK: mrs x21, trcrsctlr11 +# CHECK: mrs x21, {{trcrsctlr11|TRCRSCTLR11}} 0x1 0x1c 0x31 0xd5 -# CHECK: mrs x1, trcrsctlr12 +# CHECK: mrs x1, {{trcrsctlr12|TRCRSCTLR12}} 0x8 0x1d 0x31 0xd5 -# CHECK: mrs x8, trcrsctlr13 +# CHECK: mrs x8, {{trcrsctlr13|TRCRSCTLR13}} 0x18 0x1e 0x31 0xd5 -# CHECK: mrs x24, trcrsctlr14 +# CHECK: mrs x24, {{trcrsctlr14|TRCRSCTLR14}} 0x0 0x1f 0x31 0xd5 -# CHECK: mrs x0, trcrsctlr15 +# CHECK: mrs x0, {{trcrsctlr15|TRCRSCTLR15}} 0x22 0x10 0x31 0xd5 -# CHECK: mrs x2, trcrsctlr16 +# CHECK: mrs x2, {{trcrsctlr16|TRCRSCTLR16}} 0x3d 0x11 0x31 0xd5 -# CHECK: mrs x29, trcrsctlr17 +# CHECK: mrs x29, {{trcrsctlr17|TRCRSCTLR17}} 0x36 0x12 0x31 0xd5 -# CHECK: mrs x22, trcrsctlr18 +# CHECK: mrs x22, {{trcrsctlr18|TRCRSCTLR18}} 0x26 0x13 0x31 0xd5 -# CHECK: mrs x6, trcrsctlr19 +# CHECK: mrs x6, {{trcrsctlr19|TRCRSCTLR19}} 0x3a 0x14 0x31 0xd5 -# CHECK: mrs x26, trcrsctlr20 +# CHECK: mrs x26, {{trcrsctlr20|TRCRSCTLR20}} 0x3a 0x15 0x31 0xd5 -# CHECK: mrs x26, trcrsctlr21 +# CHECK: mrs x26, {{trcrsctlr21|TRCRSCTLR21}} 0x24 0x16 0x31 0xd5 -# CHECK: mrs x4, trcrsctlr22 +# CHECK: mrs x4, {{trcrsctlr22|TRCRSCTLR22}} 0x2c 0x17 0x31 0xd5 -# CHECK: mrs x12, trcrsctlr23 +# CHECK: mrs x12, {{trcrsctlr23|TRCRSCTLR23}} 0x21 0x18 0x31 0xd5 -# CHECK: mrs x1, trcrsctlr24 +# CHECK: mrs x1, {{trcrsctlr24|TRCRSCTLR24}} 0x20 0x19 0x31 0xd5 -# CHECK: mrs x0, trcrsctlr25 +# CHECK: mrs x0, {{trcrsctlr25|TRCRSCTLR25}} 0x31 0x1a 0x31 0xd5 -# CHECK: mrs x17, trcrsctlr26 +# CHECK: mrs x17, {{trcrsctlr26|TRCRSCTLR26}} 0x28 0x1b 0x31 0xd5 -# CHECK: mrs x8, trcrsctlr27 +# CHECK: mrs x8, {{trcrsctlr27|TRCRSCTLR27}} 0x2a 0x1c 0x31 0xd5 -# CHECK: mrs x10, trcrsctlr28 +# CHECK: mrs x10, {{trcrsctlr28|TRCRSCTLR28}} 0x39 0x1d 0x31 0xd5 -# CHECK: mrs x25, trcrsctlr29 +# CHECK: mrs x25, {{trcrsctlr29|TRCRSCTLR29}} 0x2c 0x1e 0x31 0xd5 -# CHECK: mrs x12, trcrsctlr30 +# CHECK: mrs x12, {{trcrsctlr30|TRCRSCTLR30}} 0x2b 0x1f 0x31 0xd5 -# CHECK: mrs x11, trcrsctlr31 +# CHECK: mrs x11, {{trcrsctlr31|TRCRSCTLR31}} 0x52 0x10 0x31 0xd5 -# CHECK: mrs x18, trcssccr0 +# CHECK: mrs x18, {{trcssccr0|TRCSSCCR0}} 0x4c 0x11 0x31 0xd5 -# CHECK: mrs x12, trcssccr1 +# CHECK: mrs x12, {{trcssccr1|TRCSSCCR1}} 0x43 0x12 0x31 0xd5 -# CHECK: mrs x3, trcssccr2 +# CHECK: mrs x3, {{trcssccr2|TRCSSCCR2}} 0x42 0x13 0x31 0xd5 -# CHECK: mrs x2, trcssccr3 +# CHECK: mrs x2, {{trcssccr3|TRCSSCCR3}} 0x55 0x14 0x31 0xd5 -# CHECK: mrs x21, trcssccr4 +# CHECK: mrs x21, {{trcssccr4|TRCSSCCR4}} 0x4a 0x15 0x31 0xd5 -# CHECK: mrs x10, trcssccr5 +# CHECK: mrs x10, {{trcssccr5|TRCSSCCR5}} 0x56 0x16 0x31 0xd5 -# CHECK: mrs x22, trcssccr6 +# CHECK: mrs x22, {{trcssccr6|TRCSSCCR6}} 0x57 0x17 0x31 0xd5 -# CHECK: mrs x23, trcssccr7 +# CHECK: mrs x23, {{trcssccr7|TRCSSCCR7}} 0x57 0x18 0x31 0xd5 -# CHECK: mrs x23, trcsscsr0 +# CHECK: mrs x23, {{trcsscsr0|TRCSSCSR0}} 0x53 0x19 0x31 0xd5 -# CHECK: mrs x19, trcsscsr1 +# CHECK: mrs x19, {{trcsscsr1|TRCSSCSR1}} 0x59 0x1a 0x31 0xd5 -# CHECK: mrs x25, trcsscsr2 +# CHECK: mrs x25, {{trcsscsr2|TRCSSCSR2}} 0x51 0x1b 0x31 0xd5 -# CHECK: mrs x17, trcsscsr3 +# CHECK: mrs x17, {{trcsscsr3|TRCSSCSR3}} 0x53 0x1c 0x31 0xd5 -# CHECK: mrs x19, trcsscsr4 +# CHECK: mrs x19, {{trcsscsr4|TRCSSCSR4}} 0x4b 0x1d 0x31 0xd5 -# CHECK: mrs x11, trcsscsr5 +# CHECK: mrs x11, {{trcsscsr5|TRCSSCSR5}} 0x45 0x1e 0x31 0xd5 -# CHECK: mrs x5, trcsscsr6 +# CHECK: mrs x5, {{trcsscsr6|TRCSSCSR6}} 0x49 0x1f 0x31 0xd5 -# CHECK: mrs x9, trcsscsr7 +# CHECK: mrs x9, {{trcsscsr7|TRCSSCSR7}} 0x9a 0x14 0x31 0xd5 -# CHECK: mrs x26, trcpdcr +# CHECK: mrs x26, {{trcpdcr|TRCPDCR}} 0x8 0x20 0x31 0xd5 -# CHECK: mrs x8, trcacvr0 +# CHECK: mrs x8, {{trcacvr0|TRCACVR0}} 0xf 0x22 0x31 0xd5 -# CHECK: mrs x15, trcacvr1 +# CHECK: mrs x15, {{trcacvr1|TRCACVR1}} 0x13 0x24 0x31 0xd5 -# CHECK: mrs x19, trcacvr2 +# CHECK: mrs x19, {{trcacvr2|TRCACVR2}} 0x8 0x26 0x31 0xd5 -# CHECK: mrs x8, trcacvr3 +# CHECK: mrs x8, {{trcacvr3|TRCACVR3}} 0x1c 0x28 0x31 0xd5 -# CHECK: mrs x28, trcacvr4 +# CHECK: mrs x28, {{trcacvr4|TRCACVR4}} 0x3 0x2a 0x31 0xd5 -# CHECK: mrs x3, trcacvr5 +# CHECK: mrs x3, {{trcacvr5|TRCACVR5}} 0x19 0x2c 0x31 0xd5 -# CHECK: mrs x25, trcacvr6 +# CHECK: mrs x25, {{trcacvr6|TRCACVR6}} 0x18 0x2e 0x31 0xd5 -# CHECK: mrs x24, trcacvr7 +# CHECK: mrs x24, {{trcacvr7|TRCACVR7}} 0x26 0x20 0x31 0xd5 -# CHECK: mrs x6, trcacvr8 +# CHECK: mrs x6, {{trcacvr8|TRCACVR8}} 0x23 0x22 0x31 0xd5 -# CHECK: mrs x3, trcacvr9 +# CHECK: mrs x3, {{trcacvr9|TRCACVR9}} 0x38 0x24 0x31 0xd5 -# CHECK: mrs x24, trcacvr10 +# CHECK: mrs x24, {{trcacvr10|TRCACVR10}} 0x23 0x26 0x31 0xd5 -# CHECK: mrs x3, trcacvr11 +# CHECK: mrs x3, {{trcacvr11|TRCACVR11}} 0x2c 0x28 0x31 0xd5 -# CHECK: mrs x12, trcacvr12 +# CHECK: mrs x12, {{trcacvr12|TRCACVR12}} 0x29 0x2a 0x31 0xd5 -# CHECK: mrs x9, trcacvr13 +# CHECK: mrs x9, {{trcacvr13|TRCACVR13}} 0x2e 0x2c 0x31 0xd5 -# CHECK: mrs x14, trcacvr14 +# CHECK: mrs x14, {{trcacvr14|TRCACVR14}} 0x23 0x2e 0x31 0xd5 -# CHECK: mrs x3, trcacvr15 +# CHECK: mrs x3, {{trcacvr15|TRCACVR15}} 0x55 0x20 0x31 0xd5 -# CHECK: mrs x21, trcacatr0 +# CHECK: mrs x21, {{trcacatr0|TRCACATR0}} 0x5a 0x22 0x31 0xd5 -# CHECK: mrs x26, trcacatr1 +# CHECK: mrs x26, {{trcacatr1|TRCACATR1}} 0x48 0x24 0x31 0xd5 -# CHECK: mrs x8, trcacatr2 +# CHECK: mrs x8, {{trcacatr2|TRCACATR2}} 0x56 0x26 0x31 0xd5 -# CHECK: mrs x22, trcacatr3 +# CHECK: mrs x22, {{trcacatr3|TRCACATR3}} 0x46 0x28 0x31 0xd5 -# CHECK: mrs x6, trcacatr4 +# CHECK: mrs x6, {{trcacatr4|TRCACATR4}} 0x5d 0x2a 0x31 0xd5 -# CHECK: mrs x29, trcacatr5 +# CHECK: mrs x29, {{trcacatr5|TRCACATR5}} 0x45 0x2c 0x31 0xd5 -# CHECK: mrs x5, trcacatr6 +# CHECK: mrs x5, {{trcacatr6|TRCACATR6}} 0x52 0x2e 0x31 0xd5 -# CHECK: mrs x18, trcacatr7 +# CHECK: mrs x18, {{trcacatr7|TRCACATR7}} 0x62 0x20 0x31 0xd5 -# CHECK: mrs x2, trcacatr8 +# CHECK: mrs x2, {{trcacatr8|TRCACATR8}} 0x73 0x22 0x31 0xd5 -# CHECK: mrs x19, trcacatr9 +# CHECK: mrs x19, {{trcacatr9|TRCACATR9}} 0x6d 0x24 0x31 0xd5 -# CHECK: mrs x13, trcacatr10 +# CHECK: mrs x13, {{trcacatr10|TRCACATR10}} 0x79 0x26 0x31 0xd5 -# CHECK: mrs x25, trcacatr11 +# CHECK: mrs x25, {{trcacatr11|TRCACATR11}} 0x72 0x28 0x31 0xd5 -# CHECK: mrs x18, trcacatr12 +# CHECK: mrs x18, {{trcacatr12|TRCACATR12}} 0x7d 0x2a 0x31 0xd5 -# CHECK: mrs x29, trcacatr13 +# CHECK: mrs x29, {{trcacatr13|TRCACATR13}} 0x69 0x2c 0x31 0xd5 -# CHECK: mrs x9, trcacatr14 +# CHECK: mrs x9, {{trcacatr14|TRCACATR14}} 0x72 0x2e 0x31 0xd5 -# CHECK: mrs x18, trcacatr15 +# CHECK: mrs x18, {{trcacatr15|TRCACATR15}} 0x9d 0x20 0x31 0xd5 -# CHECK: mrs x29, trcdvcvr0 +# CHECK: mrs x29, {{trcdvcvr0|TRCDVCVR0}} 0x8f 0x24 0x31 0xd5 -# CHECK: mrs x15, trcdvcvr1 +# CHECK: mrs x15, {{trcdvcvr1|TRCDVCVR1}} 0x8f 0x28 0x31 0xd5 -# CHECK: mrs x15, trcdvcvr2 +# CHECK: mrs x15, {{trcdvcvr2|TRCDVCVR2}} 0x8f 0x2c 0x31 0xd5 -# CHECK: mrs x15, trcdvcvr3 +# CHECK: mrs x15, {{trcdvcvr3|TRCDVCVR3}} 0xb3 0x20 0x31 0xd5 -# CHECK: mrs x19, trcdvcvr4 +# CHECK: mrs x19, {{trcdvcvr4|TRCDVCVR4}} 0xb6 0x24 0x31 0xd5 -# CHECK: mrs x22, trcdvcvr5 +# CHECK: mrs x22, {{trcdvcvr5|TRCDVCVR5}} 0xbb 0x28 0x31 0xd5 -# CHECK: mrs x27, trcdvcvr6 +# CHECK: mrs x27, {{trcdvcvr6|TRCDVCVR6}} 0xa1 0x2c 0x31 0xd5 -# CHECK: mrs x1, trcdvcvr7 +# CHECK: mrs x1, {{trcdvcvr7|TRCDVCVR7}} 0xdd 0x20 0x31 0xd5 -# CHECK: mrs x29, trcdvcmr0 +# CHECK: mrs x29, {{trcdvcmr0|TRCDVCMR0}} 0xc9 0x24 0x31 0xd5 -# CHECK: mrs x9, trcdvcmr1 +# CHECK: mrs x9, {{trcdvcmr1|TRCDVCMR1}} 0xc1 0x28 0x31 0xd5 -# CHECK: mrs x1, trcdvcmr2 +# CHECK: mrs x1, {{trcdvcmr2|TRCDVCMR2}} 0xc2 0x2c 0x31 0xd5 -# CHECK: mrs x2, trcdvcmr3 +# CHECK: mrs x2, {{trcdvcmr3|TRCDVCMR3}} 0xe5 0x20 0x31 0xd5 -# CHECK: mrs x5, trcdvcmr4 +# CHECK: mrs x5, {{trcdvcmr4|TRCDVCMR4}} 0xf5 0x24 0x31 0xd5 -# CHECK: mrs x21, trcdvcmr5 +# CHECK: mrs x21, {{trcdvcmr5|TRCDVCMR5}} 0xe5 0x28 0x31 0xd5 -# CHECK: mrs x5, trcdvcmr6 +# CHECK: mrs x5, {{trcdvcmr6|TRCDVCMR6}} 0xe1 0x2c 0x31 0xd5 -# CHECK: mrs x1, trcdvcmr7 +# CHECK: mrs x1, {{trcdvcmr7|TRCDVCMR7}} 0x15 0x30 0x31 0xd5 -# CHECK: mrs x21, trccidcvr0 +# CHECK: mrs x21, {{trccidcvr0|TRCCIDCVR0}} 0x18 0x32 0x31 0xd5 -# CHECK: mrs x24, trccidcvr1 +# CHECK: mrs x24, {{trccidcvr1|TRCCIDCVR1}} 0x18 0x34 0x31 0xd5 -# CHECK: mrs x24, trccidcvr2 +# CHECK: mrs x24, {{trccidcvr2|TRCCIDCVR2}} 0xc 0x36 0x31 0xd5 -# CHECK: mrs x12, trccidcvr3 +# CHECK: mrs x12, {{trccidcvr3|TRCCIDCVR3}} 0xa 0x38 0x31 0xd5 -# CHECK: mrs x10, trccidcvr4 +# CHECK: mrs x10, {{trccidcvr4|TRCCIDCVR4}} 0x9 0x3a 0x31 0xd5 -# CHECK: mrs x9, trccidcvr5 +# CHECK: mrs x9, {{trccidcvr5|TRCCIDCVR5}} 0x6 0x3c 0x31 0xd5 -# CHECK: mrs x6, trccidcvr6 +# CHECK: mrs x6, {{trccidcvr6|TRCCIDCVR6}} 0x14 0x3e 0x31 0xd5 -# CHECK: mrs x20, trccidcvr7 +# CHECK: mrs x20, {{trccidcvr7|TRCCIDCVR7}} 0x34 0x30 0x31 0xd5 -# CHECK: mrs x20, trcvmidcvr0 +# CHECK: mrs x20, {{trcvmidcvr0|TRCVMIDCVR0}} 0x34 0x32 0x31 0xd5 -# CHECK: mrs x20, trcvmidcvr1 +# CHECK: mrs x20, {{trcvmidcvr1|TRCVMIDCVR1}} 0x3a 0x34 0x31 0xd5 -# CHECK: mrs x26, trcvmidcvr2 +# CHECK: mrs x26, {{trcvmidcvr2|TRCVMIDCVR2}} 0x21 0x36 0x31 0xd5 -# CHECK: mrs x1, trcvmidcvr3 +# CHECK: mrs x1, {{trcvmidcvr3|TRCVMIDCVR3}} 0x2e 0x38 0x31 0xd5 -# CHECK: mrs x14, trcvmidcvr4 +# CHECK: mrs x14, {{trcvmidcvr4|TRCVMIDCVR4}} 0x3b 0x3a 0x31 0xd5 -# CHECK: mrs x27, trcvmidcvr5 +# CHECK: mrs x27, {{trcvmidcvr5|TRCVMIDCVR5}} 0x3d 0x3c 0x31 0xd5 -# CHECK: mrs x29, trcvmidcvr6 +# CHECK: mrs x29, {{trcvmidcvr6|TRCVMIDCVR6}} 0x31 0x3e 0x31 0xd5 -# CHECK: mrs x17, trcvmidcvr7 +# CHECK: mrs x17, {{trcvmidcvr7|TRCVMIDCVR7}} 0x4a 0x30 0x31 0xd5 -# CHECK: mrs x10, trccidcctlr0 +# CHECK: mrs x10, {{trccidcctlr0|TRCCIDCCTLR0}} 0x44 0x31 0x31 0xd5 -# CHECK: mrs x4, trccidcctlr1 +# CHECK: mrs x4, {{trccidcctlr1|TRCCIDCCTLR1}} 0x49 0x32 0x31 0xd5 -# CHECK: mrs x9, trcvmidcctlr0 +# CHECK: mrs x9, {{trcvmidcctlr0|TRCVMIDCCTLR0}} 0x4b 0x33 0x31 0xd5 -# CHECK: mrs x11, trcvmidcctlr1 +# CHECK: mrs x11, {{trcvmidcctlr1|TRCVMIDCCTLR1}} 0x96 0x70 0x31 0xd5 -# CHECK: mrs x22, trcitctrl +# CHECK: mrs x22, {{trcitctrl|TRCITCTRL}} 0xd7 0x78 0x31 0xd5 -# CHECK: mrs x23, trcclaimset +# CHECK: mrs x23, {{trcclaimset|TRCCLAIMSET}} 0xce 0x79 0x31 0xd5 -# CHECK: mrs x14, trcclaimclr +# CHECK: mrs x14, {{trcclaimclr|TRCCLAIMCLR}} 0x9c 0x10 0x11 0xd5 -# CHECK: msr trcoslar, x28 +# CHECK: msr {{trcoslar|TRCOSLAR}}, x28 0xce 0x7c 0x11 0xd5 -# CHECK: msr trclar, x14 +# CHECK: msr {{trclar|TRCLAR}}, x14 0xa 0x1 0x11 0xd5 -# CHECK: msr trcprgctlr, x10 +# CHECK: msr {{trcprgctlr|TRCPRGCTLR}}, x10 0x1b 0x2 0x11 0xd5 -# CHECK: msr trcprocselr, x27 +# CHECK: msr {{trcprocselr|TRCPROCSELR}}, x27 0x18 0x4 0x11 0xd5 -# CHECK: msr trcconfigr, x24 +# CHECK: msr {{trcconfigr|TRCCONFIGR}}, x24 0x8 0x6 0x11 0xd5 -# CHECK: msr trcauxctlr, x8 +# CHECK: msr {{trcauxctlr|TRCAUXCTLR}}, x8 0x10 0x8 0x11 0xd5 -# CHECK: msr trceventctl0r, x16 +# CHECK: msr {{trceventctl0r|TRCEVENTCTL0R}}, x16 0x1b 0x9 0x11 0xd5 -# CHECK: msr trceventctl1r, x27 +# CHECK: msr {{trceventctl1r|TRCEVENTCTL1R}}, x27 0x1a 0xb 0x11 0xd5 -# CHECK: msr trcstallctlr, x26 +# CHECK: msr {{trcstallctlr|TRCSTALLCTLR}}, x26 0x0 0xc 0x11 0xd5 -# CHECK: msr trctsctlr, x0 +# CHECK: msr {{trctsctlr|TRCTSCTLR}}, x0 0xe 0xd 0x11 0xd5 -# CHECK: msr trcsyncpr, x14 +# CHECK: msr {{trcsyncpr|TRCSYNCPR}}, x14 0x8 0xe 0x11 0xd5 -# CHECK: msr trcccctlr, x8 +# CHECK: msr {{trcccctlr|TRCCCCTLR}}, x8 0x6 0xf 0x11 0xd5 -# CHECK: msr trcbbctlr, x6 +# CHECK: msr {{trcbbctlr|TRCBBCTLR}}, x6 0x37 0x0 0x11 0xd5 -# CHECK: msr trctraceidr, x23 +# CHECK: msr {{trctraceidr|TRCTRACEIDR}}, x23 0x25 0x1 0x11 0xd5 -# CHECK: msr trcqctlr, x5 +# CHECK: msr {{trcqctlr|TRCQCTLR}}, x5 0x40 0x0 0x11 0xd5 -# CHECK: msr trcvictlr, x0 +# CHECK: msr {{trcvictlr|TRCVICTLR}}, x0 0x40 0x1 0x11 0xd5 -# CHECK: msr trcviiectlr, x0 +# CHECK: msr {{trcviiectlr|TRCVIIECTLR}}, x0 0x41 0x2 0x11 0xd5 -# CHECK: msr trcvissctlr, x1 +# CHECK: msr {{trcvissctlr|TRCVISSCTLR}}, x1 0x40 0x3 0x11 0xd5 -# CHECK: msr trcvipcssctlr, x0 +# CHECK: msr {{trcvipcssctlr|TRCVIPCSSCTLR}}, x0 0x47 0x8 0x11 0xd5 -# CHECK: msr trcvdctlr, x7 +# CHECK: msr {{trcvdctlr|TRCVDCTLR}}, x7 0x52 0x9 0x11 0xd5 -# CHECK: msr trcvdsacctlr, x18 +# CHECK: msr {{trcvdsacctlr|TRCVDSACCTLR}}, x18 0x58 0xa 0x11 0xd5 -# CHECK: msr trcvdarcctlr, x24 +# CHECK: msr {{trcvdarcctlr|TRCVDARCCTLR}}, x24 0x9c 0x0 0x11 0xd5 -# CHECK: msr trcseqevr0, x28 +# CHECK: msr {{trcseqevr0|TRCSEQEVR0}}, x28 0x95 0x1 0x11 0xd5 -# CHECK: msr trcseqevr1, x21 +# CHECK: msr {{trcseqevr1|TRCSEQEVR1}}, x21 0x90 0x2 0x11 0xd5 -# CHECK: msr trcseqevr2, x16 +# CHECK: msr {{trcseqevr2|TRCSEQEVR2}}, x16 0x90 0x6 0x11 0xd5 -# CHECK: msr trcseqrstevr, x16 +# CHECK: msr {{trcseqrstevr|TRCSEQRSTEVR}}, x16 0x99 0x7 0x11 0xd5 -# CHECK: msr trcseqstr, x25 +# CHECK: msr {{trcseqstr|TRCSEQSTR}}, x25 0x9d 0x8 0x11 0xd5 -# CHECK: msr trcextinselr, x29 +# CHECK: msr {{trcextinselr|TRCEXTINSELR}}, x29 0xb4 0x0 0x11 0xd5 -# CHECK: msr trccntrldvr0, x20 +# CHECK: msr {{trccntrldvr0|TRCCNTRLDVR0}}, x20 0xb4 0x1 0x11 0xd5 -# CHECK: msr trccntrldvr1, x20 +# CHECK: msr {{trccntrldvr1|TRCCNTRLDVR1}}, x20 0xb6 0x2 0x11 0xd5 -# CHECK: msr trccntrldvr2, x22 +# CHECK: msr {{trccntrldvr2|TRCCNTRLDVR2}}, x22 0xac 0x3 0x11 0xd5 -# CHECK: msr trccntrldvr3, x12 +# CHECK: msr {{trccntrldvr3|TRCCNTRLDVR3}}, x12 0xb4 0x4 0x11 0xd5 -# CHECK: msr trccntctlr0, x20 +# CHECK: msr {{trccntctlr0|TRCCNTCTLR0}}, x20 0xa4 0x5 0x11 0xd5 -# CHECK: msr trccntctlr1, x4 +# CHECK: msr {{trccntctlr1|TRCCNTCTLR1}}, x4 0xa8 0x6 0x11 0xd5 -# CHECK: msr trccntctlr2, x8 +# CHECK: msr {{trccntctlr2|TRCCNTCTLR2}}, x8 0xb0 0x7 0x11 0xd5 -# CHECK: msr trccntctlr3, x16 +# CHECK: msr {{trccntctlr3|TRCCNTCTLR3}}, x16 0xa5 0x8 0x11 0xd5 -# CHECK: msr trccntvr0, x5 +# CHECK: msr {{trccntvr0|TRCCNTVR0}}, x5 0xbb 0x9 0x11 0xd5 -# CHECK: msr trccntvr1, x27 +# CHECK: msr {{trccntvr1|TRCCNTVR1}}, x27 0xb5 0xa 0x11 0xd5 -# CHECK: msr trccntvr2, x21 +# CHECK: msr {{trccntvr2|TRCCNTVR2}}, x21 0xa8 0xb 0x11 0xd5 -# CHECK: msr trccntvr3, x8 +# CHECK: msr {{trccntvr3|TRCCNTVR3}}, x8 0xe6 0x0 0x11 0xd5 -# CHECK: msr trcimspec0, x6 +# CHECK: msr {{trcimspec0|TRCIMSPEC0}}, x6 0xfb 0x1 0x11 0xd5 -# CHECK: msr trcimspec1, x27 +# CHECK: msr {{trcimspec1|TRCIMSPEC1}}, x27 0xf7 0x2 0x11 0xd5 -# CHECK: msr trcimspec2, x23 +# CHECK: msr {{trcimspec2|TRCIMSPEC2}}, x23 0xef 0x3 0x11 0xd5 -# CHECK: msr trcimspec3, x15 +# CHECK: msr {{trcimspec3|TRCIMSPEC3}}, x15 0xed 0x4 0x11 0xd5 -# CHECK: msr trcimspec4, x13 +# CHECK: msr {{trcimspec4|TRCIMSPEC4}}, x13 0xf9 0x5 0x11 0xd5 -# CHECK: msr trcimspec5, x25 +# CHECK: msr {{trcimspec5|TRCIMSPEC5}}, x25 0xf3 0x6 0x11 0xd5 -# CHECK: msr trcimspec6, x19 +# CHECK: msr {{trcimspec6|TRCIMSPEC6}}, x19 0xfb 0x7 0x11 0xd5 -# CHECK: msr trcimspec7, x27 +# CHECK: msr {{trcimspec7|TRCIMSPEC7}}, x27 0x4 0x12 0x11 0xd5 -# CHECK: msr trcrsctlr2, x4 +# CHECK: msr {{trcrsctlr2|TRCRSCTLR2}}, x4 0x0 0x13 0x11 0xd5 -# CHECK: msr trcrsctlr3, x0 +# CHECK: msr {{trcrsctlr3|TRCRSCTLR3}}, x0 0x15 0x14 0x11 0xd5 -# CHECK: msr trcrsctlr4, x21 +# CHECK: msr {{trcrsctlr4|TRCRSCTLR4}}, x21 0x8 0x15 0x11 0xd5 -# CHECK: msr trcrsctlr5, x8 +# CHECK: msr {{trcrsctlr5|TRCRSCTLR5}}, x8 0x14 0x16 0x11 0xd5 -# CHECK: msr trcrsctlr6, x20 +# CHECK: msr {{trcrsctlr6|TRCRSCTLR6}}, x20 0xb 0x17 0x11 0xd5 -# CHECK: msr trcrsctlr7, x11 +# CHECK: msr {{trcrsctlr7|TRCRSCTLR7}}, x11 0x12 0x18 0x11 0xd5 -# CHECK: msr trcrsctlr8, x18 +# CHECK: msr {{trcrsctlr8|TRCRSCTLR8}}, x18 0x18 0x19 0x11 0xd5 -# CHECK: msr trcrsctlr9, x24 +# CHECK: msr {{trcrsctlr9|TRCRSCTLR9}}, x24 0xf 0x1a 0x11 0xd5 -# CHECK: msr trcrsctlr10, x15 +# CHECK: msr {{trcrsctlr10|TRCRSCTLR10}}, x15 0x15 0x1b 0x11 0xd5 -# CHECK: msr trcrsctlr11, x21 +# CHECK: msr {{trcrsctlr11|TRCRSCTLR11}}, x21 0x4 0x1c 0x11 0xd5 -# CHECK: msr trcrsctlr12, x4 +# CHECK: msr {{trcrsctlr12|TRCRSCTLR12}}, x4 0x1c 0x1d 0x11 0xd5 -# CHECK: msr trcrsctlr13, x28 +# CHECK: msr {{trcrsctlr13|TRCRSCTLR13}}, x28 0x3 0x1e 0x11 0xd5 -# CHECK: msr trcrsctlr14, x3 +# CHECK: msr {{trcrsctlr14|TRCRSCTLR14}}, x3 0x14 0x1f 0x11 0xd5 -# CHECK: msr trcrsctlr15, x20 +# CHECK: msr {{trcrsctlr15|TRCRSCTLR15}}, x20 0x2c 0x10 0x11 0xd5 -# CHECK: msr trcrsctlr16, x12 +# CHECK: msr {{trcrsctlr16|TRCRSCTLR16}}, x12 0x31 0x11 0x11 0xd5 -# CHECK: msr trcrsctlr17, x17 +# CHECK: msr {{trcrsctlr17|TRCRSCTLR17}}, x17 0x2a 0x12 0x11 0xd5 -# CHECK: msr trcrsctlr18, x10 +# CHECK: msr {{trcrsctlr18|TRCRSCTLR18}}, x10 0x2b 0x13 0x11 0xd5 -# CHECK: msr trcrsctlr19, x11 +# CHECK: msr {{trcrsctlr19|TRCRSCTLR19}}, x11 0x23 0x14 0x11 0xd5 -# CHECK: msr trcrsctlr20, x3 +# CHECK: msr {{trcrsctlr20|TRCRSCTLR20}}, x3 0x32 0x15 0x11 0xd5 -# CHECK: msr trcrsctlr21, x18 +# CHECK: msr {{trcrsctlr21|TRCRSCTLR21}}, x18 0x3a 0x16 0x11 0xd5 -# CHECK: msr trcrsctlr22, x26 +# CHECK: msr {{trcrsctlr22|TRCRSCTLR22}}, x26 0x25 0x17 0x11 0xd5 -# CHECK: msr trcrsctlr23, x5 +# CHECK: msr {{trcrsctlr23|TRCRSCTLR23}}, x5 0x39 0x18 0x11 0xd5 -# CHECK: msr trcrsctlr24, x25 +# CHECK: msr {{trcrsctlr24|TRCRSCTLR24}}, x25 0x25 0x19 0x11 0xd5 -# CHECK: msr trcrsctlr25, x5 +# CHECK: msr {{trcrsctlr25|TRCRSCTLR25}}, x5 0x24 0x1a 0x11 0xd5 -# CHECK: msr trcrsctlr26, x4 +# CHECK: msr {{trcrsctlr26|TRCRSCTLR26}}, x4 0x34 0x1b 0x11 0xd5 -# CHECK: msr trcrsctlr27, x20 +# CHECK: msr {{trcrsctlr27|TRCRSCTLR27}}, x20 0x25 0x1c 0x11 0xd5 -# CHECK: msr trcrsctlr28, x5 +# CHECK: msr {{trcrsctlr28|TRCRSCTLR28}}, x5 0x2a 0x1d 0x11 0xd5 -# CHECK: msr trcrsctlr29, x10 +# CHECK: msr {{trcrsctlr29|TRCRSCTLR29}}, x10 0x38 0x1e 0x11 0xd5 -# CHECK: msr trcrsctlr30, x24 +# CHECK: msr {{trcrsctlr30|TRCRSCTLR30}}, x24 0x34 0x1f 0x11 0xd5 -# CHECK: msr trcrsctlr31, x20 +# CHECK: msr {{trcrsctlr31|TRCRSCTLR31}}, x20 0x57 0x10 0x11 0xd5 -# CHECK: msr trcssccr0, x23 +# CHECK: msr {{trcssccr0|TRCSSCCR0}}, x23 0x5b 0x11 0x11 0xd5 -# CHECK: msr trcssccr1, x27 +# CHECK: msr {{trcssccr1|TRCSSCCR1}}, x27 0x5b 0x12 0x11 0xd5 -# CHECK: msr trcssccr2, x27 +# CHECK: msr {{trcssccr2|TRCSSCCR2}}, x27 0x46 0x13 0x11 0xd5 -# CHECK: msr trcssccr3, x6 +# CHECK: msr {{trcssccr3|TRCSSCCR3}}, x6 0x43 0x14 0x11 0xd5 -# CHECK: msr trcssccr4, x3 +# CHECK: msr {{trcssccr4|TRCSSCCR4}}, x3 0x4c 0x15 0x11 0xd5 -# CHECK: msr trcssccr5, x12 +# CHECK: msr {{trcssccr5|TRCSSCCR5}}, x12 0x47 0x16 0x11 0xd5 -# CHECK: msr trcssccr6, x7 +# CHECK: msr {{trcssccr6|TRCSSCCR6}}, x7 0x46 0x17 0x11 0xd5 -# CHECK: msr trcssccr7, x6 +# CHECK: msr {{trcssccr7|TRCSSCCR7}}, x6 0x54 0x18 0x11 0xd5 -# CHECK: msr trcsscsr0, x20 +# CHECK: msr {{trcsscsr0|TRCSSCSR0}}, x20 0x51 0x19 0x11 0xd5 -# CHECK: msr trcsscsr1, x17 +# CHECK: msr {{trcsscsr1|TRCSSCSR1}}, x17 0x4b 0x1a 0x11 0xd5 -# CHECK: msr trcsscsr2, x11 +# CHECK: msr {{trcsscsr2|TRCSSCSR2}}, x11 0x44 0x1b 0x11 0xd5 -# CHECK: msr trcsscsr3, x4 +# CHECK: msr {{trcsscsr3|TRCSSCSR3}}, x4 0x4e 0x1c 0x11 0xd5 -# CHECK: msr trcsscsr4, x14 +# CHECK: msr {{trcsscsr4|TRCSSCSR4}}, x14 0x56 0x1d 0x11 0xd5 -# CHECK: msr trcsscsr5, x22 +# CHECK: msr {{trcsscsr5|TRCSSCSR5}}, x22 0x43 0x1e 0x11 0xd5 -# CHECK: msr trcsscsr6, x3 +# CHECK: msr {{trcsscsr6|TRCSSCSR6}}, x3 0x4b 0x1f 0x11 0xd5 -# CHECK: msr trcsscsr7, x11 +# CHECK: msr {{trcsscsr7|TRCSSCSR7}}, x11 0x83 0x14 0x11 0xd5 -# CHECK: msr trcpdcr, x3 +# CHECK: msr {{trcpdcr|TRCPDCR}}, x3 0x6 0x20 0x11 0xd5 -# CHECK: msr trcacvr0, x6 +# CHECK: msr {{trcacvr0|TRCACVR0}}, x6 0x14 0x22 0x11 0xd5 -# CHECK: msr trcacvr1, x20 +# CHECK: msr {{trcacvr1|TRCACVR1}}, x20 0x19 0x24 0x11 0xd5 -# CHECK: msr trcacvr2, x25 +# CHECK: msr {{trcacvr2|TRCACVR2}}, x25 0x1 0x26 0x11 0xd5 -# CHECK: msr trcacvr3, x1 +# CHECK: msr {{trcacvr3|TRCACVR3}}, x1 0x1c 0x28 0x11 0xd5 -# CHECK: msr trcacvr4, x28 +# CHECK: msr {{trcacvr4|TRCACVR4}}, x28 0xf 0x2a 0x11 0xd5 -# CHECK: msr trcacvr5, x15 +# CHECK: msr {{trcacvr5|TRCACVR5}}, x15 0x19 0x2c 0x11 0xd5 -# CHECK: msr trcacvr6, x25 +# CHECK: msr {{trcacvr6|TRCACVR6}}, x25 0xc 0x2e 0x11 0xd5 -# CHECK: msr trcacvr7, x12 +# CHECK: msr {{trcacvr7|TRCACVR7}}, x12 0x25 0x20 0x11 0xd5 -# CHECK: msr trcacvr8, x5 +# CHECK: msr {{trcacvr8|TRCACVR8}}, x5 0x39 0x22 0x11 0xd5 -# CHECK: msr trcacvr9, x25 +# CHECK: msr {{trcacvr9|TRCACVR9}}, x25 0x2d 0x24 0x11 0xd5 -# CHECK: msr trcacvr10, x13 +# CHECK: msr {{trcacvr10|TRCACVR10}}, x13 0x2a 0x26 0x11 0xd5 -# CHECK: msr trcacvr11, x10 +# CHECK: msr {{trcacvr11|TRCACVR11}}, x10 0x33 0x28 0x11 0xd5 -# CHECK: msr trcacvr12, x19 +# CHECK: msr {{trcacvr12|TRCACVR12}}, x19 0x2a 0x2a 0x11 0xd5 -# CHECK: msr trcacvr13, x10 +# CHECK: msr {{trcacvr13|TRCACVR13}}, x10 0x33 0x2c 0x11 0xd5 -# CHECK: msr trcacvr14, x19 +# CHECK: msr {{trcacvr14|TRCACVR14}}, x19 0x22 0x2e 0x11 0xd5 -# CHECK: msr trcacvr15, x2 +# CHECK: msr {{trcacvr15|TRCACVR15}}, x2 0x4f 0x20 0x11 0xd5 -# CHECK: msr trcacatr0, x15 +# CHECK: msr {{trcacatr0|TRCACATR0}}, x15 0x4d 0x22 0x11 0xd5 -# CHECK: msr trcacatr1, x13 +# CHECK: msr {{trcacatr1|TRCACATR1}}, x13 0x48 0x24 0x11 0xd5 -# CHECK: msr trcacatr2, x8 +# CHECK: msr {{trcacatr2|TRCACATR2}}, x8 0x41 0x26 0x11 0xd5 -# CHECK: msr trcacatr3, x1 +# CHECK: msr {{trcacatr3|TRCACATR3}}, x1 0x4b 0x28 0x11 0xd5 -# CHECK: msr trcacatr4, x11 +# CHECK: msr {{trcacatr4|TRCACATR4}}, x11 0x48 0x2a 0x11 0xd5 -# CHECK: msr trcacatr5, x8 +# CHECK: msr {{trcacatr5|TRCACATR5}}, x8 0x58 0x2c 0x11 0xd5 -# CHECK: msr trcacatr6, x24 +# CHECK: msr {{trcacatr6|TRCACATR6}}, x24 0x46 0x2e 0x11 0xd5 -# CHECK: msr trcacatr7, x6 +# CHECK: msr {{trcacatr7|TRCACATR7}}, x6 0x77 0x20 0x11 0xd5 -# CHECK: msr trcacatr8, x23 +# CHECK: msr {{trcacatr8|TRCACATR8}}, x23 0x65 0x22 0x11 0xd5 -# CHECK: msr trcacatr9, x5 +# CHECK: msr {{trcacatr9|TRCACATR9}}, x5 0x6b 0x24 0x11 0xd5 -# CHECK: msr trcacatr10, x11 +# CHECK: msr {{trcacatr10|TRCACATR10}}, x11 0x6b 0x26 0x11 0xd5 -# CHECK: msr trcacatr11, x11 +# CHECK: msr {{trcacatr11|TRCACATR11}}, x11 0x63 0x28 0x11 0xd5 -# CHECK: msr trcacatr12, x3 +# CHECK: msr {{trcacatr12|TRCACATR12}}, x3 0x7c 0x2a 0x11 0xd5 -# CHECK: msr trcacatr13, x28 +# CHECK: msr {{trcacatr13|TRCACATR13}}, x28 0x79 0x2c 0x11 0xd5 -# CHECK: msr trcacatr14, x25 +# CHECK: msr {{trcacatr14|TRCACATR14}}, x25 0x64 0x2e 0x11 0xd5 -# CHECK: msr trcacatr15, x4 +# CHECK: msr {{trcacatr15|TRCACATR15}}, x4 0x86 0x20 0x11 0xd5 -# CHECK: msr trcdvcvr0, x6 +# CHECK: msr {{trcdvcvr0|TRCDVCVR0}}, x6 0x83 0x24 0x11 0xd5 -# CHECK: msr trcdvcvr1, x3 +# CHECK: msr {{trcdvcvr1|TRCDVCVR1}}, x3 0x85 0x28 0x11 0xd5 -# CHECK: msr trcdvcvr2, x5 +# CHECK: msr {{trcdvcvr2|TRCDVCVR2}}, x5 0x8b 0x2c 0x11 0xd5 -# CHECK: msr trcdvcvr3, x11 +# CHECK: msr {{trcdvcvr3|TRCDVCVR3}}, x11 0xa9 0x20 0x11 0xd5 -# CHECK: msr trcdvcvr4, x9 +# CHECK: msr {{trcdvcvr4|TRCDVCVR4}}, x9 0xae 0x24 0x11 0xd5 -# CHECK: msr trcdvcvr5, x14 +# CHECK: msr {{trcdvcvr5|TRCDVCVR5}}, x14 0xaa 0x28 0x11 0xd5 -# CHECK: msr trcdvcvr6, x10 +# CHECK: msr {{trcdvcvr6|TRCDVCVR6}}, x10 0xac 0x2c 0x11 0xd5 -# CHECK: msr trcdvcvr7, x12 +# CHECK: msr {{trcdvcvr7|TRCDVCVR7}}, x12 0xc8 0x20 0x11 0xd5 -# CHECK: msr trcdvcmr0, x8 +# CHECK: msr {{trcdvcmr0|TRCDVCMR0}}, x8 0xc8 0x24 0x11 0xd5 -# CHECK: msr trcdvcmr1, x8 +# CHECK: msr {{trcdvcmr1|TRCDVCMR1}}, x8 0xd6 0x28 0x11 0xd5 -# CHECK: msr trcdvcmr2, x22 +# CHECK: msr {{trcdvcmr2|TRCDVCMR2}}, x22 0xd6 0x2c 0x11 0xd5 -# CHECK: msr trcdvcmr3, x22 +# CHECK: msr {{trcdvcmr3|TRCDVCMR3}}, x22 0xe5 0x20 0x11 0xd5 -# CHECK: msr trcdvcmr4, x5 +# CHECK: msr {{trcdvcmr4|TRCDVCMR4}}, x5 0xf0 0x24 0x11 0xd5 -# CHECK: msr trcdvcmr5, x16 +# CHECK: msr {{trcdvcmr5|TRCDVCMR5}}, x16 0xfb 0x28 0x11 0xd5 -# CHECK: msr trcdvcmr6, x27 +# CHECK: msr {{trcdvcmr6|TRCDVCMR6}}, x27 0xf5 0x2c 0x11 0xd5 -# CHECK: msr trcdvcmr7, x21 +# CHECK: msr {{trcdvcmr7|TRCDVCMR7}}, x21 0x8 0x30 0x11 0xd5 -# CHECK: msr trccidcvr0, x8 +# CHECK: msr {{trccidcvr0|TRCCIDCVR0}}, x8 0x6 0x32 0x11 0xd5 -# CHECK: msr trccidcvr1, x6 +# CHECK: msr {{trccidcvr1|TRCCIDCVR1}}, x6 0x9 0x34 0x11 0xd5 -# CHECK: msr trccidcvr2, x9 +# CHECK: msr {{trccidcvr2|TRCCIDCVR2}}, x9 0x8 0x36 0x11 0xd5 -# CHECK: msr trccidcvr3, x8 +# CHECK: msr {{trccidcvr3|TRCCIDCVR3}}, x8 0x3 0x38 0x11 0xd5 -# CHECK: msr trccidcvr4, x3 +# CHECK: msr {{trccidcvr4|TRCCIDCVR4}}, x3 0x15 0x3a 0x11 0xd5 -# CHECK: msr trccidcvr5, x21 +# CHECK: msr {{trccidcvr5|TRCCIDCVR5}}, x21 0xc 0x3c 0x11 0xd5 -# CHECK: msr trccidcvr6, x12 +# CHECK: msr {{trccidcvr6|TRCCIDCVR6}}, x12 0x7 0x3e 0x11 0xd5 -# CHECK: msr trccidcvr7, x7 +# CHECK: msr {{trccidcvr7|TRCCIDCVR7}}, x7 0x24 0x30 0x11 0xd5 -# CHECK: msr trcvmidcvr0, x4 +# CHECK: msr {{trcvmidcvr0|TRCVMIDCVR0}}, x4 0x23 0x32 0x11 0xd5 -# CHECK: msr trcvmidcvr1, x3 +# CHECK: msr {{trcvmidcvr1|TRCVMIDCVR1}}, x3 0x29 0x34 0x11 0xd5 -# CHECK: msr trcvmidcvr2, x9 +# CHECK: msr {{trcvmidcvr2|TRCVMIDCVR2}}, x9 0x31 0x36 0x11 0xd5 -# CHECK: msr trcvmidcvr3, x17 +# CHECK: msr {{trcvmidcvr3|TRCVMIDCVR3}}, x17 0x2e 0x38 0x11 0xd5 -# CHECK: msr trcvmidcvr4, x14 +# CHECK: msr {{trcvmidcvr4|TRCVMIDCVR4}}, x14 0x2c 0x3a 0x11 0xd5 -# CHECK: msr trcvmidcvr5, x12 +# CHECK: msr {{trcvmidcvr5|TRCVMIDCVR5}}, x12 0x2a 0x3c 0x11 0xd5 -# CHECK: msr trcvmidcvr6, x10 +# CHECK: msr {{trcvmidcvr6|TRCVMIDCVR6}}, x10 0x23 0x3e 0x11 0xd5 -# CHECK: msr trcvmidcvr7, x3 +# CHECK: msr {{trcvmidcvr7|TRCVMIDCVR7}}, x3 0x4e 0x30 0x11 0xd5 -# CHECK: msr trccidcctlr0, x14 +# CHECK: msr {{trccidcctlr0|TRCCIDCCTLR0}}, x14 0x56 0x31 0x11 0xd5 -# CHECK: msr trccidcctlr1, x22 +# CHECK: msr {{trccidcctlr1|TRCCIDCCTLR1}}, x22 0x48 0x32 0x11 0xd5 -# CHECK: msr trcvmidcctlr0, x8 +# CHECK: msr {{trcvmidcctlr0|TRCVMIDCCTLR0}}, x8 0x4f 0x33 0x11 0xd5 -# CHECK: msr trcvmidcctlr1, x15 +# CHECK: msr {{trcvmidcctlr1|TRCVMIDCCTLR1}}, x15 0x81 0x70 0x11 0xd5 -# CHECK: msr trcitctrl, x1 +# CHECK: msr {{trcitctrl|TRCITCTRL}}, x1 0xc7 0x78 0x11 0xd5 -# CHECK: msr trcclaimset, x7 +# CHECK: msr {{trcclaimset|TRCCLAIMSET}}, x7 0xdd 0x79 0x11 0xd5 -# CHECK: msr trcclaimclr, x29 +# CHECK: msr {{trcclaimclr|TRCCLAIMCLR}}, x29 |