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diff --git a/test/MC/Disassembler/ARM64/logical.txt b/test/MC/Disassembler/ARM64/logical.txt
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-# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
-
-#==---------------------------------------------------------------------------==
-# 5.4.2 Logical (immediate)
-#==---------------------------------------------------------------------------==
-
-0x00 0x00 0x00 0x12
-0x00 0x00 0x40 0x92
-0x41 0x0c 0x00 0x12
-0x41 0x0c 0x40 0x92
-0xbf 0xec 0x7c 0x92
-0x00 0x00 0x00 0x72
-0x00 0x00 0x40 0xf2
-0x41 0x0c 0x00 0x72
-0x41 0x0c 0x40 0xf2
-
-# CHECK: and w0, w0, #0x1
-# CHECK: and x0, x0, #0x1
-# CHECK: and w1, w2, #0xf
-# CHECK: and x1, x2, #0xf
-# CHECK: and sp, x5, #0xfffffffffffffff0
-# CHECK: ands w0, w0, #0x1
-# CHECK: ands x0, x0, #0x1
-# CHECK: ands w1, w2, #0xf
-# CHECK: ands x1, x2, #0xf
-
-0x41 0x00 0x12 0x52
-0x41 0x00 0x71 0xd2
-
-# CHECK: eor w1, w2, #0x4000
-# CHECK: eor x1, x2, #0x8000
-
-0x41 0x00 0x12 0x32
-0x41 0x00 0x71 0xb2
-
-# CHECK: orr w1, w2, #0x4000
-# CHECK: orr x1, x2, #0x8000
-
-#==---------------------------------------------------------------------------==
-# 5.5.3 Logical (shifted register)
-#==---------------------------------------------------------------------------==
-
-0x41 0x00 0x03 0x0a
-0x41 0x00 0x03 0x8a
-0x41 0x08 0x03 0x0a
-0x41 0x08 0x03 0x8a
-0x41 0x08 0x43 0x0a
-0x41 0x08 0x43 0x8a
-0x41 0x08 0x83 0x0a
-0x41 0x08 0x83 0x8a
-0x41 0x08 0xc3 0x0a
-0x41 0x08 0xc3 0x8a
-
-# CHECK: and w1, w2, w3
-# CHECK: and x1, x2, x3
-# CHECK: and w1, w2, w3, lsl #2
-# CHECK: and x1, x2, x3, lsl #2
-# CHECK: and w1, w2, w3, lsr #2
-# CHECK: and x1, x2, x3, lsr #2
-# CHECK: and w1, w2, w3, asr #2
-# CHECK: and x1, x2, x3, asr #2
-# CHECK: and w1, w2, w3, ror #2
-# CHECK: and x1, x2, x3, ror #2
-
-0x41 0x00 0x03 0x6a
-0x41 0x00 0x03 0xea
-0x41 0x08 0x03 0x6a
-0x41 0x08 0x03 0xea
-0x41 0x08 0x43 0x6a
-0x41 0x08 0x43 0xea
-0x41 0x08 0x83 0x6a
-0x41 0x08 0x83 0xea
-0x41 0x08 0xc3 0x6a
-0x41 0x08 0xc3 0xea
-
-# CHECK: ands w1, w2, w3
-# CHECK: ands x1, x2, x3
-# CHECK: ands w1, w2, w3, lsl #2
-# CHECK: ands x1, x2, x3, lsl #2
-# CHECK: ands w1, w2, w3, lsr #2
-# CHECK: ands x1, x2, x3, lsr #2
-# CHECK: ands w1, w2, w3, asr #2
-# CHECK: ands x1, x2, x3, asr #2
-# CHECK: ands w1, w2, w3, ror #2
-# CHECK: ands x1, x2, x3, ror #2
-
-0x41 0x00 0x23 0x0a
-0x41 0x00 0x23 0x8a
-0x41 0x0c 0x23 0x0a
-0x41 0x0c 0x23 0x8a
-0x41 0x0c 0x63 0x0a
-0x41 0x0c 0x63 0x8a
-0x41 0x0c 0xa3 0x0a
-0x41 0x0c 0xa3 0x8a
-0x41 0x0c 0xe3 0x0a
-0x41 0x0c 0xe3 0x8a
-
-# CHECK: bic w1, w2, w3
-# CHECK: bic x1, x2, x3
-# CHECK: bic w1, w2, w3, lsl #3
-# CHECK: bic x1, x2, x3, lsl #3
-# CHECK: bic w1, w2, w3, lsr #3
-# CHECK: bic x1, x2, x3, lsr #3
-# CHECK: bic w1, w2, w3, asr #3
-# CHECK: bic x1, x2, x3, asr #3
-# CHECK: bic w1, w2, w3, ror #3
-# CHECK: bic x1, x2, x3, ror #3
-
-0x41 0x00 0x23 0x6a
-0x41 0x00 0x23 0xea
-0x41 0x0c 0x23 0x6a
-0x41 0x0c 0x23 0xea
-0x41 0x0c 0x63 0x6a
-0x41 0x0c 0x63 0xea
-0x41 0x0c 0xa3 0x6a
-0x41 0x0c 0xa3 0xea
-0x41 0x0c 0xe3 0x6a
-0x41 0x0c 0xe3 0xea
-
-# CHECK: bics w1, w2, w3
-# CHECK: bics x1, x2, x3
-# CHECK: bics w1, w2, w3, lsl #3
-# CHECK: bics x1, x2, x3, lsl #3
-# CHECK: bics w1, w2, w3, lsr #3
-# CHECK: bics x1, x2, x3, lsr #3
-# CHECK: bics w1, w2, w3, asr #3
-# CHECK: bics x1, x2, x3, asr #3
-# CHECK: bics w1, w2, w3, ror #3
-# CHECK: bics x1, x2, x3, ror #3
-
-0x41 0x00 0x23 0x4a
-0x41 0x00 0x23 0xca
-0x41 0x10 0x23 0x4a
-0x41 0x10 0x23 0xca
-0x41 0x10 0x63 0x4a
-0x41 0x10 0x63 0xca
-0x41 0x10 0xa3 0x4a
-0x41 0x10 0xa3 0xca
-0x41 0x10 0xe3 0x4a
-0x41 0x10 0xe3 0xca
-
-# CHECK: eon w1, w2, w3
-# CHECK: eon x1, x2, x3
-# CHECK: eon w1, w2, w3, lsl #4
-# CHECK: eon x1, x2, x3, lsl #4
-# CHECK: eon w1, w2, w3, lsr #4
-# CHECK: eon x1, x2, x3, lsr #4
-# CHECK: eon w1, w2, w3, asr #4
-# CHECK: eon x1, x2, x3, asr #4
-# CHECK: eon w1, w2, w3, ror #4
-# CHECK: eon x1, x2, x3, ror #4
-
-0x41 0x00 0x03 0x4a
-0x41 0x00 0x03 0xca
-0x41 0x14 0x03 0x4a
-0x41 0x14 0x03 0xca
-0x41 0x14 0x43 0x4a
-0x41 0x14 0x43 0xca
-0x41 0x14 0x83 0x4a
-0x41 0x14 0x83 0xca
-0x41 0x14 0xc3 0x4a
-0x41 0x14 0xc3 0xca
-
-# CHECK: eor w1, w2, w3
-# CHECK: eor x1, x2, x3
-# CHECK: eor w1, w2, w3, lsl #5
-# CHECK: eor x1, x2, x3, lsl #5
-# CHECK: eor w1, w2, w3, lsr #5
-# CHECK: eor x1, x2, x3, lsr #5
-# CHECK: eor w1, w2, w3, asr #5
-# CHECK: eor x1, x2, x3, asr #5
-# CHECK: eor w1, w2, w3, ror #5
-# CHECK: eor x1, x2, x3, ror #5
-
-0x41 0x00 0x03 0x2a
-0x41 0x00 0x03 0xaa
-0x41 0x18 0x03 0x2a
-0x41 0x18 0x03 0xaa
-0x41 0x18 0x43 0x2a
-0x41 0x18 0x43 0xaa
-0x41 0x18 0x83 0x2a
-0x41 0x18 0x83 0xaa
-0x41 0x18 0xc3 0x2a
-0x41 0x18 0xc3 0xaa
-
-# CHECK: orr w1, w2, w3
-# CHECK: orr x1, x2, x3
-# CHECK: orr w1, w2, w3, lsl #6
-# CHECK: orr x1, x2, x3, lsl #6
-# CHECK: orr w1, w2, w3, lsr #6
-# CHECK: orr x1, x2, x3, lsr #6
-# CHECK: orr w1, w2, w3, asr #6
-# CHECK: orr x1, x2, x3, asr #6
-# CHECK: orr w1, w2, w3, ror #6
-# CHECK: orr x1, x2, x3, ror #6
-
-0x41 0x00 0x23 0x2a
-0x41 0x00 0x23 0xaa
-0x41 0x1c 0x23 0x2a
-0x41 0x1c 0x23 0xaa
-0x41 0x1c 0x63 0x2a
-0x41 0x1c 0x63 0xaa
-0x41 0x1c 0xa3 0x2a
-0x41 0x1c 0xa3 0xaa
-0x41 0x1c 0xe3 0x2a
-0x41 0x1c 0xe3 0xaa
-
-# CHECK: orn w1, w2, w3
-# CHECK: orn x1, x2, x3
-# CHECK: orn w1, w2, w3, lsl #7
-# CHECK: orn x1, x2, x3, lsl #7
-# CHECK: orn w1, w2, w3, lsr #7
-# CHECK: orn x1, x2, x3, lsr #7
-# CHECK: orn w1, w2, w3, asr #7
-# CHECK: orn x1, x2, x3, asr #7
-# CHECK: orn w1, w2, w3, ror #7
-# CHECK: orn x1, x2, x3, ror #7