diff options
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/CellSPU/icmp16.ll | 246 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/icmp32.ll | 249 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/icmp8.ll | 180 |
3 files changed, 643 insertions, 32 deletions
diff --git a/test/CodeGen/CellSPU/icmp16.ll b/test/CodeGen/CellSPU/icmp16.ll index 32b1261..2f9b091 100644 --- a/test/CodeGen/CellSPU/icmp16.ll +++ b/test/CodeGen/CellSPU/icmp16.ll @@ -1,14 +1,4 @@ -; RUN: llc < %s -march=cellspu > %t1.s -; RUN: grep ilh %t1.s | count 15 -; RUN: grep ceqh %t1.s | count 29 -; RUN: grep ceqhi %t1.s | count 13 -; RUN: grep clgth %t1.s | count 15 -; RUN: grep cgth %t1.s | count 14 -; RUN: grep cgthi %t1.s | count 6 -; RUN: grep {selb\t\\\$3, \\\$6, \\\$5, \\\$3} %t1.s | count 7 -; RUN: grep {selb\t\\\$3, \\\$5, \\\$6, \\\$3} %t1.s | count 3 -; RUN: grep {selb\t\\\$3, \\\$5, \\\$4, \\\$3} %t1.s | count 17 -; RUN: grep {selb\t\\\$3, \\\$4, \\\$5, \\\$3} %t1.s | count 6 +; RUN: llc < %s -march=cellspu | FileCheck %s target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" @@ -27,6 +17,10 @@ target triple = "spu" ; i16 integer comparisons: define i16 @icmp_eq_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_eq_select_i16: +; CHECK: ceqh +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp eq i16 %arg1, %arg2 %B = select i1 %A, i16 %val1, i16 %val2 @@ -34,12 +28,22 @@ entry: } define i1 @icmp_eq_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_eq_setcc_i16: +; CHECK: ilhu +; CHECK: ceqh +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp eq i16 %arg1, %arg2 ret i1 %A } define i16 @icmp_eq_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_eq_immed01_i16: +; CHECK: ceqhi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp eq i16 %arg1, 511 %B = select i1 %A, i16 %val1, i16 %val2 @@ -47,6 +51,10 @@ entry: } define i16 @icmp_eq_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_eq_immed02_i16: +; CHECK: ceqhi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp eq i16 %arg1, -512 %B = select i1 %A, i16 %val1, i16 %val2 @@ -54,6 +62,10 @@ entry: } define i16 @icmp_eq_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_eq_immed03_i16: +; CHECK: ceqhi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp eq i16 %arg1, -1 %B = select i1 %A, i16 %val1, i16 %val2 @@ -61,6 +73,11 @@ entry: } define i16 @icmp_eq_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_eq_immed04_i16: +; CHECK: ilh +; CHECK: ceqh +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp eq i16 %arg1, 32768 %B = select i1 %A, i16 %val1, i16 %val2 @@ -68,6 +85,10 @@ entry: } define i16 @icmp_ne_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ne_select_i16: +; CHECK: ceqh +; CHECK: selb $3, $5, $6, $3 + entry: %A = icmp ne i16 %arg1, %arg2 %B = select i1 %A, i16 %val1, i16 %val2 @@ -75,12 +96,23 @@ entry: } define i1 @icmp_ne_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ne_setcc_i16: +; CHECK: ceqh +; CHECK: ilhu +; CHECK: xorhi +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp ne i16 %arg1, %arg2 ret i1 %A } define i16 @icmp_ne_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ne_immed01_i16: +; CHECK: ceqhi +; CHECK: selb $3, $4, $5, $3 + entry: %A = icmp ne i16 %arg1, 511 %B = select i1 %A, i16 %val1, i16 %val2 @@ -88,6 +120,10 @@ entry: } define i16 @icmp_ne_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ne_immed02_i16: +; CHECK: ceqhi +; CHECK: selb $3, $4, $5, $3 + entry: %A = icmp ne i16 %arg1, -512 %B = select i1 %A, i16 %val1, i16 %val2 @@ -95,6 +131,10 @@ entry: } define i16 @icmp_ne_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ne_immed03_i16: +; CHECK: ceqhi +; CHECK: selb $3, $4, $5, $3 + entry: %A = icmp ne i16 %arg1, -1 %B = select i1 %A, i16 %val1, i16 %val2 @@ -102,6 +142,11 @@ entry: } define i16 @icmp_ne_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ne_immed04_i16: +; CHECK: ilh +; CHECK: ceqh +; CHECK: selb $3, $4, $5, $3 + entry: %A = icmp ne i16 %arg1, 32768 %B = select i1 %A, i16 %val1, i16 %val2 @@ -109,6 +154,10 @@ entry: } define i16 @icmp_ugt_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ugt_select_i16: +; CHECK: clgth +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp ugt i16 %arg1, %arg2 %B = select i1 %A, i16 %val1, i16 %val2 @@ -116,12 +165,22 @@ entry: } define i1 @icmp_ugt_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ugt_setcc_i16: +; CHECK: ilhu +; CHECK: clgth +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp ugt i16 %arg1, %arg2 ret i1 %A } define i16 @icmp_ugt_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ugt_immed01_i16: +; CHECK: clgthi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ugt i16 %arg1, 500 %B = select i1 %A, i16 %val1, i16 %val2 @@ -129,6 +188,10 @@ entry: } define i16 @icmp_ugt_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ugt_immed02_i16: +; CHECK: ceqhi +; CHECK: selb $3, $4, $5, $3 + entry: %A = icmp ugt i16 %arg1, 0 %B = select i1 %A, i16 %val1, i16 %val2 @@ -136,6 +199,10 @@ entry: } define i16 @icmp_ugt_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ugt_immed03_i16: +; CHECK: clgthi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ugt i16 %arg1, 65024 %B = select i1 %A, i16 %val1, i16 %val2 @@ -143,6 +210,11 @@ entry: } define i16 @icmp_ugt_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ugt_immed04_i16: +; CHECK: ilh +; CHECK: clgth +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ugt i16 %arg1, 32768 %B = select i1 %A, i16 %val1, i16 %val2 @@ -150,6 +222,12 @@ entry: } define i16 @icmp_uge_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_uge_select_i16: +; CHECK: ceqh +; CHECK: clgth +; CHECK: or +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp uge i16 %arg1, %arg2 %B = select i1 %A, i16 %val1, i16 %val2 @@ -157,6 +235,14 @@ entry: } define i1 @icmp_uge_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_uge_setcc_i16: +; CHECK: ceqh +; CHECK: clgth +; CHECK: ilhu +; CHECK: or +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp uge i16 %arg1, %arg2 ret i1 %A @@ -169,6 +255,12 @@ entry: ;; they'll ever be generated. define i16 @icmp_ult_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ult_select_i16: +; CHECK: ceqh +; CHECK: clgth +; CHECK: nor +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp ult i16 %arg1, %arg2 %B = select i1 %A, i16 %val1, i16 %val2 @@ -176,12 +268,26 @@ entry: } define i1 @icmp_ult_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ult_setcc_i16: +; CHECK: ceqh +; CHECK: clgth +; CHECK: ilhu +; CHECK: nor +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp ult i16 %arg1, %arg2 ret i1 %A } define i16 @icmp_ult_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ult_immed01_i16: +; CHECK: ceqhi +; CHECK: clgthi +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ult i16 %arg1, 511 %B = select i1 %A, i16 %val1, i16 %val2 @@ -189,6 +295,12 @@ entry: } define i16 @icmp_ult_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ult_immed02_i16: +; CHECK: ceqhi +; CHECK: clgthi +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ult i16 %arg1, 65534 %B = select i1 %A, i16 %val1, i16 %val2 @@ -196,6 +308,12 @@ entry: } define i16 @icmp_ult_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ult_immed03_i16: +; CHECK: ceqhi +; CHECK: clgthi +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ult i16 %arg1, 65024 %B = select i1 %A, i16 %val1, i16 %val2 @@ -203,6 +321,13 @@ entry: } define i16 @icmp_ult_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ult_immed04_i16: +; CHECK: ilh +; CHECK: ceqh +; CHECK: clgth +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ult i16 %arg1, 32769 %B = select i1 %A, i16 %val1, i16 %val2 @@ -210,6 +335,10 @@ entry: } define i16 @icmp_ule_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ule_select_i16: +; CHECK: clgth +; CHECK: selb $3, $5, $6, $3 + entry: %A = icmp ule i16 %arg1, %arg2 %B = select i1 %A, i16 %val1, i16 %val2 @@ -217,6 +346,13 @@ entry: } define i1 @icmp_ule_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_ule_setcc_i16: +; CHECK: clgth +; CHECK: ilhu +; CHECK: xorhi +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp ule i16 %arg1, %arg2 ret i1 %A @@ -229,6 +365,10 @@ entry: ;; they'll ever be generated. define i16 @icmp_sgt_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_sgt_select_i16: +; CHECK: cgth +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp sgt i16 %arg1, %arg2 %B = select i1 %A, i16 %val1, i16 %val2 @@ -236,12 +376,22 @@ entry: } define i1 @icmp_sgt_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_sgt_setcc_i16: +; CHECK: ilhu +; CHECK: cgth +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp sgt i16 %arg1, %arg2 ret i1 %A } define i16 @icmp_sgt_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_sgt_immed01_i16: +; CHECK: cgthi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp sgt i16 %arg1, 511 %B = select i1 %A, i16 %val1, i16 %val2 @@ -249,6 +399,10 @@ entry: } define i16 @icmp_sgt_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_sgt_immed02_i16: +; CHECK: cgthi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp sgt i16 %arg1, -1 %B = select i1 %A, i16 %val1, i16 %val2 @@ -256,6 +410,10 @@ entry: } define i16 @icmp_sgt_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_sgt_immed03_i16: +; CHECK: cgthi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp sgt i16 %arg1, -512 %B = select i1 %A, i16 %val1, i16 %val2 @@ -263,6 +421,11 @@ entry: } define i16 @icmp_sgt_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_sgt_immed04_i16: +; CHECK: ilh +; CHECK: ceqh +; CHECK: selb $3, $4, $5, $3 + entry: %A = icmp sgt i16 %arg1, 32768 %B = select i1 %A, i16 %val1, i16 %val2 @@ -270,6 +433,12 @@ entry: } define i16 @icmp_sge_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_sge_select_i16: +; CHECK: ceqh +; CHECK: cgth +; CHECK: or +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp sge i16 %arg1, %arg2 %B = select i1 %A, i16 %val1, i16 %val2 @@ -277,6 +446,14 @@ entry: } define i1 @icmp_sge_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_sge_setcc_i16: +; CHECK: ceqh +; CHECK: cgth +; CHECK: ilhu +; CHECK: or +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp sge i16 %arg1, %arg2 ret i1 %A @@ -289,6 +466,12 @@ entry: ;; they'll ever be generated. define i16 @icmp_slt_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_slt_select_i16: +; CHECK: ceqh +; CHECK: cgth +; CHECK: nor +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp slt i16 %arg1, %arg2 %B = select i1 %A, i16 %val1, i16 %val2 @@ -296,12 +479,26 @@ entry: } define i1 @icmp_slt_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_slt_setcc_i16: +; CHECK: ceqh +; CHECK: cgth +; CHECK: ilhu +; CHECK: nor +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp slt i16 %arg1, %arg2 ret i1 %A } define i16 @icmp_slt_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_slt_immed01_i16: +; CHECK: ceqhi +; CHECK: cgthi +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp slt i16 %arg1, 511 %B = select i1 %A, i16 %val1, i16 %val2 @@ -309,6 +506,12 @@ entry: } define i16 @icmp_slt_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_slt_immed02_i16: +; CHECK: ceqhi +; CHECK: cgthi +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp slt i16 %arg1, -512 %B = select i1 %A, i16 %val1, i16 %val2 @@ -316,6 +519,12 @@ entry: } define i16 @icmp_slt_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_slt_immed03_i16: +; CHECK: ceqhi +; CHECK: cgthi +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp slt i16 %arg1, -1 %B = select i1 %A, i16 %val1, i16 %val2 @@ -323,6 +532,10 @@ entry: } define i16 @icmp_slt_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_slt_immed04_i16: +; CHECK: lr +; CHECK-NETX: bi + entry: %A = icmp slt i16 %arg1, 32768 %B = select i1 %A, i16 %val1, i16 %val2 @@ -330,6 +543,10 @@ entry: } define i16 @icmp_sle_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_sle_select_i16: +; CHECK: cgth +; CHECK: selb $3, $5, $6, $3 + entry: %A = icmp sle i16 %arg1, %arg2 %B = select i1 %A, i16 %val1, i16 %val2 @@ -337,6 +554,13 @@ entry: } define i1 @icmp_sle_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind { +; CHECK: icmp_sle_setcc_i16: +; CHECK: cgth +; CHECK: ilhu +; CHECK: xorhi +; CHECK: iohl +; CHECK-NETX: bi + entry: %A = icmp sle i16 %arg1, %arg2 ret i1 %A diff --git a/test/CodeGen/CellSPU/icmp32.ll b/test/CodeGen/CellSPU/icmp32.ll index ccbb5f7..ea91284 100644 --- a/test/CodeGen/CellSPU/icmp32.ll +++ b/test/CodeGen/CellSPU/icmp32.ll @@ -1,14 +1,4 @@ -; RUN: llc < %s -march=cellspu > %t1.s -; RUN: grep ila %t1.s | count 6 -; RUN: grep ceq %t1.s | count 28 -; RUN: grep ceqi %t1.s | count 12 -; RUN: grep clgt %t1.s | count 16 -; RUN: grep clgti %t1.s | count 6 -; RUN: grep cgt %t1.s | count 16 -; RUN: grep cgti %t1.s | count 6 -; RUN: grep {selb\t\\\$3, \\\$6, \\\$5, \\\$3} %t1.s | count 7 -; RUN: grep {selb\t\\\$3, \\\$5, \\\$6, \\\$3} %t1.s | count 3 -; RUN: grep {selb\t\\\$3, \\\$5, \\\$4, \\\$3} %t1.s | count 20 +; RUN: llc < %s -march=cellspu | FileCheck %s target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" @@ -27,6 +17,10 @@ target triple = "spu" ; i32 integer comparisons: define i32 @icmp_eq_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_eq_select_i32: +; CHECK: ceq +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp eq i32 %arg1, %arg2 %B = select i1 %A, i32 %val1, i32 %val2 @@ -34,12 +28,22 @@ entry: } define i1 @icmp_eq_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_eq_setcc_i32: +; CHECK: ilhu +; CHECK: ceq +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp eq i32 %arg1, %arg2 ret i1 %A } define i32 @icmp_eq_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_eq_immed01_i32: +; CHECK: ceqi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp eq i32 %arg1, 511 %B = select i1 %A, i32 %val1, i32 %val2 @@ -47,6 +51,10 @@ entry: } define i32 @icmp_eq_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_eq_immed02_i32: +; CHECK: ceqi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp eq i32 %arg1, -512 %B = select i1 %A, i32 %val1, i32 %val2 @@ -54,6 +62,10 @@ entry: } define i32 @icmp_eq_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_eq_immed03_i32: +; CHECK: ceqi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp eq i32 %arg1, -1 %B = select i1 %A, i32 %val1, i32 %val2 @@ -61,6 +73,11 @@ entry: } define i32 @icmp_eq_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_eq_immed04_i32: +; CHECK: ila +; CHECK: ceq +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp eq i32 %arg1, 32768 %B = select i1 %A, i32 %val1, i32 %val2 @@ -68,6 +85,10 @@ entry: } define i32 @icmp_ne_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ne_select_i32: +; CHECK: ceq +; CHECK: selb $3, $5, $6, $3 + entry: %A = icmp ne i32 %arg1, %arg2 %B = select i1 %A, i32 %val1, i32 %val2 @@ -75,12 +96,23 @@ entry: } define i1 @icmp_ne_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ne_setcc_i32: +; CHECK: ceq +; CHECK: ilhu +; CHECK: xori +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp ne i32 %arg1, %arg2 ret i1 %A } define i32 @icmp_ne_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ne_immed01_i32: +; CHECK: ceqi +; CHECK: selb $3, $4, $5, $3 + entry: %A = icmp ne i32 %arg1, 511 %B = select i1 %A, i32 %val1, i32 %val2 @@ -88,6 +120,10 @@ entry: } define i32 @icmp_ne_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ne_immed02_i32: +; CHECK: ceqi +; CHECK: selb $3, $4, $5, $3 + entry: %A = icmp ne i32 %arg1, -512 %B = select i1 %A, i32 %val1, i32 %val2 @@ -95,6 +131,10 @@ entry: } define i32 @icmp_ne_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ne_immed03_i32: +; CHECK: ceqi +; CHECK: selb $3, $4, $5, $3 + entry: %A = icmp ne i32 %arg1, -1 %B = select i1 %A, i32 %val1, i32 %val2 @@ -102,6 +142,11 @@ entry: } define i32 @icmp_ne_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ne_immed04_i32: +; CHECK: ila +; CHECK: ceq +; CHECK: selb $3, $4, $5, $3 + entry: %A = icmp ne i32 %arg1, 32768 %B = select i1 %A, i32 %val1, i32 %val2 @@ -109,6 +154,10 @@ entry: } define i32 @icmp_ugt_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ugt_select_i32: +; CHECK: clgt +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp ugt i32 %arg1, %arg2 %B = select i1 %A, i32 %val1, i32 %val2 @@ -116,12 +165,22 @@ entry: } define i1 @icmp_ugt_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ugt_setcc_i32: +; CHECK: ilhu +; CHECK: clgt +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp ugt i32 %arg1, %arg2 ret i1 %A } define i32 @icmp_ugt_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ugt_immed01_i32: +; CHECK: clgti +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ugt i32 %arg1, 511 %B = select i1 %A, i32 %val1, i32 %val2 @@ -129,6 +188,10 @@ entry: } define i32 @icmp_ugt_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ugt_immed02_i32: +; CHECK: clgti +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ugt i32 %arg1, 4294966784 %B = select i1 %A, i32 %val1, i32 %val2 @@ -136,6 +199,10 @@ entry: } define i32 @icmp_ugt_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ugt_immed03_i32: +; CHECK: clgti +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ugt i32 %arg1, 4294967293 %B = select i1 %A, i32 %val1, i32 %val2 @@ -143,6 +210,11 @@ entry: } define i32 @icmp_ugt_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ugt_immed04_i32: +; CHECK: ila +; CHECK: clgt +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ugt i32 %arg1, 32768 %B = select i1 %A, i32 %val1, i32 %val2 @@ -150,6 +222,12 @@ entry: } define i32 @icmp_uge_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_uge_select_i32: +; CHECK: ceq +; CHECK: clgt +; CHECK: or +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp uge i32 %arg1, %arg2 %B = select i1 %A, i32 %val1, i32 %val2 @@ -157,6 +235,14 @@ entry: } define i1 @icmp_uge_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_uge_setcc_i32: +; CHECK: ceq +; CHECK: clgt +; CHECK: ilhu +; CHECK: or +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp uge i32 %arg1, %arg2 ret i1 %A @@ -169,6 +255,12 @@ entry: ;; they'll ever be generated. define i32 @icmp_ult_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ult_select_i32: +; CHECK: ceq +; CHECK: clgt +; CHECK: nor +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp ult i32 %arg1, %arg2 %B = select i1 %A, i32 %val1, i32 %val2 @@ -176,12 +268,26 @@ entry: } define i1 @icmp_ult_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ult_setcc_i32: +; CHECK: ceq +; CHECK: clgt +; CHECK: ilhu +; CHECK: nor +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp ult i32 %arg1, %arg2 ret i1 %A } define i32 @icmp_ult_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ult_immed01_i32: +; CHECK: ceqi +; CHECK: clgti +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ult i32 %arg1, 511 %B = select i1 %A, i32 %val1, i32 %val2 @@ -189,6 +295,12 @@ entry: } define i32 @icmp_ult_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ult_immed02_i32: +; CHECK: ceqi +; CHECK: clgti +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ult i32 %arg1, 4294966784 %B = select i1 %A, i32 %val1, i32 %val2 @@ -196,6 +308,12 @@ entry: } define i32 @icmp_ult_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ult_immed03_i32: +; CHECK: ceqi +; CHECK: clgti +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ult i32 %arg1, 4294967293 %B = select i1 %A, i32 %val1, i32 %val2 @@ -203,6 +321,13 @@ entry: } define i32 @icmp_ult_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ult_immed04_i32: +; CHECK: ila +; CHECK: ceq +; CHECK: clgt +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ult i32 %arg1, 32768 %B = select i1 %A, i32 %val1, i32 %val2 @@ -210,6 +335,10 @@ entry: } define i32 @icmp_ule_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ule_select_i32: +; CHECK: clgt +; CHECK: selb $3, $5, $6, $3 + entry: %A = icmp ule i32 %arg1, %arg2 %B = select i1 %A, i32 %val1, i32 %val2 @@ -217,6 +346,13 @@ entry: } define i1 @icmp_ule_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_ule_setcc_i32: +; CHECK: clgt +; CHECK: ilhu +; CHECK: xori +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp ule i32 %arg1, %arg2 ret i1 %A @@ -229,6 +365,10 @@ entry: ;; they'll ever be generated. define i32 @icmp_sgt_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_sgt_select_i32: +; CHECK: cgt +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp sgt i32 %arg1, %arg2 %B = select i1 %A, i32 %val1, i32 %val2 @@ -236,12 +376,22 @@ entry: } define i1 @icmp_sgt_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_sgt_setcc_i32: +; CHECK: ilhu +; CHECK: cgt +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp sgt i32 %arg1, %arg2 ret i1 %A } define i32 @icmp_sgt_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_sgt_immed01_i32: +; CHECK: cgti +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp sgt i32 %arg1, 511 %B = select i1 %A, i32 %val1, i32 %val2 @@ -249,6 +399,10 @@ entry: } define i32 @icmp_sgt_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_sgt_immed02_i32: +; CHECK: cgti +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp sgt i32 %arg1, 4294966784 %B = select i1 %A, i32 %val1, i32 %val2 @@ -256,6 +410,10 @@ entry: } define i32 @icmp_sgt_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_sgt_immed03_i32: +; CHECK: cgti +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp sgt i32 %arg1, 4294967293 %B = select i1 %A, i32 %val1, i32 %val2 @@ -263,6 +421,11 @@ entry: } define i32 @icmp_sgt_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_sgt_immed04_i32: +; CHECK: ila +; CHECK: cgt +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp sgt i32 %arg1, 32768 %B = select i1 %A, i32 %val1, i32 %val2 @@ -270,6 +433,12 @@ entry: } define i32 @icmp_sge_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_sge_select_i32: +; CHECK: ceq +; CHECK: cgt +; CHECK: or +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp sge i32 %arg1, %arg2 %B = select i1 %A, i32 %val1, i32 %val2 @@ -277,6 +446,14 @@ entry: } define i1 @icmp_sge_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_sge_setcc_i32: +; CHECK: ceq +; CHECK: cgt +; CHECK: ilhu +; CHECK: or +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp sge i32 %arg1, %arg2 ret i1 %A @@ -289,6 +466,12 @@ entry: ;; they'll ever be generated. define i32 @icmp_slt_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_slt_select_i32: +; CHECK: ceq +; CHECK: cgt +; CHECK: nor +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp slt i32 %arg1, %arg2 %B = select i1 %A, i32 %val1, i32 %val2 @@ -296,12 +479,26 @@ entry: } define i1 @icmp_slt_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_slt_setcc_i32: +; CHECK: ceq +; CHECK: cgt +; CHECK: ilhu +; CHECK: nor +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp slt i32 %arg1, %arg2 ret i1 %A } define i32 @icmp_slt_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_slt_immed01_i32: +; CHECK: ceqi +; CHECK: cgti +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp slt i32 %arg1, 511 %B = select i1 %A, i32 %val1, i32 %val2 @@ -309,6 +506,12 @@ entry: } define i32 @icmp_slt_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_slt_immed02_i32: +; CHECK: ceqi +; CHECK: cgti +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp slt i32 %arg1, -512 %B = select i1 %A, i32 %val1, i32 %val2 @@ -316,6 +519,12 @@ entry: } define i32 @icmp_slt_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_slt_immed03_i32: +; CHECK: ceqi +; CHECK: cgti +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp slt i32 %arg1, -1 %B = select i1 %A, i32 %val1, i32 %val2 @@ -323,6 +532,13 @@ entry: } define i32 @icmp_slt_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_slt_immed04_i32: +; CHECK: ila +; CHECK: ceq +; CHECK: cgt +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp slt i32 %arg1, 32768 %B = select i1 %A, i32 %val1, i32 %val2 @@ -330,6 +546,10 @@ entry: } define i32 @icmp_sle_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_sle_select_i32: +; CHECK: cgt +; CHECK: selb $3, $5, $6, $3 + entry: %A = icmp sle i32 %arg1, %arg2 %B = select i1 %A, i32 %val1, i32 %val2 @@ -337,6 +557,13 @@ entry: } define i1 @icmp_sle_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind { +; CHECK: icmp_sle_setcc_i32: +; CHECK: cgt +; CHECK: ilhu +; CHECK: xori +; CHECK: iohl +; CHECK: shufb + entry: %A = icmp sle i32 %arg1, %arg2 ret i1 %A diff --git a/test/CodeGen/CellSPU/icmp8.ll b/test/CodeGen/CellSPU/icmp8.ll index 5517d10..1db641e 100644 --- a/test/CodeGen/CellSPU/icmp8.ll +++ b/test/CodeGen/CellSPU/icmp8.ll @@ -1,13 +1,4 @@ -; RUN: llc < %s -march=cellspu > %t1.s -; RUN: grep ceqb %t1.s | count 24 -; RUN: grep ceqbi %t1.s | count 12 -; RUN: grep clgtb %t1.s | count 11 -; RUN: grep cgtb %t1.s | count 13 -; RUN: grep cgtbi %t1.s | count 5 -; RUN: grep {selb\t\\\$3, \\\$6, \\\$5, \\\$3} %t1.s | count 7 -; RUN: grep {selb\t\\\$3, \\\$5, \\\$6, \\\$3} %t1.s | count 3 -; RUN: grep {selb\t\\\$3, \\\$5, \\\$4, \\\$3} %t1.s | count 11 -; RUN: grep {selb\t\\\$3, \\\$4, \\\$5, \\\$3} %t1.s | count 4 +; RUN: llc < %s -march=cellspu | FileCheck %s target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" @@ -26,6 +17,10 @@ target triple = "spu" ; i8 integer comparisons: define i8 @icmp_eq_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_eq_select_i8: +; CHECK: ceqb +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp eq i8 %arg1, %arg2 %B = select i1 %A, i8 %val1, i8 %val2 @@ -33,12 +28,20 @@ entry: } define i1 @icmp_eq_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_eq_setcc_i8: +; CHECK: ceqb +; CHECK-NEXT: bi + entry: %A = icmp eq i8 %arg1, %arg2 ret i1 %A } define i8 @icmp_eq_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_eq_immed01_i8: +; CHECK: ceqbi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp eq i8 %arg1, 127 %B = select i1 %A, i8 %val1, i8 %val2 @@ -46,6 +49,10 @@ entry: } define i8 @icmp_eq_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_eq_immed02_i8: +; CHECK: ceqbi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp eq i8 %arg1, -128 %B = select i1 %A, i8 %val1, i8 %val2 @@ -53,6 +60,10 @@ entry: } define i8 @icmp_eq_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_eq_immed03_i8: +; CHECK: ceqbi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp eq i8 %arg1, -1 %B = select i1 %A, i8 %val1, i8 %val2 @@ -60,6 +71,10 @@ entry: } define i8 @icmp_ne_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_ne_select_i8: +; CHECK: ceqb +; CHECK: selb $3, $5, $6, $3 + entry: %A = icmp ne i8 %arg1, %arg2 %B = select i1 %A, i8 %val1, i8 %val2 @@ -67,12 +82,21 @@ entry: } define i1 @icmp_ne_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_ne_setcc_i8: +; CHECK: ceqb +; CHECK: xorbi +; CHECK-NEXT: bi + entry: %A = icmp ne i8 %arg1, %arg2 ret i1 %A } define i8 @icmp_ne_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_ne_immed01_i8: +; CHECK: ceqbi +; CHECK: selb $3, $4, $5, $3 + entry: %A = icmp ne i8 %arg1, 127 %B = select i1 %A, i8 %val1, i8 %val2 @@ -80,6 +104,10 @@ entry: } define i8 @icmp_ne_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_ne_immed02_i8: +; CHECK: ceqbi +; CHECK: selb $3, $4, $5, $3 + entry: %A = icmp ne i8 %arg1, -128 %B = select i1 %A, i8 %val1, i8 %val2 @@ -87,6 +115,10 @@ entry: } define i8 @icmp_ne_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_ne_immed03_i8: +; CHECK: ceqbi +; CHECK: selb $3, $4, $5, $3 + entry: %A = icmp ne i8 %arg1, -1 %B = select i1 %A, i8 %val1, i8 %val2 @@ -94,6 +126,10 @@ entry: } define i8 @icmp_ugt_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_ugt_select_i8: +; CHECK: clgtb +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp ugt i8 %arg1, %arg2 %B = select i1 %A, i8 %val1, i8 %val2 @@ -101,12 +137,20 @@ entry: } define i1 @icmp_ugt_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_ugt_setcc_i8: +; CHECK: clgtb +; CHECK-NEXT: bi + entry: %A = icmp ugt i8 %arg1, %arg2 ret i1 %A } define i8 @icmp_ugt_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_ugt_immed01_i8: +; CHECK: clgtbi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ugt i8 %arg1, 126 %B = select i1 %A, i8 %val1, i8 %val2 @@ -114,6 +158,12 @@ entry: } define i8 @icmp_uge_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_uge_select_i8: +; CHECK: ceqb +; CHECK: clgtb +; CHECK: or +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp uge i8 %arg1, %arg2 %B = select i1 %A, i8 %val1, i8 %val2 @@ -121,6 +171,12 @@ entry: } define i1 @icmp_uge_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_uge_setcc_i8: +; CHECK: ceqb +; CHECK: clgtb +; CHECK: or +; CHECK-NEXT: bi + entry: %A = icmp uge i8 %arg1, %arg2 ret i1 %A @@ -133,6 +189,12 @@ entry: ;; they'll ever be generated. define i8 @icmp_ult_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_ult_select_i8: +; CHECK: ceqb +; CHECK: clgtb +; CHECK: nor +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp ult i8 %arg1, %arg2 %B = select i1 %A, i8 %val1, i8 %val2 @@ -140,12 +202,24 @@ entry: } define i1 @icmp_ult_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_ult_setcc_i8: +; CHECK: ceqb +; CHECK: clgtb +; CHECK: nor +; CHECK-NEXT: bi + entry: %A = icmp ult i8 %arg1, %arg2 ret i1 %A } define i8 @icmp_ult_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_ult_immed01_i8: +; CHECK: ceqbi +; CHECK: clgtbi +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ult i8 %arg1, 253 %B = select i1 %A, i8 %val1, i8 %val2 @@ -153,6 +227,12 @@ entry: } define i8 @icmp_ult_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_ult_immed02_i8: +; CHECK: ceqbi +; CHECK: clgtbi +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp ult i8 %arg1, 129 %B = select i1 %A, i8 %val1, i8 %val2 @@ -160,6 +240,10 @@ entry: } define i8 @icmp_ule_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_ule_select_i8: +; CHECK: clgtb +; CHECK: selb $3, $5, $6, $3 + entry: %A = icmp ule i8 %arg1, %arg2 %B = select i1 %A, i8 %val1, i8 %val2 @@ -167,6 +251,11 @@ entry: } define i1 @icmp_ule_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_ule_setcc_i8: +; CHECK: clgtb +; CHECK: xorbi +; CHECK-NEXT: bi + entry: %A = icmp ule i8 %arg1, %arg2 ret i1 %A @@ -179,6 +268,10 @@ entry: ;; they'll ever be generated. define i8 @icmp_sgt_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_sgt_select_i8: +; CHECK: cgtb +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp sgt i8 %arg1, %arg2 %B = select i1 %A, i8 %val1, i8 %val2 @@ -186,12 +279,20 @@ entry: } define i1 @icmp_sgt_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_sgt_setcc_i8: +; CHECK: cgtb +; CHECK-NEXT: bi + entry: %A = icmp sgt i8 %arg1, %arg2 ret i1 %A } define i8 @icmp_sgt_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_sgt_immed01_i8: +; CHECK: cgtbi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp sgt i8 %arg1, 96 %B = select i1 %A, i8 %val1, i8 %val2 @@ -199,6 +300,10 @@ entry: } define i8 @icmp_sgt_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_sgt_immed02_i8: +; CHECK: cgtbi +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp sgt i8 %arg1, -1 %B = select i1 %A, i8 %val1, i8 %val2 @@ -206,6 +311,10 @@ entry: } define i8 @icmp_sgt_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_sgt_immed03_i8: +; CHECK: ceqbi +; CHECK: selb $3, $4, $5, $3 + entry: %A = icmp sgt i8 %arg1, -128 %B = select i1 %A, i8 %val1, i8 %val2 @@ -213,6 +322,12 @@ entry: } define i8 @icmp_sge_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_sge_select_i8: +; CHECK: ceqb +; CHECK: cgtb +; CHECK: or +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp sge i8 %arg1, %arg2 %B = select i1 %A, i8 %val1, i8 %val2 @@ -220,6 +335,12 @@ entry: } define i1 @icmp_sge_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_sge_setcc_i8: +; CHECK: ceqb +; CHECK: cgtb +; CHECK: or +; CHECK-NEXT: bi + entry: %A = icmp sge i8 %arg1, %arg2 ret i1 %A @@ -232,6 +353,12 @@ entry: ;; they'll ever be generated. define i8 @icmp_slt_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_slt_select_i8: +; CHECK: ceqb +; CHECK: cgtb +; CHECK: nor +; CHECK: selb $3, $6, $5, $3 + entry: %A = icmp slt i8 %arg1, %arg2 %B = select i1 %A, i8 %val1, i8 %val2 @@ -239,12 +366,24 @@ entry: } define i1 @icmp_slt_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_slt_setcc_i8: +; CHECK: ceqb +; CHECK: cgtb +; CHECK: nor +; CHECK-NEXT: bi + entry: %A = icmp slt i8 %arg1, %arg2 ret i1 %A } define i8 @icmp_slt_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_slt_immed01_i8: +; CHECK: ceqbi +; CHECK: cgtbi +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp slt i8 %arg1, 96 %B = select i1 %A, i8 %val1, i8 %val2 @@ -252,6 +391,12 @@ entry: } define i8 @icmp_slt_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_slt_immed02_i8: +; CHECK: ceqbi +; CHECK: cgtbi +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp slt i8 %arg1, -120 %B = select i1 %A, i8 %val1, i8 %val2 @@ -259,6 +404,12 @@ entry: } define i8 @icmp_slt_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_slt_immed03_i8: +; CHECK: ceqbi +; CHECK: cgtbi +; CHECK: nor +; CHECK: selb $3, $5, $4, $3 + entry: %A = icmp slt i8 %arg1, -1 %B = select i1 %A, i8 %val1, i8 %val2 @@ -266,6 +417,10 @@ entry: } define i8 @icmp_sle_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_sle_select_i8: +; CHECK: cgtb +; CHECK: selb $3, $5, $6, $3 + entry: %A = icmp sle i8 %arg1, %arg2 %B = select i1 %A, i8 %val1, i8 %val2 @@ -273,6 +428,11 @@ entry: } define i1 @icmp_sle_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind { +; CHECK: icmp_sle_setcc_i8: +; CHECK: cgtb +; CHECK: xorbi +; CHECK-NEXT: bi + entry: %A = icmp sle i8 %arg1, %arg2 ret i1 %A |