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-rw-r--r--test/MC/Disassembler/ARM/invalid-NEON-thumb.txt9
-rw-r--r--test/MC/Disassembler/ARM/invalid-VFP-thumb.txt9
2 files changed, 18 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt b/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt
new file mode 100644
index 0000000..a191d9e
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt
@@ -0,0 +1,9 @@
+# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110)
+
+# VMOV
+# RUN: echo "0x00 0xde 0x10 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# VDUP
+# RUN: echo "0xff 0xde 0xf0 0xfb" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# CHECK: invalid instruction encoding
diff --git a/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt b/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt
new file mode 100644
index 0000000..7a4ddaa
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt
@@ -0,0 +1,9 @@
+# VFP instructions with invalid predicate bits (pred != 0b1110)
+
+# VABS
+# RUN: echo "0x40 0xde 0x00 0x0a" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# VMLA
+# RUN: echo "0xf0 0xde 0xe0 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
+
+# CHECK: invalid instruction encoding