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* Reject bitcasts between address spaces with different sizesMatt Arsenault2013-07-3111-36/+219
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187506 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Implement isLegalAddressingMode()Richard Sandiford2013-07-313-3/+46
| | | | | | | | | | | The loop optimizers were assuming that scales > 1 were OK. I think this is actually a bug in TargetLoweringBase::isLegalAddressingMode(), since it seems to be trying to reject anything that isn't r+i or r+r, but it has no default case for scales other than 0, 1 or 2. Implementing the hook for z means that z can no longer test any change there though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187497 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Be more careful about inverting CC masks (conditional loads)Richard Sandiford2013-07-317-45/+45
| | | | | | | | | Extend r187495 to conditional loads. I split this out because the easiest way seemed to be to force a particular operand order in SystemZISelDAGToDAG.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187496 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Be more careful about inverting CC masksRichard Sandiford2013-07-3156-205/+286
| | | | | | | | | | | | | | | | | | | | | | | | | System z branches have a mask to select which of the 4 CC values should cause the branch to be taken. We can invert a branch by inverting the mask. However, not all instructions can produce all 4 CC values, so inverting the branch like this can lead to some oddities. For example, integer comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater). If an integer EQ is reversed to NE before instruction selection, the branch will test for 1 or 2. If instead the branch is reversed after instruction selection (by inverting the mask), it will test for 1, 2 or 3. Both are correct, but the second isn't really canonical. This patch therefore keeps track of which CC values are possible and uses this when inverting a mask. Although this is mostly cosmestic, it fixes undefined behavior for the CIJNLH in branch-08.ll. Another fix would have been to mask out bit 0 when generating the fused compare and branch, but the point of this patch is that we shouldn't need to do that in the first place. The patch also makes it easier to reuse CC results from other instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187495 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Move compare-and-branch generation even laterRichard Sandiford2013-07-315-136/+164
| | | | | | | | | | | | | | | | | | | | | | | | r187116 moved compare-and-branch generation from the instruction-selection pass to the peephole optimizer (via optimizeCompare). It turns out that even this is a bit too early. Fused compare-and-branch instructions don't interact well with predication, where a CC result is needed. They also make it harder to reuse the CC side-effects of earlier instructions (not yet implemented, but the subject of a later patch). Another problem was that the AnalyzeBranch family of routines weren't handling compares and branches, so we weren't able to reverse the fused form in cases where we would reverse a separate branch. This could have been fixed by extending AnalyzeBranch, but given the other problems, I've instead moved the fusing to the long-branch pass, which is also responsible for the opposite transformation: splitting out-of-range compares and branches into separate compares and long branches. I've added a test for the AnalyzeBranch problem. A test for the predication problem is included in the next patch, which fixes a bug in the choice of CC mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187494 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed assertion in Extract128BitVector()Elena Demikhovsky2013-07-311-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187493 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()Richard Sandiford2013-07-3133-510/+639
| | | | | | | | | | | | | | | | | | | | | | | r186399 aggressively used the RISBG instruction for immediate ANDs, both because it can handle some values that AND IMMEDIATE can't, and because it allows the destination register to be different from the source. I realized later while implementing the distinct-ops support that it would be better to leave the choice up to convertToThreeAddress() instead. The AND IMMEDIATE form is shorter and is less likely to be cracked. This is a problem for 32-bit ANDs because we assume that all 32-bit operations will leave the high word untouched, whereas RISBG used in this way will either clear the high word or copy it from the source register. The patch uses the z196 instruction RISBLG for this instead. This means that z10 will be restricted to NILL, NILH and NILF for 32-bit ANDs, but I think that should be OK for now. Although we're using z10 as the base architecture, the optimization work is going to be focused more on z196 and zEC12. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187492 91177308-0d34-0410-b5e6-96231b3b80d8
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-317-181/+855
| | | | | | | | | | All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms. Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors. Added lowering for EXTRACT/INSERT subvector for 512-bit vectors. Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187491 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add RISBLG and RISBHG instruction definitionsRichard Sandiford2013-07-318-3/+143
| | | | | | | The next patch will make use of RISBLG for codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187490 91177308-0d34-0410-b5e6-96231b3b80d8
* Add parentheses to silence gcc warning.Richard Trieu2013-07-311-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187482 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix register pressure tables on ARM.Andrew Trick2013-07-311-3/+31
| | | | | | The heuristic that merges register pressure sets was bogus for ARM's S/D regs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187479 91177308-0d34-0410-b5e6-96231b3b80d8
* Add tracing to the tblgen register pressure table generator.Andrew Trick2013-07-311-7/+63
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187478 91177308-0d34-0410-b5e6-96231b3b80d8
* Increment arg_count inside the loop in printInline. Patch by Joe Matarazzo.Craig Topper2013-07-311-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187477 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed register names (and pointer keywords) to be lower case when using ↵Craig Topper2013-07-3116-274/+269
| | | | | | | | | | Intel X86 assembler syntax. Patch by Richard Mitton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187476 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a severe compile time problem when forming large SCEV expressions.Andrew Trick2013-07-311-0/+3
| | | | | | | | | | | | This fix is very lightweight. The same fix already existed for AddRec but was missing for NAry expressions. This is obviously an improvement and I'm unsure how to test compile time problems. Patch by Xiaoyi Guo! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187475 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove trailing whitespace and some tab characters.Craig Topper2013-07-311-9/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187472 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed incorrect disassembly for MOV16o16a when using Intel syntax.Craig Topper2013-07-311-2/+2
| | | | | | | | Patch by Richard Mitton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187471 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix crashing on invalid inline asm with matching constraints.Eric Christopher2013-07-311-15/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For a testcase like the following: typedef unsigned long uint64_t; typedef struct { uint64_t lo; uint64_t hi; } blob128_t; void add_128_to_128(const blob128_t *in, blob128_t *res) { asm ("PAND %1, %0" : "+Q"(*res) : "Q"(*in)); } where we'll fail to allocate the register for the output constraint, our matching input constraint will not find a register to match, and could try to search past the end of the current operands array. On the idea that we'd like to attempt to keep compilation going to find more errors in the module, change the error cases when we're visiting inline asm IR to return immediately and avoid trying to create a node in the DAG. This leaves us with only a single error message per inline asm instruction, but allows us to safely keep going in the general case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187470 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename instruction DANDi to ANDi64.Akira Hatanaka2013-07-311-4/+4
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187469 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Define instruction itineraries IIArith and IILogic.Akira Hatanaka2013-07-315-38/+49
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187468 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ptr vector inconsistency in CreatePointerCastMatt Arsenault2013-07-312-5/+24
| | | | | | | | One form would accept a vector of pointers, and the other did not. Make both accept vectors of pointers, and add an assertion for the number of elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187464 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix windows' implementation of status when a file doesn't exist.Rafael Espindola2013-07-312-6/+15
| | | | | | | | | The unix one was returning no_such_file_or_directory, but the windows one was return success. Update the one one caller that was depending on the old behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187463 91177308-0d34-0410-b5e6-96231b3b80d8
* Preserve fast-math flags when folding (fsub x, (fneg y)) to (fadd x, y).Owen Anderson2013-07-302-4/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187462 91177308-0d34-0410-b5e6-96231b3b80d8
* Reflow this to be easier to read.Eric Christopher2013-07-301-7/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187459 91177308-0d34-0410-b5e6-96231b3b80d8
* Make these just inline, not static inline.Eric Christopher2013-07-301-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187457 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure that -gsplit-dwarf isn't passed to the linker.Eric Christopher2013-07-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187456 91177308-0d34-0410-b5e6-96231b3b80d8
* Respect address space sizes in isEliminableCastPair.Matt Arsenault2013-07-303-16/+131
| | | | | | | This avoids constant folding bitcast/ptrtoint/inttoptr combinations that have illegal bitcasts between differently sized address spaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187455 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Remove isCastable since nothing uses it now"Matt Arsenault2013-07-303-5/+79
| | | | | | Apparently dragonegg uses it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187454 91177308-0d34-0410-b5e6-96231b3b80d8
* Add capability for building with -gsplit-dwarf to the cmake build.Eric Christopher2013-07-302-0/+8
| | | | | | In limited testing this seems to work. Caveat emptor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187452 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove isCastable since nothing uses it nowMatt Arsenault2013-07-303-79/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187448 91177308-0d34-0410-b5e6-96231b3b80d8
* isKnownToBeAPowerOfTwo: Strengthen isKnownToBeAPowerOfTwo's analysis on add ↵David Majnemer2013-07-302-16/+62
| | | | | | | | | | instructions Call into ComputeMaskedBits to figure out which bits are set on both add operands and determine if the value is a power-of-two-or-zero or not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187445 91177308-0d34-0410-b5e6-96231b3b80d8
* Change behavior of calling bitcasted alias functions.Matt Arsenault2013-07-3010-83/+430
| | | | | | | | It will now only convert the arguments / return value and call the underlying function if the types are able to be bitcasted. This avoids using fp<->int conversions that would occur before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187444 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Delete instruction format for "bal".Akira Hatanaka2013-07-301-11/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187443 91177308-0d34-0410-b5e6-96231b3b80d8
* This test may have been sensitive to the ARM ABI...Andrew Trick2013-07-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187442 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement getUniqueID for directories on windows.Rafael Espindola2013-07-302-18/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187441 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias thatAkira Hatanaka2013-07-302-5/+9
| | | | | | | | turns "bal" into "bgezal". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187440 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code.Rafael Espindola2013-07-301-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187439 91177308-0d34-0410-b5e6-96231b3b80d8
* Down-scale slot index distance to save bits.Andrew Trick2013-07-302-1/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187438 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2013-07-301-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187437 91177308-0d34-0410-b5e6-96231b3b80d8
* MI Sched: Track live-thru registers.Andrew Trick2013-07-303-15/+101
| | | | | | | | | | | When registers must be live throughout the scheduling region, increase the limit for the register class. Once we exceed the original limit, they will be spilled, and there's no point further reducing pressure. This isn't a perfect heuristics but avoids a situation where the scheduler could become trapped by trying to achieve the impossible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187436 91177308-0d34-0410-b5e6-96231b3b80d8
* MI Sched fix: assert "Disconnected LRG within the scheduling region."Andrew Trick2013-07-302-1/+60
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187435 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Rewrite MBB's live-in registers for leaf functions. Also, addVenkatraman Govindaraju2013-07-302-7/+20
| | | | | | | | | | register i7 as a live-in if current function's return address is taken. This revision fixes PR16269. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187433 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement TokenizeWindowsCommandLine.Rui Ueyama2013-07-302-10/+129
| | | | | | | | | | This is a follow up patch for r187390 to implement the parser for the Windows-style command line. This should follow the rule as described at http://msdn.microsoft.com/en-us/library/windows/desktop/17w5ykft(v=vs.85).aspx Differential Revision: http://llvm-reviews.chandlerc.com/D1235 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187430 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix parameter ordering bug in createDebugIRPass()Daniel Malea2013-07-301-3/+3
| | | | | | | | - Thanks to Ilia Filippov for pointing out the inconsistency! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187424 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Expand vector fp <-> int conversionsTom Stellard2013-07-306-40/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187421 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements parsing of mips FCC register operands. The example ↵Vladimir Medic2013-07-305-14/+72
| | | | | | instructions have been added to test files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix underscore to be the proper length.Bill Wendling2013-07-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187406 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] check bitwidth in PerformORCombineSaleem Abdulrasool2013-07-302-14/+53
| | | | | | | | | | | | | | When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the bitwidth of the second operands to both ands match before comparing the negation of the values. Split the check of the value of the second operands to the ands. Move the cast and variable declaration slightly higher to make it slightly easier to follow. Bug-Id: 16700 Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187404 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove more dead documentation.Rafael Espindola2013-07-301-11/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187403 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Use call's debugloc for the unimp instruction.Venkatraman Govindaraju2013-07-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187402 91177308-0d34-0410-b5e6-96231b3b80d8
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