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* minor code style cleanup.Chris Lattner2013-03-201-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177576 91177308-0d34-0410-b5e6-96231b3b80d8
* xlC doesn't like Header being both a type and a member variable. Rename theRafael Espindola2013-03-202-20/+20
| | | | | | | | member variable. Patch by Kai <kai@redstar.de> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177575 91177308-0d34-0410-b5e6-96231b3b80d8
* Add std prefixes to fix the build with xlc.Rafael Espindola2013-03-202-2/+2
| | | | | | Patch by Kai <kai@redstar.de>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177574 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure TableGen exits with an error code after printing errors.Jakob Stoklund Olesen2013-03-203-2/+12
| | | | | | | | | | This makes it possible to report multiple errors in one invocation. There are already calls to PrintError in CodeGenDAGPatterns.cpp which previously would not cause TableGen to fail. <rdar://problem/13463339> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177573 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor file/directory path in namespace debug info to refer directly to ↵David Blaikie2013-03-204-14/+11
| | | | | | | | the pair rather than the DIFile (paired to a Clang test - excuse the buildbot skew/fallout) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177566 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance debug info namespace test to check for context/scope referenceDavid Blaikie2013-03-201-7/+16
| | | | | | | The differing file (due to the #line directive in the original source) is for future testing improvements coming soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177560 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove blank line before block comment.Eric Christopher2013-03-201-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177550 91177308-0d34-0410-b5e6-96231b3b80d8
* DIBuilder: allow linkage name to be specified for global variablesDavid Blaikie2013-03-202-4/+26
| | | | | | Patch by Kai Nacke (kai@redstar.de) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177547 91177308-0d34-0410-b5e6-96231b3b80d8
* Make target-specific test case in r177474 only run when that target is builtDavid Blaikie2013-03-203-1/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177545 91177308-0d34-0410-b5e6-96231b3b80d8
* Add timing of the IR parsing code with a new -time-ir-parsing flagEli Bendersky2013-03-203-0/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177543 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some missing SSE annotations.Jakob Stoklund Olesen2013-03-201-8/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177540 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate remaining IIC_BIN_* instructions.Jakob Stoklund Olesen2013-03-201-5/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177539 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "pre-RA-sched: fix TargetOpcode usage"Christian Konig2013-03-201-18/+12
| | | | | | | | | | | | This reverts commit 06091513c283c863296f01cc7c2e86b56bb50d02. The code is obviously wrong, but the trivial fix causes inefficient code generation on X86. Somebody with more knowledge of the code needs to take a look here. Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177529 91177308-0d34-0410-b5e6-96231b3b80d8
* Move SDNode order propagation to SDNodeOrdering, which also fixes a missedJustin Holewinski2013-03-204-23/+15
| | | | | | | | case of order propagation during isel. Thanks Owen for the suggestion! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177525 91177308-0d34-0410-b5e6-96231b3b80d8
* pre-RA-sched: fix TargetOpcode usageChristian Konig2013-03-201-12/+18
| | | | | | | | TargetOpcodes need to be treaded as Machine- and not ISD-Opcodes. Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177518 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a silly search-and-replace goof with r177495 that only brokeChandler Carruth2013-03-201-1/+1
| | | | | | non-release builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177498 91177308-0d34-0410-b5e6-96231b3b80d8
* [SROA] Don't preserve the IR names in release builds.Chandler Carruth2013-03-201-28/+37
| | | | | | | | | | | This is espcially important because the new SROA pass goes to great lengths to provide helpful names for debugging, and as a consequence they can become very slow to render. Good for between 5% and 15% of the SROA runtime on some slow test cases such as the one in PR15412. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177495 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the endif to the correct line so we don't have warnings aboutChandler Carruth2013-03-201-1/+1
| | | | | | unused statistics variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177494 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce some new statistics to help track the exact behavior of theChandler Carruth2013-03-201-4/+20
| | | | | | new SROA pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177493 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorder the DIFile parameter in DINameSpaceDavid Blaikie2013-03-203-6/+7
| | | | | | | | Moving the DIFile parameter to immediately proceed the tag so that it will be a common prefix with other DIScopes (once the DIFile is replaced with the raw file/directory pair). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177492 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test case for PR15318 fixed in r177472Hao Liu2013-03-201-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177489 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't assume the test directory is writable, use %T to find a writableNick Lewycky2013-03-202-8/+8
| | | | | | | directory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177488 91177308-0d34-0410-b5e6-96231b3b80d8
* Test DW_TAG_namespace support in the backendDavid Blaikie2013-03-201-0/+25
| | | | | | | | This is the backend portion of a Clang test case (clang/test/CodeGenCXX/debug-info-namespace.cpp) that was roughly/coarsely testing LLVM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177487 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide more details for DINameSpace debug info in the IR comment annotationsDavid Blaikie2013-03-202-0/+12
| | | | | | | Sorry for the version skew - I should've committed this before the corresponding Clang test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177486 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR15296Michael Liao2013-03-202-119/+245
| | | | | | | | | - Move SRA/SRL/SHL lowering support from DAG combination to DAG lowering to support extended 256-bit integer in AVX but not AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177478 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark all variable shifts needing customizingMichael Liao2013-03-201-28/+29
| | | | | | | | | - Prepare moving logic from DAG combining into DAG lowering. There's no functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177477 91177308-0d34-0410-b5e6-96231b3b80d8
* Move scalar immediate shift lowering into a dedicated funcMichael Liao2013-03-201-5/+20
| | | | | | | | - no functionality change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177476 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test case regression on ARM & PPC introduced r177239David Blaikie2013-03-201-4/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177474 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix AsmPrinter crashes with assertion. Bug 15318 in BugzillaHao Liu2013-03-201-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177472 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor the DIFile (2nd) parameter to DITypes to be an MDNode reference to ↵David Blaikie2013-03-2043-265/+261
| | | | | | | | | a raw directory/file pair This makes DIType's first non-tag parameter the same as DIFile's, allowing them to both share the common implementation of getFilename/getDirectory in DIScope. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177467 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate DAG node ordering during type legalization and instruction selectionJustin Holewinski2013-03-207-16/+120
| | | | | | | | A node's ordering is only propagated during legalization if (a) the new node does not have an ordering (is not a CSE'd node), or (b) the new node has an ordering that is higher than the node being legalized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177465 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr13145 - Naming a function like a register name confuses the asm parser.Chad Rosier2013-03-192-14/+25
| | | | | | | Patch by Stepan Dyatkovskiy <stpworld@narod.ru> rdar://13457826 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177463 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the DIFile operand to DITypes from the 4th operand to the 2nd.David Blaikie2013-03-1955-430/+402
| | | | | | | | This is another step along the way to making all DIScopes have a common prefix which can be added to in a general manner to support using directives (DW_TAG_imported_module). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177462 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate various null idioms with SchedRW lists.Jakob Stoklund Olesen2013-03-191-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177461 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate SSE float conversions with SchedRW lists.Jakob Stoklund Olesen2013-03-191-60/+81
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177460 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate X86InstrCMovSetCC.td with SchedRW lists.Jakob Stoklund Olesen2013-03-191-4/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177459 91177308-0d34-0410-b5e6-96231b3b80d8
* Formatting fixups.Eric Christopher2013-03-191-14/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177458 91177308-0d34-0410-b5e6-96231b3b80d8
* Dead code.Chad Rosier2013-03-191-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177451 91177308-0d34-0410-b5e6-96231b3b80d8
* Dead code.Chad Rosier2013-03-191-6/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177450 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Move the immediate asm rewrite into the target specificChad Rosier2013-03-192-15/+5
| | | | | | | logic as a QOI cleanup. No functional change. Tests already in place. rdar://13456414 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177446 91177308-0d34-0410-b5e6-96231b3b80d8
* Update global merge pass according to Duncan's advices:Quentin Colombet2013-03-191-8/+7
| | | | | | | | | - Remove useless includes - Change misleading comments - Move code into doFinalization git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177445 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate X86InstrCompiler.td with SchedRW lists.Jakob Stoklund Olesen2013-03-192-8/+13
| | | | | | | Add a new WriteZero SchedWrite type for the common dependency-breaking instructions that clear a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177442 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Remove the brackets from X86Operand in the IR. These will beChad Rosier2013-03-191-8/+19
| | | | | | | | | | | | | | | | | | | | added back in by X86AsmPrinter::printIntelMemReference() during codegen. Previously, this following example void t() { int i; __asm mov eax, [i] } would generate the below assembly mov eax, dword ptr [[eax]] which resulted in a fatal error when compiling. Test case coming on the clang side. rdar://13444264 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177440 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Create a helper function, CreateMemForInlineAsm, that createsChad Rosier2013-03-191-36/+49
| | | | | | | | | | an X86Operand, but also performs a Sema lookup and adds the sizing directive when appropriate. Use this when parsing a bracketed statement. This is necessary to get the instruction matching correct as well. Test case coming on clang side. rdar://13455408 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177439 91177308-0d34-0410-b5e6-96231b3b80d8
* Register the GCOV writeout functions so that they're emitted serially.Bill Wendling2013-03-191-10/+31
| | | | | | | | | | We don't want to write out >1000 files at the same time. That could make things prohibitively expensive. Instead, register the "writeout" function so that it's emitted serially. <rdar://problem/12439551> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177437 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a comment to the CodeGen/PowerPC/asym-regclass-copy.ll testHal Finkel2013-03-191-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177434 91177308-0d34-0410-b5e6-96231b3b80d8
* IndVarSimplify: do not recompute an IV value outside of the loop if :Arnaud A. de Grandmaison2013-03-192-0/+108
| | | | | | | - it is trivially known to be used inside the loop in a way that can not be optimized away - there is no use outside of the loop which can take advantage of the computation hoisting git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177432 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing mayLoad flag to LHAUX8 and LWAUX.Ulrich Weigand2013-03-191-1/+2
| | | | | | | | | | | All pre-increment load patterns need to set the mayLoad flag (since they don't provide a DAG pattern). This was missing for LHAUX8 and LWAUX, which is added by this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177431 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite LHAU8 pattern to use standard memory operand.Ulrich Weigand2013-03-191-4/+4
| | | | | | | | | | | | | | As opposed to to pre-increment store patterns, the pre-increment load patterns were already using standard memory operands, with the sole exception of LHAU8. As there's no real reason why LHAU8 should be different here, this patch simply rewrites the pattern to also use a memri operand, just like all the other patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177430 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite pre-increment store patterns to use standard memory operands.Ulrich Weigand2013-03-193-151/+291
| | | | | | | | | | | | | | | | | | | | | | | | Currently, pre-increment store patterns are written to use two separate operands to represent address base and displacement: stwu $rS, $ptroff($ptrreg) This causes problems when implementing the assembler parser, so this commit changes the patterns to use standard (complex) memory operands like in all other memory access instruction patterns: stwu $rS, $dst To still match those instructions against the appropriate pre_store SelectionDAG nodes, the patch uses the new feature that allows a Pat to match multiple DAG operands against a single (complex) instruction operand. Approved by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177429 91177308-0d34-0410-b5e6-96231b3b80d8
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