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* Remove an unneeded call to 'UpdateThumbVFPPredicate', spotted by Amaury.Joey Gouly2013-07-041-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185651 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} ↵Joey Gouly2013-07-046-2/+137
| | | | | | | | | | instructions. This adds a new decoder table/namespace 'VFPV8', as these instructions have their top 4 bits as 0b1111, while other Thumb instructions have 0b1110. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185642 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add all trap mnemonicsUlrich Weigand2013-07-043-2/+180
| | | | | | | | | This adds support for all basic and extended variants of the trap instructions to the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185638 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add asm parser support for CR expressionsUlrich Weigand2013-07-043-6/+183
| | | | | | | | | | This adds support for specifying condition registers and condition register fields via expressions using the symbols defined by the PowerISA, like "4*cr2+eq". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185633 91177308-0d34-0410-b5e6-96231b3b80d8
* SimplifyCFG: Teach switch generation some patterns that instcombine forms.Benjamin Kramer2013-07-042-1/+63
| | | | | | | | This allows us to create switches even if instcombine has munged two of the incombing compares into one and some bit twiddling. This was motivated by enum compares that are common in clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185632 91177308-0d34-0410-b5e6-96231b3b80d8
* Supporting ssize_t on WIN64 with its proper size. Patch thanks to David ↵Aaron Ballman2013-07-042-2/+11
| | | | | | Cournapeau! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185627 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-0410-60/+0
| | | | | | These exception-related opcodes are not used any longer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.Joey Gouly2013-07-046-1/+125
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185620 91177308-0d34-0410-b5e6-96231b3b80d8
* Typo.Jakob Stoklund Olesen2013-07-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185618 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify landing pad lowering.Jakob Stoklund Olesen2013-07-043-26/+26
| | | | | | | | | | | | | | | | | | | | | Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering landing pad arguments. These nodes were previously legalized into CopyFromReg nodes, but that never worked properly because the CopyFromReg node weren't guaranteed to be scheduled at the top of the basic block. This meant the exception pointer and selector registers could be clobbered before being copied to a virtual register. This patch copies the two physical registers to virtual registers at the beginning of the basic block, and lowers the landingpad instruction directly to two CopyFromReg nodes reading the *virtual* registers. This is safe because virtual registers don't get clobbered. A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185617 91177308-0d34-0410-b5e6-96231b3b80d8
* FastISel can only apend to basic blocks.Jakob Stoklund Olesen2013-07-041-8/+5
| | | | | | | | | | Compute the insertion point from the end of the basic block instead of skipping labels from the front. This caused failures in landing pads when live-in copies where inserted before instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185616 91177308-0d34-0410-b5e6-96231b3b80d8
* Live-in copies go *after* EH_LABELs.Jakob Stoklund Olesen2013-07-041-1/+1
| | | | | | This will soon be tested by exception handling working at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185615 91177308-0d34-0410-b5e6-96231b3b80d8
* Tabs to spaces. No functionality change.Nick Lewycky2013-07-041-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185612 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a space between closing template '>' to unbreak build.Craig Topper2013-07-041-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185607 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-0429-65/+65
| | | | | | specifying the vector size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185606 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r185601 with a fix for the cmake build.Eric Christopher2013-07-046-1/+137
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185605 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert 185601 as it caused cmake build regressions.Eric Christopher2013-07-045-131/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185603 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for futimens for platforms that don't support futimes.Eric Christopher2013-07-045-1/+131
| | | | | | Patch by pashev.igor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185601 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-0413-26/+86
| | | | | | | Revert "Simplify landing pad lowering." Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-0310-60/+0
| | | | | | These exception-related opcodes are not used any longer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify landing pad lowering.Jakob Stoklund Olesen2013-07-033-26/+26
| | | | | | | | | | | | | | | | | | | | | Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering landing pad arguments. These nodes were previously legalized into CopyFromReg nodes, but that never worked properly because the CopyFromReg node weren't guaranteed to be scheduled at the top of the basic block. This meant the exception pointer and selector registers could be clobbered before being copied to a virtual register. This patch copies the two physical registers to virtual registers at the beginning of the basic block, and lowers the landingpad instruction directly to two CopyFromReg nodes reading the *virtual* registers. This is safe because virtual registers don't get clobbered. A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185595 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MachineBasicBlock::addLiveIn().Jakob Stoklund Olesen2013-07-032-0/+38
| | | | | | | This function adds a live-in physical register to an MBB and ensures that it is copied to a virtual register immediately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185594 91177308-0d34-0410-b5e6-96231b3b80d8
* Have ARMBaseRegisterInfo::getCallPreservedMask return the 'correct' mask for ↵Stephen Lin2013-07-032-10/+13
| | | | | | | | | the GHC calling convention. This is purely academic because GHC calls are always tail calls so the register mask will never be used; however, this change makes the code clearer and brings the ARM implementation of the GHC calling convention in line with the X86 implementation. Also, it might save someone else some time trying to figuring out what is happening... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185592 91177308-0d34-0410-b5e6-96231b3b80d8
* Hoist all of the Entry.getLoc() calls int a single variable.Eric Christopher2013-07-031-7/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185589 91177308-0d34-0410-b5e6-96231b3b80d8
* Make DotDebugLocEntry a class, reorder the members along with commentsEric Christopher2013-07-032-14/+29
| | | | | | for them and update all uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185588 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Improve the instruction selection of vector loads.Quentin Colombet2013-07-033-1/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In the ARM back-end, build_vector nodes are lowered to a target specific build_vector that uses floating point type. This works well, unless the inserted bitcasts survive until instruction selection. In that case, they incur moves between integer unit and floating point unit that may result in inefficient code. In other words, this conversion may introduce artificial dependencies when the code leading to the build vector cannot be completed with a floating point type. In particular, this happens when loads are not aligned. Before this patch, in that case, the compiler generates general purpose loads and creates the floating point vector from them, instead of directly using the vector unit. The patch uses a vector friendly sequence of code when the inserted bitcasts to floating point survived DAGCombine. This is done by a target specific DAGCombine that changes the target specific build_vector into a sequence of insert_vector_elt that get rid of the bitcasts. <rdar://problem/14170854> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185587 91177308-0d34-0410-b5e6-96231b3b80d8
* Elaborate on comment.Eric Christopher2013-07-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185586 91177308-0d34-0410-b5e6-96231b3b80d8
* Add names to the header file since they help in documenting the APIEric Christopher2013-07-031-10/+11
| | | | | | (and for consistency). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185585 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] FreeBSD does not require f128 in its data layout string.Bill Schmidt2013-07-031-1/+1
| | | | | | | Long double is 64 bits on FreeBSD PPC, so the f128 entry is superfluous. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185583 91177308-0d34-0410-b5e6-96231b3b80d8
* Add platform specific tests docRenato Golin2013-07-031-0/+60
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185581 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying ↵Tilmann Scheller2013-07-032-9/+7
| | | | | | | | | | | | | | | | certain Thumb2 add immediate T3 encodings. Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding. The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process. This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly. Fixes <rdar://problem/14224440>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185575 91177308-0d34-0410-b5e6-96231b3b80d8
* Move typedefs inside the class that they belong to.Eric Christopher2013-07-031-10/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185573 91177308-0d34-0410-b5e6-96231b3b80d8
* Use an RWMutex instead of a Mutex in PassRegistry.Chad Rosier2013-07-031-10/+11
| | | | | | | Patch by Alex Crichton <alex@crichton.co>. Approved by Chris Lattner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185566 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support lmw/stmw in the asm parserUlrich Weigand2013-07-032-1/+14
| | | | | | | | | This adds support for the load/store multiple instructions, currently used by the asm parser only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185564 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Use mtocrf when availableUlrich Weigand2013-07-0310-25/+54
| | | | | | | | | | | | | | | | | | | | | | Just as with mfocrf, it is also preferable to use mtocrf instead of mtcrf when only a single CR register is to be written. Current code however always emits mtcrf. This probably does not matter when using an external assembler, since the GNU assembler will in fact automatically replace mtcrf with mtocrf when possible. It does create inefficient code with the integrated assembler, however. To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and uses those instead of MTCRF/MTCRF8 everything. Just as done in the MFOCRF patch committed as 185556, these patterns will be converted back to MTCRF if MTOCRF is not available on the machine. As a side effect, this allows to modify the MTCRF pattern to accept the full range of mask operands for the benefit of the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Always use mfocrf if availableUlrich Weigand2013-07-039-65/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When accessing just a single CR register, it is always preferable to use mfocrf instead of mfcr, if the former is available on the CPU. Current code makes that distinction in many, but not all places where a single CR register value is retrieved. One missing location is PPCRegisterInfo::lowerCRSpilling. To fix this and make this simpler in the future, this patch changes the bulk of the back-end to always assume mfocrf is available and simply generate it when needed. On machines that actually do not support mfocrf, the instruction is replaced by mfcr at the very end, in EmitInstruction. This has the additional benefit that we no longer need the MFCRpseud hack, since before EmitInstruction we always have a MFOCRF instruction pattern, which already models data flow as required. The patch also adds the MFOCRF8 version of the instruction, which was missing so far. Except for the PPCRegisterInfo::lowerCRSpilling case, no change in generated code intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185556 91177308-0d34-0410-b5e6-96231b3b80d8
* Prefix failing commands with not to make clear they are expected to fail.Rafael Espindola2013-07-0326-30/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185554 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove another old test.Rafael Espindola2013-07-031-99/+0
| | | | | | | It was only passing because 'grep andpd' was not finding any andpd, but we don't fail if part of a pipe fails. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185552 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove test for the old EH system. It doesn't parse anymore.Rafael Espindola2013-07-031-19/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185551 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test: It was missing run lines and llvm-dis has no -disable-verify option.Rafael Espindola2013-07-031-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185550 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for gnu archives with a string table and no symtab.Rafael Espindola2013-07-033-27/+60
| | | | | | While there, use early returns to reduce nesting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185547 91177308-0d34-0410-b5e6-96231b3b80d8
* Make llvm-nm return 1 on error.Rafael Espindola2013-07-032-0/+25
| | | | | | | This is a small compatibility improvement with gnu nm and makes llvm-nm more useful as a testing tool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185546 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Remove dead code from PPCDAGToDAGISel::SelectSETCCUlrich Weigand2013-07-031-23/+5
| | | | | | | | | | | | | | | | | | The subroutine getCRIdxForSetCC has a parameter "Other" and comment: If this returns with Other != -1, then the returned comparison is an or of two simpler comparisons. However for at least the last five years this routine has never returned a value of Other != -1; these cases are now handled differently to begin with. This patch removes the parameter and the code in SelectSETCC that attempted to handle the Other != -1 case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185541 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-0311-35/+35
| | | | | | specifying the vector size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185540 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix regular expression used by 'make update' to only look for 'I' and '?' at ↵Craig Topper2013-07-031-1/+1
| | | | | | | | | | the start of svn info results and to check for spaces after 'I' instead of just after '?'. Previously it was able to match 'I' anywhere in the filenames of the svn info results instead of just files that where ignored or unknown to svn. This would cause 'make update' to infinitely recurse if a file was modified with I anywhere in its name since svn info would return a Path pointing to the llvm root for those files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185539 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Unpoison stack allocations and undef values in blacklisted functions.Evgeniy Stepanov2013-07-032-10/+49
| | | | | | | | | This changes behavior of -msan-poison-stack=0 flag from not poisoning stack allocations to actively unpoisoning them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185538 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Make specialized AltiVec patterns isCodeGenOnlyUlrich Weigand2013-07-031-2/+3
| | | | | | | | | | | | | A couple of AltiVec patterns are just specialized forms of the generic instruction pattern, and should therefore be marked isCodeGenOnly to avoid confusing the asm parser: VCFSX_0, VCTUXS_0, VCFUX_0, VCTSXS_0, and V_SETALLONES. Noticed by inspection of the generated PPCGenAsmMatcher.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185533 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support mtspr/mfspr in the asm parserUlrich Weigand2013-07-034-15/+28
| | | | | | | | | | | This adds support for the generic forms of mtspr/mfspr for the asm parser. The compiler will continue to use the specialized patters for mtlr etc. since those are needed to correctly describe data flow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185532 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Fold more spillsRichard Sandiford2013-07-0360-251/+4023
| | | | | | | | | | | | | | | | Add a mapping from register-based <INSN>R instructions to the corresponding memory-based <INSN>. Use it to cut down on the number of spill loads. Some instructions extend their operands from smaller fields, so this required a new TSFlags field to say how big the unextended operand is. This optimisation doesn't trigger for C(G)R and CL(G)R because in practice we always combine those instructions with a branch. Adding a test for every other case probably seems excessive, but it did catch a missed optimisation for DSGF (fixed in r185435). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185529 91177308-0d34-0410-b5e6-96231b3b80d8
* This corrects the implementation of Thumb ADR instruction. There are three ↵Mihai Popa2013-07-039-14/+62
| | | | | | | | | | | issues: 1. it should accept only 4-byte aligned addresses 2. the maximum offset should be 1020 3. it should be encoded with the offset scaled by two bits git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185528 91177308-0d34-0410-b5e6-96231b3b80d8
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