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* fix one more fp80 case (used only by Interpreter)Dale Johannesen2009-03-241-21/+5
| | | | | | | | and streamline code here a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67636 91177308-0d34-0410-b5e6-96231b3b80d8
* two changes:Chris Lattner2009-03-242-45/+36
| | | | | | | | | | | | 1. Make instcombine always canonicalize trunc x to i1 into an icmp(x&1). This exposes the AND to other instcombine xforms and is more of what the code generator expects. 2. Rewrite the remaining trunc pattern match to use 'match', which simplifies it a lot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67635 91177308-0d34-0410-b5e6-96231b3b80d8
* Change JIT for different layout of fp80.Dale Johannesen2009-03-241-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67629 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a testcase for the scheduling heuristic introduced in r67586.Dan Gohman2009-03-241-0/+242
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67622 91177308-0d34-0410-b5e6-96231b3b80d8
* more tidying: name the components of PhysReg in the case whenChris Lattner2009-03-241-8/+9
| | | | | | | the target constraint specifies a specific physreg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67618 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy a bit more.Chris Lattner2009-03-241-3/+3
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* simplify this code a bit now that "allocation to a vreg class" can neverChris Lattner2009-03-241-16/+13
| | | | | | | fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67616 91177308-0d34-0410-b5e6-96231b3b80d8
* I was convinced that it's ok to allow a second i8 return valueDan Gohman2009-03-241-7/+8
| | | | | | | | | | | | to be returned in DL. LLVM's multiple-return-value support is not ABI-conforming; front-ends that wish to have code emitted that conforms to an ABI are currently expected to make arrangements for this on their own rather than assuming that multiple-return-values will automatically do the right thing. This commit doesn't fundamentally change this situation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67588 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor compile-time optimization; don't bother checkingDan Gohman2009-03-241-1/+1
| | | | | | | | canClobberPhysRegDefs if the successor node doesn't clobber any physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67587 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a pre-pass to the burr-list scheduler which makes adjustments toDan Gohman2009-03-241-0/+120
| | | | | | | | | | help out the register pressure reduction heuristics in the case of nodes with multiple uses. Currently this uses very conservative heuristics, so it doesn't have a broad impact, but in cases where it does help it can make a big difference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67586 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not emit comments unless -asm-verbose.Evan Cheng2009-03-2410-134/+229
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67580 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a SmallPtrSet instead of std::set.Dale Johannesen2009-03-232-4/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67578 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in spill weight computation. If the alias is a super-register, and ↵Evan Cheng2009-03-232-7/+57
| | | | | | | | | | | | the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases. e.g. allocating for GR32, bh is not used, updating bl spill weight. bl should get the same spill weight otherwise it will be choosen as a spill candidate since spilling bh doesn't make ebx available. This fix PR2866. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67574 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sanity check in Clang TableGen backend to check if 'Component' is a string.Ted Kremenek2009-03-231-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67565 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix internal representation of fp80 to be theDale Johannesen2009-03-239-27/+97
| | | | | | | | | | | | same as a normal i80 {low64, high16} rather than its own {high64, low16}. A depressing number of places know about this; I think I got them all. Bitcode readers and writers convert back to the old form to avoid breaking compatibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67562 91177308-0d34-0410-b5e6-96231b3b80d8
* README.txt: test commit w/blank line appendedJohn Mosby2009-03-231-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67560 91177308-0d34-0410-b5e6-96231b3b80d8
* When unfolding a load during scheduling, the new operator node hasDan Gohman2009-03-231-3/+6
| | | | | | | | | | | a data dependency on the load node, so it really needs a data-dependence edge to the load node, even if the load previously existed. And add a few comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67554 91177308-0d34-0410-b5e6-96231b3b80d8
* Update test for pr3864.Evan Cheng2009-03-231-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67545 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR3391 and PR3864. Reg allocator infinite looping.Evan Cheng2009-03-234-8/+59
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67544 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't set SUnit::hasPhysRegDefs to true unless the defs areDan Gohman2009-03-231-1/+4
| | | | | | | actually have uses, which reflects the way it's used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67540 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix canClobberPhysRegDefs to check all SDNodes grouped togetherDan Gohman2009-03-231-14/+19
| | | | | | | | in an SUnit, instead of just the first one. This fix is needed by some upcoming scheduler changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67531 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new bit to SUnit to record whether a node has implicit physregDan Gohman2009-03-232-3/+10
| | | | | | | defs, regardless of whether they are actually used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67528 91177308-0d34-0410-b5e6-96231b3b80d8
* Now that errs() is properly non-buffered, there's no need toDan Gohman2009-03-237-11/+5
| | | | | | | explicitly flush it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67526 91177308-0d34-0410-b5e6-96231b3b80d8
* Clarify a comment.Dan Gohman2009-03-231-1/+1
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* LoopVR is not CFGOnly.Dan Gohman2009-03-231-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67524 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance LiveValues to work on PHI operands.Dan Gohman2009-03-231-13/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67523 91177308-0d34-0410-b5e6-96231b3b80d8
* Make getOperandNumForIncomingValue and getOperandNumForIncomingBlockDan Gohman2009-03-231-2/+10
| | | | | | | | | static member functions, and add getIncomingValueNumForOperand and getIncomingBlockNumForOperand, which are the respective inverses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67522 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct some comments. Operand numbers start at 0.Dan Gohman2009-03-231-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67518 91177308-0d34-0410-b5e6-96231b3b80d8
* Model inline asm constraint which ties an input to an output register as ↵Evan Cheng2009-03-2310-53/+144
| | | | | | machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67512 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not fold away subreg_to_reg if the source register has a sub-register ↵Evan Cheng2009-03-232-3/+34
| | | | | | | | | | | index. That means the source register is taking a sub-register of a larger register. e.g. On x86 %RAX<def> = ... %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3 The first def is defining RAX, not EAX so the top bits were not zero-extended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67511 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a bug Alexei Svitkine pointed out.Chris Lattner2009-03-231-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67510 91177308-0d34-0410-b5e6-96231b3b80d8
* When we restore signal handlers, restore them back to what theyChris Lattner2009-03-231-8/+30
| | | | | | | | were when we came around, not to their default handler. This should fix PR3848 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67509 91177308-0d34-0410-b5e6-96231b3b80d8
* factorize signal registration, part of PR3848.Chris Lattner2009-03-231-10/+23
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* Fix a grammaro in a comment that Bill noticed.Dan Gohman2009-03-231-1/+1
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* tt'ify.Chris Lattner2009-03-231-2/+2
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* VC++ 6.0 is not future work :)Chris Lattner2009-03-231-64/+5
| | | | | | | Do not recommend llvm::OStream anymore. Use raw_ostream or MemoryBuffer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67504 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comments explaining why there's only one register forDan Gohman2009-03-231-1/+6
| | | | | | | i8 return values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67502 91177308-0d34-0410-b5e6-96231b3b80d8
* Missed this as part of r67451.Evan Cheng2009-03-231-20/+22
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* Fix PR3860 by correcting a predicate.Chris Lattner2009-03-221-8/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67473 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some explanations of how apint loads and storesDuncan Sands2009-03-221-2/+15
| | | | | | | work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67471 91177308-0d34-0410-b5e6-96231b3b80d8
* Really should pass -dylib to the linker...Bill Wendling2009-03-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67469 91177308-0d34-0410-b5e6-96231b3b80d8
* A dylib should be built as a dylib and not a bundle.Bill Wendling2009-03-221-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67468 91177308-0d34-0410-b5e6-96231b3b80d8
* add method to access a template argument.Chris Lattner2009-03-221-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67458 91177308-0d34-0410-b5e6-96231b3b80d8
* Factorize out a concept - no functionality change.Duncan Sands2009-03-214-8/+15
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* Re-commit r67334 and r67349 with fix.Evan Cheng2009-03-214-9/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67451 91177308-0d34-0410-b5e6-96231b3b80d8
* add a fastpath to ConstantExpr::getBitCast to handle the case when an obviouslyChris Lattner2009-03-211-0/+5
| | | | | | | | | | unneeded bitcast is requested. This is common for frontends who just unconditionally cast even if the target is often the right type already. THis prevents going into getFoldedCast which switches on the opcode and does a bunch of other stuff before doing the same opzn. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67435 91177308-0d34-0410-b5e6-96231b3b80d8
* add some inline methods for infix operators on sparse vectors,Chris Lattner2009-03-212-13/+41
| | | | | | | tidy some df iteration stuff, patch by John Mosby! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67428 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed AFGR32 register classBruno Cardoso Lopes2009-03-215-176/+110
| | | | | | | | Handle odd registers allocation in FGR32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67422 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a few more indentation problems and an 80-column violation.Bob Wilson2009-03-201-8/+8
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* No functional changes. Fix indentation and whitespace only.Bob Wilson2009-03-201-101/+91
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67412 91177308-0d34-0410-b5e6-96231b3b80d8
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