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* This reverts 192447 because of compiler warning generated on darwin build.Matheus Almeida2013-10-114-189/+14
* This reverts r192449 because of compiler warning generated on darwin build.Matheus Almeida2013-10-113-157/+31
* [mips][msa] Direct Object Emission for the majority of the ELM instructions.Matheus Almeida2013-10-113-31/+157
* [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.Matheus Almeida2013-10-114-14/+189
* [mips][msa] Improves robustness of the test by enhancing pattern matching.Matheus Almeida2013-10-111-240/+360
* [NVPTX] Switch from StrongPHIElimination to PHIElimination in NVPTXTargetMach...Justin Holewinski2013-10-112-2/+60
* Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom ...Justin Holewinski2013-10-115-20/+54
* [ARM] Add a test case for disabled neon/fpu features.Amara Emerson2013-10-111-0/+33
* [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from no...Daniel Sanders2013-10-113-16/+193
* [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not in...Daniel Sanders2013-10-113-4/+51
* XCore target fix bug in emitArrayBound() causing segmentation faultRobert Lytton2013-10-113-7/+13
* XCore target does not emit '.hidden' or '.protected' attributesRobert Lytton2013-10-112-0/+14
* XCore target: fix bug in XCoreLowerThreadLocal.cppRobert Lytton2013-10-112-10/+60
* XCore target: add XCoreTargetLowering::isZExtFree()Robert Lytton2013-10-113-0/+37
* [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not in...Daniel Sanders2013-10-113-4/+51
* [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] ...Daniel Sanders2013-10-113-12/+143
* Remove another unnecessary filter from the disassembler.Craig Topper2013-10-111-3/+0
* LiveRangeCalc.h: Update a description corresponding to r192396. [-Wdocumentat...NAKAMURA Takumi2013-10-111-1/+1
* Implement aarch64 neon instruction set AdvSIMD (copy).Kevin Qin2013-10-116-56/+875
* Fix typoMatt Arsenault2013-10-101-2/+2
* Tests: Do not unnecessarily depend on kill commentsMatthias Braun2013-10-101-9/+4
* Tests: Use CHECK-LABEL where possibleMatthias Braun2013-10-104-15/+15
* Print register in LiveInterval::print()Matthias Braun2013-10-107-23/+28
* Represent RegUnit liveness with LiveRange instanceMatthias Braun2013-10-1013-129/+132
* Work on LiveRange instead of LiveInterval where possibleMatthias Braun2013-10-106-69/+63
* Change MachineVerifier to work on LiveRange + LiveIntervalMatthias Braun2013-10-101-92/+117
* Pass LiveQueryResult by valueMatthias Braun2013-10-1010-117/+125
* Refactor LiveInterval: introduce new LiveRange classMatthias Braun2013-10-104-217/+235
* Rename LiveRange to LiveInterval::SegmentMatthias Braun2013-10-1016-369/+366
* Rename parameter: defined regs are not incoming.Matthias Braun2013-10-102-18/+17
* test commitSriram Murali2013-10-101-2/+4
* Use getPointerSizeInBits() rather than 8 * getPointerSize()Matt Arsenault2013-10-101-2/+3
* Fix grammar / missing wordsMatt Arsenault2013-10-101-2/+3
* Debug Info: In DIBuilder, the context field of subprogram is updated to useManman Ren2013-10-108-12/+56
* Add comments to debug info testing case.Manman Ren2013-10-101-0/+8
* R600: Fix trunc i64 to i32 on SIMatt Arsenault2013-10-102-0/+17
* Provide msbuild integration for vs2013.Hans Wennborg2013-10-104-1/+49
* Fix msbuild integration install script.Hans Wennborg2013-10-101-2/+5
* R600/SI: Implement SIInstrInfo::verifyInstruction() for VOP*Tom Stellard2013-10-105-4/+142
* R600/SI: Use -verify-machineinstrs for most testsTom Stellard2013-10-1084-86/+86
* R600/SI: Define a separate MIMG instruction for each possible output value typeTom Stellard2013-10-105-35/+90
* R600/SI: Mark the EXEC register as reservedTom Stellard2013-10-101-0/+1
* R600: Use StructurizeCFGPass for non SI targetsTom Stellard2013-10-106-2/+18
* Implement AArch64 vector load/store multiple N-element structure class SIMD(l...Hao Liu2013-10-1015-3/+2827
* Revert "Implement AArch64 vector load/store multiple N-element structure clas...Rafael Espindola2013-10-1015-2808/+3
* Implement AArch64 vector load/store multiple N-element structure class SIMD(l...Hao Liu2013-10-1015-3/+2808
* ARM: Put isV8EligibleForIT into the llvm namespace. While there make it inline.Benjamin Kramer2013-10-101-2/+4
* Disable function padding to get this test to pass on atom.Benjamin Kramer2013-10-101-1/+1
* ARM: correct liveness flags during ARMLoadStoreOptTim Northover2013-10-102-0/+117
* Allow non-AVX form of pmovmskb to take a GR64 operand.Craig Topper2013-10-102-0/+6
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