aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Remove tailing whitespacesMichael Liao2013-03-061-14/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176570 91177308-0d34-0410-b5e6-96231b3b80d8
* Give -loop-vectorize an explicit default.Andrew Trick2013-03-061-1/+1
| | | | | | This way, clang -mllvm -print-options shows that the driver is overriding it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176569 91177308-0d34-0410-b5e6-96231b3b80d8
* Memory Dependence Analysis (not mem-dep test) take advantage of ↵Shuxin Yang2013-03-065-7/+55
| | | | | | | | | | | | | | | | | "invariant.load" metadata. The "invariant.load" metadata indicates the memory unit being accessed is immutable. A load annotated with this metadata can be moved across any store. As I am not sure if it is legal to move such loads across barrier/fence, this change dose not allow such transformation. rdar://11311484 Thank Arnold for code review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176562 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Don't shrink allocas when combining with a bitcast.Jim Grosbach2013-03-063-1/+52
| | | | | | | | | | When considering folding a bitcast of an alloca into the alloca itself, make sure we don't shrink the amount of memory being allocated, or things rapidly go sideways. rdar://13324424 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176547 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add a line which checks function name. Rename file.Akira Hatanaka2013-03-061-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176543 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR15355Michael Liao2013-03-0614-119/+199
| | | | | | | | | | | | | | | - Clear 'mayStore' flag when loading from the atomic variable before the spin loop - Clear kill flag from one use to multiple use in registers forming the address to that atomic variable - don't use a physical register as live-in register in BB (neither entry nor landing pad.) by copying it into virtual register (patch by Cameron Zwarich) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176538 91177308-0d34-0410-b5e6-96231b3b80d8
* Use dyn_cast instead of isa && cast. No functionality change.Jakub Staszak2013-03-061-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176537 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove duplicated forward declaration.Jakub Staszak2013-03-061-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176536 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Remove android calling convention.Akira Hatanaka2013-03-055-31/+1
| | | | | | | | | This calling convention was added just to handle functions which return vector of floats. The fix committed in r165585 solves the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176530 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 getsAkira Hatanaka2013-03-053-45/+60
| | | | | | | | returned in registers $2 and $4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176527 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctlyAkira Hatanaka2013-03-053-15/+92
| | | | | | | | handle fp128 returns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176523 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floatingAkira Hatanaka2013-03-053-6/+28
| | | | | | | | point registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176521 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Correct handling of fp128 (long double) formals and read long doubleAkira Hatanaka2013-03-053-9/+92
| | | | | | | | parameters from floating point registers if target is mips64 hard float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176520 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a few typos in comments.Jakub Staszak2013-03-054-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176519 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some constantness.Jakub Staszak2013-03-051-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176518 91177308-0d34-0410-b5e6-96231b3b80d8
* std::distance() == 0 means that iterators are equal. No functionality change.Jakub Staszak2013-03-051-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176516 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more functions to the TLI.Meador Inge2013-03-052-9/+465
| | | | | | | | | | | | This patch adds many more functions to the target library information. All of the functions being added were discovered while doing the migration of the simplify-libcalls attribute annotation functionality to the functionattrs pass. As a part of that work the attribute annotation logic will query TLI to determine if a function should be annotated or not. Signed-off-by: Meador Inge <meadori@codesourcery.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176514 91177308-0d34-0410-b5e6-96231b3b80d8
* reverting patch 176508.Jyotsna Verma2013-03-056-106/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176513 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add support for lowering block address.Jyotsna Verma2013-03-056-0/+106
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Do not predicate vector opVincent Lejeune2013-03-051-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176507 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Expand addc, adde, subc and sube.Jyotsna Verma2013-03-053-0/+86
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176505 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the right number of slashes in comment stringArnold Schwaighofer2013-03-051-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176504 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes a test by replacing .align by .p2align and setting triples explicitly.Eli Bendersky2013-03-051-2/+5
| | | | | | | | Patch by David Sehr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176502 91177308-0d34-0410-b5e6-96231b3b80d8
* Update cmake build.Benjamin Kramer2013-03-051-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176501 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use MO operand flags to mark constant extended instructions.Jyotsna Verma2013-03-053-471/+43
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176500 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add encoding bits to the TFR64 instructions.Jyotsna Verma2013-03-053-25/+51
| | | | | | | | Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: initial scheduler codeVincent Lejeune2013-03-053-1/+624
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a skeleton for a pre-RA MachineInstr scheduler strategy. Currently it only tries to expose more parallelism for ALU instructions (this also makes the distribution of GPR channels more uniform and increases the chances of ALU instructions to be packed together in a single VLIW group). Also it tries to reduce clause switching by grouping instruction of the same kind (ALU/FETCH/CF) together. Vincent Lejeune: - Support for VLIW4 Slot assignement - Recomputation of ScheduleDAG to get more parallelism opportunities Tom Stellard: - Fix assertion failure when trying to determine an instruction's slot based on its destination register's class - Fix some compiler warnings Vincent Lejeune: [v2] - Remove recomputation of ScheduleDAG (will be provided in a later patch) - Improve estimation of an ALU clause size so that heuristic does not emit cf instructions at the wrong position. - Make schedule heuristic smarter using SUnit Depth - Take constant read limitations into account Vincent Lejeune: [v3] - Fix some uninitialized values in ConstPair - Add asserts to ensure an ALU slot is always populated git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176498 91177308-0d34-0410-b5e6-96231b3b80d8
* Clarify comment for function getObjectSizeArnold Schwaighofer2013-03-051-1/+3
| | | | | | | Clarify that we mean the object starting at the pointer to the end of the underlying object and not the size of the whole allocated object. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176491 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test that .align directives on capable processors use long NOPs.David Sehr2013-03-051-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176490 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Remove LowerConstCopyPass and lower CONST_COPY right after ISel.Vincent Lejeune2013-03-055-228/+11
| | | | | | | Maintaining CONST_COPY Instructions until Pre Emit may prevent some ifcvt case and taking them in account for scheduling is difficult for no real benefit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176488 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Turn BUILD_VECTOR into Reg_SequenceVincent Lejeune2013-03-053-4/+32
| | | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176487 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: CONST_ADDRESS node is not marked as mayLoad anymoreVincent Lejeune2013-03-051-1/+1
| | | | | | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> mayLoad complexify scheduling and does not bring any usefull info as the location is not writeable at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176486 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use MUL_IEEE for trig/fdiv intrinsicVincent Lejeune2013-03-052-8/+8
| | | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176485 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add support for indirect addressing of non default const bufferVincent Lejeune2013-03-052-7/+8
| | | | | | NOTE: This is a candidate for the Mesa stable branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176484 91177308-0d34-0410-b5e6-96231b3b80d8
* Print a warning message if compiler-rt can't be built because of old CMake ↵Alexey Samsonov2013-03-051-3/+6
| | | | | | version to make this requirement more visible to users git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176481 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/Mips/mips64-f128.ll: Add explicit ↵NAKAMURA Takumi2013-03-051-1/+1
| | | | | | | | -mtriple=mips64el-unknown-unknown to appease win32. FIXME: Is it expected for win32 to affect mips targets? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176471 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/Thumb/iabs.ll: Add explicit -mtriple=thumb-unknown-unknown ↵NAKAMURA Takumi2013-03-051-1/+1
| | | | | | to appease win32 hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176470 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused #includes.Bill Wendling2013-03-059-9/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176467 91177308-0d34-0410-b5e6-96231b3b80d8
* The current X86 NOP padding uses one long NOP followed by the remainder inDavid Sehr2013-03-052-12/+39
| | | | | | | | | | | | one-byte NOPs. If the processor actually executes those NOPs, as it sometimes does with aligned bundling, this can have a performance impact. From my micro-benchmarks run on my one machine, a 15-byte NOP followed by twelve one-byte NOPs is about 20% worse than a 15 followed by a 12. This patch changes NOP emission to emit as many 15-byte (the maximum) as possible followed by at most one shorter NOP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176464 91177308-0d34-0410-b5e6-96231b3b80d8
* Check isDiscardableIfUnused, rather than hasLocalLinkage, when bumpingLang Hames2013-03-042-3/+26
| | | | | | | | GlobalValue linkage up to ExternalLinkage in the ExtractGV pass. This prevents linkonce and linkonce_odr symbols from being DCE'd. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176459 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Print move instructions.Akira Hatanaka2013-03-0411-44/+44
| | | | | | | | "move $4, $5" is printed instead of "or $4, $5, $zero". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176455 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips specific inline assembler constraint 'R'Jack Carter2013-03-042-0/+14
| | | | | | | | | 'R' An address that can be sued in a non-macro load or store. This patch includes a positive test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176452 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r176381, writing the CHECKs in a more forgiving manner to account forEli Bendersky2013-03-041-14/+12
| | | | | | | running llvm-objdump on Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176443 91177308-0d34-0410-b5e6-96231b3b80d8
* Bypass Slow DividesPreston Gurd2013-03-045-6/+55
| | | | | | | | | | | | | | | | * Only apply divide bypass optimization when not optimizing for size. * Fixed bug caused by constant for 0 value of type Int32, used dividend type to generate the constant instead. * For atom x86-64 apply the divide bypass to use 16-bit divides instead of 64-bit divides when operand values are small enough. * Added lit tests for 64-bit divide bypass. Patch by Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176442 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Clean up datalayout strings so they better match hardware capabilitiesTom Stellard2013-03-042-12/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176439 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips ISD typoJia Liu2013-03-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176426 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Creating a vector from a lane of another.Jim Grosbach2013-03-022-2/+19
| | | | | | | | | | | The VDUP instruction source register doesn't allow a non-constant lane index, so make sure we don't construct a ARM::VDUPLANE node asking it to do so. rdar://13328063 http://llvm.org/bugs/show_bug.cgi?id=13963 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176413 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up code format a bit.Jim Grosbach2013-03-021-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176412 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Trailing whitespace.Jim Grosbach2013-03-021-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176411 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON: Fix v2f32 float intrinsicsArnold Schwaighofer2013-03-022-0/+395
| | | | | | Mark them as expand, they are not legal as our backend does not match them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176410 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-02-19 09:50:13 +0000