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* [Sparc] Implements exception handling in SPARC with DwarfCFI.Venkatraman Govindaraju2013-09-265-4/+138
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191432 91177308-0d34-0410-b5e6-96231b3b80d8
* Implements parsing and emitting of .cfi_window_save in MC.Venkatraman Govindaraju2013-09-269-2/+112
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191431 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-2612-372/+1896
| | | | | | | Patch by Artyom Skrobov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191428 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Allow partial fills in writeNopData()David Majnemer2013-09-262-5/+11
| | | | | | | | | | | | | | | | | | | When asked to pad an irregular number of bytes, we should fill with zeros. This is consistent with the behavior specified in the AIX Assembler Language Reference as well as other LLVM and binutils assemblers. N.B. There is a small deviation from binutils' PPC assembler: when handling pads which are greater than 4 bytes but not mod 4, binutils will not emit any NOP sequences at all and only use zeros. This may or may not be a bug but there is no excellent rationale as to why that behavior is important to emulate. If that behavior is needed, we can change writeNopData() to behave in the same way. This fixes PR17352. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191426 91177308-0d34-0410-b5e6-96231b3b80d8
* Add links to cross-compilation docs from getting startedRenato Golin2013-09-261-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191425 91177308-0d34-0410-b5e6-96231b3b80d8
* Added temp flag -misched-bench for staging in default changes.Andrew Trick2013-09-265-4/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191423 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2013-09-261-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191422 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Do not introduce ISD nodes for fctid and fctiwDavid Majnemer2013-09-263-8/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191421 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Add support for fctid and fctiwDavid Majnemer2013-09-264-8/+20
| | | | | | | | | | Encodings were checked against the Power ISA documents and double checked against binutils. This fixes PR17350. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191419 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission for 3R instructions.Jack Carter2013-09-264-330/+1122
| | | | | | | | | This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191415 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Updates encoding of 3R instructions to match the latest revision ↵Jack Carter2013-09-261-9/+9
| | | | | | | | | | | | of the MSA spec (1.06). Internal changes only. Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191414 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission for 2RF instructions.Jack Carter2013-09-252-41/+126
| | | | | | | Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191413 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission support for the MSA instruction set. Jack Carter2013-09-256-8/+247
| | | | | | | | | | | In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191412 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Updates encoding of 2RF instructions to match the latest ↵Jack Carter2013-09-251-4/+4
| | | | | | | | | | | | | revision of the MSA spec (1.06). This only changes internal encodings and doesn't affect output. Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191411 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR 17368: disable vector mul distribution for square of add/sub for ARMWeiming Zhao2013-09-252-0/+21
| | | | | | | | | | | | | | | | | | | | | Generally, it is desirable to distribute (a + b) * c to a*c + b*c for ARM with VMLx forwarding, where a, b and c are vectors. However, for (a + b)*(a + b), distribution will result in one extra instruction. With distribution: x = a + b (add) y = a * x (mul) z = y + b * y (mla) Without distribution: x = a + b (add) z = x * x (mul) This patch checks if a mul is a square of add/sub. If yes, skip distribution. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191410 91177308-0d34-0410-b5e6-96231b3b80d8
* Add gnu pubsections as options to llvm-dwarfdump.Eric Christopher2013-09-251-0/+2
| | | | | | Argument spelling feedback welcome. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191409 91177308-0d34-0410-b5e6-96231b3b80d8
* Dump the normal dwarf pubtypes section as well.Eric Christopher2013-09-254-20/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191408 91177308-0d34-0410-b5e6-96231b3b80d8
* Unify pubsection/gnu pubsection printing.Eric Christopher2013-09-252-33/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191407 91177308-0d34-0410-b5e6-96231b3b80d8
* Test commit. Removed trailing whitespace.Josh Magee2013-09-251-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191402 91177308-0d34-0410-b5e6-96231b3b80d8
* Slight formatting change for pubnames/pubtypes output.Eric Christopher2013-09-251-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191401 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bad typo in the inline assembly code for mips16 pic fp stubsReed Kotler2013-09-253-15/+36
| | | | | | | | | and make one cosmetic cleanup to make it look the same as gcc in this area; adjusting test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191400 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach DAGCombiner how to canonicalize dags according to the ruleAndrea Di Biagio2013-09-252-0/+201
| | | | | | | | | | | | | (shl (zext (shr A, X)), X) => (zext (shl (shr A, X), X)). The rule only triggers when there are no other uses of the zext to avoid materializing more instructions. This helps the DAGCombiner understand that the shl/shr sequence can then be converted into an and instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191393 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark the x86 machine model as incomplete. PR17367.Andrew Trick2013-09-256-5/+35
| | | | | | | | | | | | Ideally, the machinel model is added at the time the instructions are defined. But many instructions in X86InstrSSE.td still need a model. Without this workaround the scheduler asserts because x86 already has itinerary classes for these instructions, indicating they should be modeled by the scheduler. Since we use the new machine model for other instructions, it expects a new machine model for these too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191391 91177308-0d34-0410-b5e6-96231b3b80d8
* Undefine NetBSD, it may have been defined by an earlier include ofJoerg Sonnenberger2013-09-251-0/+1
| | | | | | | sys/param.h. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191384 91177308-0d34-0410-b5e6-96231b3b80d8
* Set the minimal stack size with msvc when using cmake >= 2.8.11.Rafael Espindola2013-09-251-0/+9
| | | | | | | | | | This makes sure we get the same behavior with all supported cmake versions. Once we support only versions >= 2.8.11 we can experiment with other values or just setting it for some binaries. Patch by Greg Bedwell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191372 91177308-0d34-0410-b5e6-96231b3b80d8
* SLPVectorize: Put horizontal reductions feeding a store under separate flagArnold Schwaighofer2013-09-252-21/+28
| | | | | | | Put them under a separate flag for experimentation. They are more likely to interfere with loop vectorization which happens later in the pass pipeline. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191371 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Define the GR64 low-word logic instructions as pseudo aliases.Richard Sandiford2013-09-258-111/+160
| | | | | | | | | Another patch to avoid duplication of encoding information. Things like NILF, NILL and NILH are used as both 32-bit and 64-bit instructions. Here the 64-bit versions are defined as aliases of the 32-bit ones. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191369 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Add support for treating $ as a reference to the PCDavid Majnemer2013-09-255-3/+28
| | | | | | | | | | | | | | | | | | The binutils assembler supports a mode called DOLLAR_DOT which treats the dollar sign token as a reference to the current program counter if the dollar sign doesn't precede a constant or identifier. This commit adds a new MCAsmInfo flag stating whether or not a given target supports this interpretation of the dollar sign token; by default, this flag is not enabled. Further, enable this flag for PPC. The system assembler for AIX and binutils both support using the dollar sign in this manner. This fixes PR17353. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191368 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Define the call instructions as pseudo aliases.Richard Sandiford2013-09-259-147/+97
| | | | | | | | | Similar to r191364, but for calls. This patch also removes the shortening of BRASL to BRAS within a TU. Doing that was a bit controversial internally, since there's a strong expectation with the z assembler that WYWIWYG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191366 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use subregs for 64-bit truncating storesRichard Sandiford2013-09-254-41/+70
| | | | | | | | | Another patch to reduce the duplication of encoding information. Rather than define separate patterns for truncating 64-bit stores, use the 32-bit stores with a subreg. No behavioral changed intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191365 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Define the return instruction as a pseudo alias of BRRichard Sandiford2013-09-253-8/+23
| | | | | | | | | This is the first of a few patches to reduce the dupliation of encoding information. The return instruction is a normal BR in which one of the registers is fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191364 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add instruction-shortening passRichard Sandiford2013-09-258-8/+193
| | | | | | | | | | | | | | | | | | | | | | When loading immediates into a GR32, the port prefered LHI, followed by LLILH or LLILL, followed by IILF. LHI and IILF are natural 32-bit operations, but LLILH and LLILL also clear the upper 32 bits of the register. This was represented as taking a 32-bit subreg of a 64-bit assignment. Using subregs for something as simple as a move immediate was probably a bad idea. Also, I have patches to add support for the high-word facility, and we don't want something like LLILH and LLILL to stop the high word of the same GPR from being used. This patch therefore uses LHI and IILF to begin with and adds a late machine-specific pass to use LLILH and LLILL if the other half of the register is not live. The high-word patches extend this behavior to IIHF, LLIHL and LLIHH. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191363 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Remove vestigial PCSymbol field from AsmInfoDavid Majnemer2013-09-257-16/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191362 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Fix -Wreturn-type warnings in non-self-hosted build.Evgeniy Stepanov2013-09-251-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191361 91177308-0d34-0410-b5e6-96231b3b80d8
* Try again to fix the MSVC build.Peter Collingbourne2013-09-251-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191359 91177308-0d34-0410-b5e6-96231b3b80d8
* Wrap the #include of <stdbool.h> in an #ifndef __cplusplus.Peter Collingbourne2013-09-251-0/+2
| | | | | | This should fix the MSVC build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191357 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix doxygen comments to use correct function name.Craig Topper2013-09-252-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191356 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace EVT with MVT in CodeGenDAGAPatterns.cpp.Craig Topper2013-09-251-14/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191355 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r191350.Akira Hatanaka2013-09-253-94/+55
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191353 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Move public functions to the beginning of the class definition.Akira Hatanaka2013-09-251-33/+33
| | | | | | | | | No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191352 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Define getTargetNode as a template function.Akira Hatanaka2013-09-253-55/+94
| | | | | | | | | No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191350 91177308-0d34-0410-b5e6-96231b3b80d8
* [PR16882] Ignore noreturn definitions when setting isPhysRegUsed.Quentin Colombet2013-09-252-3/+77
| | | | | | | | | | | | | | | | | | PEI inserts a save/restore sequence for the link register, according to the information it gets from the MachineRegisterInfo. MachineRegisterInfo is populated by the VirtRegMap pass. This pass was not aware of noreturn calls and was registering the definitions of these calls the same way as regular operations. Modify VirtRegPass so that it does not set the isPhysRegUsed information for registers only defined by noreturn calls. The rational is that a noreturn call is the "last instruction" of the program (if it returns the behavior is undefined), so everything that is defined by it cannot be used and will not interfere with anything else. Therefore, it is pointless to account for then. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191349 91177308-0d34-0410-b5e6-96231b3b80d8
* CriticalAntiDepBreaker is no longer needed for armv7 scheduling.Andrew Trick2013-09-254-8/+6
| | | | | | | | | | | | | | | | | This is being disabled because it is no longer needed for performance. It is only used by postRAscheduler which is also planned for removal, and it is implemented with an out-dated view of register liveness. It consideres aliases instead of register units, assumes valid kill flags, and assumes implicit uses on partial register defs. Kill flags and implicit operands are error prone and impossible to verify. We should gradually eliminate dependence on them in the postRA phases. Targets that still benefit from this should move to the MI scheduler. If that doesn't solve the problem, then we should add a hook to regalloc to optimize reload placement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191348 91177308-0d34-0410-b5e6-96231b3b80d8
* MachO: Improve backend diagnostic for overalignment.Jim Grosbach2013-09-241-1/+2
| | | | | | Give the symbol's name and disengage the enchanced crash reporting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191344 91177308-0d34-0410-b5e6-96231b3b80d8
* Move LTO support library to a component, allowing it to be testedPeter Collingbourne2013-09-2420-59/+136
| | | | | | more reliably across platforms. Patch by Tom Roeder! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191343 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing check to SETCC optimization.Eli Friedman2013-09-242-0/+19
| | | | | | PR17338. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191337 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-dwarfdump: add missing opening quotation mark lost in r191330David Blaikie2013-09-241-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191333 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch that forces MergeFunctions pass for clang.Stepan Dyatkovskiy2013-09-241-0/+14
| | | | | | | | | It is temporary patch. We need to keep it in trunk, since it makes easer to test it on buildbots on different platforms. Once we see stable MergeFunctions behaviour with satisfied perfomance, this patch will be removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191331 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-dwarfdump: re-add field formatting for the entry kind lost in r191329David Blaikie2013-09-241-1/+1
| | | | | | CR feedback from Eric Christopher git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191330 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-dwarfdump support for gnu_pubtypesDavid Blaikie2013-09-244-23/+49
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191329 91177308-0d34-0410-b5e6-96231b3b80d8
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